From patchwork Tue Mar 14 05:37:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 117D7C6FD1F for ; Tue, 14 Mar 2023 05:38:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230013AbjCNFiF (ORCPT ); Tue, 14 Mar 2023 01:38:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbjCNFiD (ORCPT ); Tue, 14 Mar 2023 01:38:03 -0400 Received: from mail-pj1-x102e.google.com (mail-pj1-x102e.google.com [IPv6:2607:f8b0:4864:20::102e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BDFB495BF2 for ; Mon, 13 Mar 2023 22:37:40 -0700 (PDT) Received: by mail-pj1-x102e.google.com with SMTP id j3-20020a17090adc8300b0023d09aea4a6so4887800pjv.5 for ; Mon, 13 Mar 2023 22:37:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772260; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e2qLWiEu+kwQHNuuyN9RiYgLYwjEZFKFrGhRPUZl538=; b=BxxSAemif3HMqEBDGRssBokbkkaHm51vUuIzdJK/3H++ZYNX9HnjmVXIIgCVNGJ4xB 4JbzAw5ygYQFgdkjMPKz7Cqupde1QscsZt1N28G8TkGyd/ZNg5hhyEw6Uo0ggqBezmVB uDYxWI7yt5SO7kwY91lKEVf0+uWmjbBsAsmt9ObcXmF6tYQXI6zRbgjWlJx0PKsus2YW 5k8r8Vlv4cfKjbAsSgkXKYBv9Bm+9pvKFNBcDYKsXurGSxp4W58YRjERsu9b4IaWGQHq 2xPs3EB9OBpNz13YCaLeWBP+DlPcTUGEz90Ju0StX8bodB8jJr+dmErzLt6fuFN0F55v kLOg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772260; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e2qLWiEu+kwQHNuuyN9RiYgLYwjEZFKFrGhRPUZl538=; b=putUAVZxtaraYZ/Cfp6v2ZLyGZSlVIC37qbgjQrgwQ5qrCOUwkxKWg5GtxGsutvNwD yWcaO1eIT3iVumiVSEdP/dJ5FuVxwf+LLbTWCJD2h9AflYhpE+rFcbGOgUuShh875V4j lpkkmAY2xIYAegagD9NlEVWkGjUfhKoeh/IDtQMlv/6mO6TMv/ywVJjt70ekzksPi6yk iBKeMf+sNTNfU6usQPRJEjMp3vYxrj9xept2R5Jcd/sR4TE1mWLXLmmW6q1GzeuI48YG u6Zg/6wDedW8jdu5w8a/jLs83f3dKp6VFqKmgcdfOgkjWoZlWSBUoYcHQYaU3S2ec6Xs O4Ew== X-Gm-Message-State: AO0yUKVcG5PPHqgbHWIU9DZffPTqA/42TzPZgpBxxOQLLmL09WfWohnm cLlDHJKOwF5zr9U7+4lvfm6C X-Google-Smtp-Source: AK7set/tW8wGTpZIWi5ofRK6X2Wv0YYAJC3DAVTOdzgj/xECKUeNCPyeIhXQ4KNoQxMfnH3fCqvUoQ== X-Received: by 2002:a17:902:a986:b0:19d:297:f30b with SMTP id bh6-20020a170902a98600b0019d0297f30bmr28982374plb.19.1678772259922; Mon, 13 Mar 2023 22:37:39 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.37.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:37:39 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 01/13] dt-bindings: arm: msm: Update the maintainers for LLCC Date: Tue, 14 Mar 2023 11:07:13 +0530 Message-Id: <20230314053725.13623-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Both Rishabh and Sai have left Qualcomm, and there is no evidence of them maintaining with a new identity. So their entry needs to be removed. Listed Bjorn as the interim maintainer until someone volunteers to maintain this binding. Signed-off-by: Manivannan Sadhasivam Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 38efcad56dbd..6570b808fd0d 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -7,8 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Last Level Cache Controller maintainers: - - Rishabh Bhatnagar - - Sai Prakash Ranjan + - Bjorn Andersson description: | LLCC (Last Level Cache Controller) provides last level of cache memory in SoC, From patchwork Tue Mar 14 05:37:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D8F1C74A5B for ; Tue, 14 Mar 2023 05:38:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230034AbjCNFiG (ORCPT ); Tue, 14 Mar 2023 01:38:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52704 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229709AbjCNFiE (ORCPT ); Tue, 14 Mar 2023 01:38:04 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C73526A429 for ; Mon, 13 Mar 2023 22:37:45 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id k2so7541993pll.8 for ; Mon, 13 Mar 2023 22:37:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E3ynFMYwQcpfXg1vBUZGiwqSjOZbWEHjnhI8PWp4GCE=; b=CKgY+Md7XM2Dq1AiLHTRelpqNfgoCLeHgyr5CE0eZGmaoLW0paAx3qE3HR67mx8o27 RaIdjBQdHGMuUMEWzPyUHya+yzGzgiN6mGSgYqMGb4JwI6wom4ahnePuf+Z9IeoD9+dU Lx1L/umvPfmE8LUfWULFgO5dfdDt4by0lxqBnUJ7ILNB1Gvltg0UabJITh+k5VcWOtT8 +EBQbVhUYEiWj3faoMjM7lZdW2Vn4f03oWYISD4ZL3kCLQiMk5JzgCpY5fIF7/jP5Aqa IAa8s5P1mIxzGKyNNpZUbJzkqPhYZTDsY0ykLduyKMAe56pRLRog6fb7kow+lHI/Q2Gz cvaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772265; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E3ynFMYwQcpfXg1vBUZGiwqSjOZbWEHjnhI8PWp4GCE=; b=g6DkVTzz4ewCrWEbUppuTZWPmE72DHeBaHEa6fWzYn/CPT3lLrD8R1HLOgLFZE00fV 7zfHt+l/pS0QSjyreLBsAIrHc0GuS1LqT5uERsi5xK1h+dHKB7nANSp6b87cQ3DW42qN n64rJ/lCVG4GDTC2JVbRQ/R4K/RYMie6SL4t74z1uIPuLXH+Lo2vkEbtnTBZXIap5RVF AuWcCND5RTL3EN9yAJvrVGV4hnqryOKYaVujolOS4PQFQ4V0dDX8aiXVFPqKW02QT/yw Zl6y43YuDxtDF9b7QaaYVvDNUwqpgNJgxC5tUBR0k5BiVOVkzbZ2aPRLGQpM+dRN9dxK bklg== X-Gm-Message-State: AO0yUKXRmf+WwRo6WMvSMtLi93+DsSd5oKnurPeXpiwQW9yTfwNwbUWB xTIWNJ1P/xCjC7MJ9/9cmmpn X-Google-Smtp-Source: AK7set+KJTFlY6G8yvIbPj2Zp9jor9UT9jln0Kx0keXKthTtTYkhhTa8OTt8TJg4VoPbK7U+aDUGgA== X-Received: by 2002:a17:903:1309:b0:1a0:5d0b:c31e with SMTP id iy9-20020a170903130900b001a05d0bc31emr2332917plb.44.1678772265234; Mon, 13 Mar 2023 22:37:45 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.37.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:37:44 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , Krzysztof Kozlowski Subject: [PATCH v7 02/13] dt-bindings: arm: msm: Fix register regions used for LLCC banks Date: Tue, 14 Mar 2023 11:07:14 +0530 Message-Id: <20230314053725.13623-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org Register regions of the LLCC banks are located at different addresses. Currently, the binding just lists the LLCC0 base address and tries to cover all the banks using a single size. This is entirely wrong as there are other register regions that happen to lie inside the size covered by the binding such as the memory controller and holes. So this needs to be fixed by specifying the base address of individual LLCC banks. This approach will break the existing users of this binding as the register regions are split and the drivers now cannot use LLCC0 register region for accessing rest of the banks (which is wrong anyway). But considering the fact that the binding was wrong from the day one and also the device drivers going wrong by the binding, this breakage is acceptable. Reported-by: Parikshit Pareek Reviewed-by: Krzysztof Kozlowski Signed-off-by: Manivannan Sadhasivam --- .../bindings/arm/msm/qcom,llcc.yaml | 125 ++++++++++++++++-- 1 file changed, 114 insertions(+), 11 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml index 6570b808fd0d..93b977428a14 100644 --- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml @@ -33,14 +33,12 @@ properties: - qcom,sm8550-llcc reg: - items: - - description: LLCC base register region - - description: LLCC broadcast base register region + minItems: 2 + maxItems: 9 reg-names: - items: - - const: llcc_base - - const: llcc_broadcast_base + minItems: 2 + maxItems: 9 interrupts: maxItems: 1 @@ -50,15 +48,120 @@ required: - reg - reg-names +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7180-llcc + - qcom,sm6350-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc7280-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8180x-llcc + - qcom,sc8280xp-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC4 base register region + - description: LLCC5 base register region + - description: LLCC6 base register region + - description: LLCC7 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc4_base + - const: llcc5_base + - const: llcc6_base + - const: llcc7_base + - const: llcc_broadcast_base + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdm845-llcc + - qcom,sm8150-llcc + - qcom,sm8250-llcc + - qcom,sm8350-llcc + - qcom,sm8450-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC1 base register region + - description: LLCC2 base register region + - description: LLCC3 base register region + - description: LLCC broadcast base register region + reg-names: + items: + - const: llcc0_base + - const: llcc1_base + - const: llcc2_base + - const: llcc3_base + - const: llcc_broadcast_base + additionalProperties: false examples: - | #include - system-cache-controller@1100000 { - compatible = "qcom,sdm845-llcc"; - reg = <0x1100000 0x200000>, <0x1300000 0x50000> ; - reg-names = "llcc_base", "llcc_broadcast_base"; - interrupts = ; + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-cache-controller@1100000 { + compatible = "qcom,sdm845-llcc"; + reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; + interrupts = ; + }; }; From patchwork Tue Mar 14 05:37:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D3F97C6FD1F for ; Tue, 14 Mar 2023 05:38:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230084AbjCNFiH (ORCPT ); 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Mon, 13 Mar 2023 22:37:49 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 03/13] arm64: dts: qcom: sdm845: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 11:07:15 +0530 Message-Id: <20230314053725.13623-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SDM845, the size of the LLCC bank 0 needs to be reduced to 0x4500 as there are LLCC BWMON registers located after this range. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 479859bd8ab3..3bf95a12ebb9 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2192,8 +2192,11 @@ uart15: serial@a9c000 { llcc: system-cache-controller@1100000 { compatible = "qcom,sdm845-llcc"; - reg = <0 0x01100000 0 0x31000>, <0 0x01300000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x01100000 0 0x45000>, <0 0x01180000 0 0x50000>, + <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>, + <0 0x01300000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Tue Mar 14 05:37:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA3ADC74A44 for ; Tue, 14 Mar 2023 05:38:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230086AbjCNFiI (ORCPT ); Tue, 14 Mar 2023 01:38:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230080AbjCNFiH (ORCPT ); Tue, 14 Mar 2023 01:38:07 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 63C2E5708E for ; Mon, 13 Mar 2023 22:37:55 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id z11so9003807pfh.4 for ; Mon, 13 Mar 2023 22:37:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5/ORW+ZG5QT+TPocYHNFiE88/XBOJZ36UEuAeSGiS3k=; b=KgC3W5IDzN4LUdbRT3iFN7d0cAncrE4n8ln/gf+4ncvZddm2JS9mfUvfgLPL/FXDH0 YQpXC5an/SOmxd+w9D63Th+6q0X2rbD8JRL9W8t6Bs8TRsqcZF+UaneG/qXuxKngLkjT 0c65N4SjLlCgGEsmbgUOll4b54vbIFmkTjmwJ3ZVkR2NWnspsczsGtkTdjw9Hg/9Yb2O ijJuyLzi7FEoConmYfLnmjSxknrXksP6K2RDG/Yi8SIia2xyTqHx37ppbXvU01sr45Jq +UO6gJgBexQ6SnagtqQp7cKP+6K/KE8UbRktjMinGIsmWmlAz2sEEduIJ+zMu0RuX+7M mYSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772275; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5/ORW+ZG5QT+TPocYHNFiE88/XBOJZ36UEuAeSGiS3k=; b=xzznjvku2kVzusmZ3ocMj0s3HUoERzsKP1fC7gXjWcmWVRuhFd+NhARR2GyykBd9rW hzyS5LTc7L0+2nvSUDDHJNWViwXaC34Yj5V4z7pANrwQlqEFx0S4v3X7HEDX/YgWdQmU 20U/wz4N9FPKqdS+NBe5P+IXWlsY070GmKvBAOApGReKqVjqFrPdUWrTTY/oFm+JWghC Ja90kf42qnWfXMowv2/EpeBZU6i3igOTrH5I3uHrOQub5PJbp1aHJbDUbkwrADKOhwQS Tn8V5QB9K1K9SwjNPgDzSJiO5p6rNYdm3tgobcAsZTaMSelnfsnXofL8FpIEmwrKV0Ig pNHQ== X-Gm-Message-State: AO0yUKVywd8HyxPG60FNwqH221adjjPSKxBtm2BDuiLwW40qZPCeauI2 7EE4A5grEFAALc16seMkTOUNd3y0xPB9IP856Q== X-Google-Smtp-Source: AK7set9Fuyifr5nJGCwVnScD/xsLUCrzuCB4Xh9lAxf7L1n3LAu3JaOKm6JqLiJs2lfcX2ghWLxPDg== X-Received: by 2002:a62:3142:0:b0:5dc:ecea:f650 with SMTP id x63-20020a623142000000b005dceceaf650mr27802545pfx.19.1678772274844; Mon, 13 Mar 2023 22:37:54 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.37.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:37:54 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 04/13] arm64: dts: qcom: sc7180: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 11:07:16 +0530 Message-Id: <20230314053725.13623-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SC7180, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ebfa21e9ed8a..62cc9eb4882d 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -2760,7 +2760,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sc7180-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Tue Mar 14 05:37:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173686 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14CB0C74A44 for ; Tue, 14 Mar 2023 05:38:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230098AbjCNFiW (ORCPT ); Tue, 14 Mar 2023 01:38:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53038 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230131AbjCNFiT (ORCPT ); Tue, 14 Mar 2023 01:38:19 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 086EC1E2B4 for ; Mon, 13 Mar 2023 22:38:00 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id fy10-20020a17090b020a00b0023b4bcf0727so6537146pjb.0 for ; Mon, 13 Mar 2023 22:38:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H3jjAvyClxqCSaG5sOi6OveXFyY33UJ9o9fFaRGOIoU=; b=pTopKsVkrmcnJWqtjzZETiBVVfzs36mxPQet1SSc4HmcKIl/9QrxEYG8b3LT4J9hxb S++6m5piyCfxh/s+J3V0YdwSE7c+YYV23iZ0mGgr/YL01LCbOCZMEo0vcy/0O/xlytSc LagXJ0g5iUX9DCWADWV+i3Zk/rk+wLcMSsytrT5KbHQvuHvToADbxLtkT7wJM4EprV58 HTOVaBE6y7rMUumLYRa/w/fNNySH2+SlPtDX3hI+f8x5aDoIBVak6k0JWY74QCeore1g 2gHtZjtXDBo0bmCMlmh4B2iQnapr2JSJss5eKGyKGfIgjDxJ3I/lxtYx4ZRTXx2zTiFk lVPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772280; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H3jjAvyClxqCSaG5sOi6OveXFyY33UJ9o9fFaRGOIoU=; b=D0lurnegOxs9w2sp+THqRRf654uA9UynIZDlJqiOsNdZH6y5hLgju450zcIzsNrNES AwjkpHPeW4qnAzJNDq8VdmoA1G7kU+seSjNYaPGxoNzRWC8KjJST/mv4YaHw6p2Ng5KY NCGYFXMPb2gS82ewhYiQtoRMCw0N+TEskFzwY3w5CwQcD7FJb+PibCKm2kMIdDEgEeWf wQb0xYrIssxplyL6qJzKAawnPE45Lm787P9UE0pc0qQ3vCRAluSPKix4OmmIgkFfGnNH YSuylSCNGG8RkOxi8mtHzn67zYiXFo9PfA1cozgIvGJ6ev00Qx/5rL3O6q3p3m69CO64 pu4Q== X-Gm-Message-State: AO0yUKWwY9dKFGoer/IfnZqvfaVpCkqzrhUGO+Gn9bfAaGk50/n3tO+o 3GdLUUt3i7q2brSUh4cqVIRK X-Google-Smtp-Source: AK7set+JWC2Y4o/tgD3y+UbDf7MYlD1NuQyiIJm43pesdd21YA1LiY3m1EAQuGngccI30EH6k6HKbA== X-Received: by 2002:a05:6a20:b919:b0:cc:7f86:a804 with SMTP id fe25-20020a056a20b91900b000cc7f86a804mr32705451pzb.6.1678772280120; Mon, 13 Mar 2023 22:38:00 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:37:59 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 05/13] arm64: dts: qcom: sc7280: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 11:07:17 +0530 Message-Id: <20230314053725.13623-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. While at it, let's also fix the size of the llcc_broadcast_base to cover the whole region. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bdcb74925313..afe74db1f5ae 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -3582,8 +3582,9 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sc7280-llcc"; - reg = <0 0x09200000 0 0xd0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Tue Mar 14 05:37:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173687 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FA2EC7618A for ; Tue, 14 Mar 2023 05:38:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230109AbjCNFiZ (ORCPT ); Tue, 14 Mar 2023 01:38:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53778 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230141AbjCNFiU (ORCPT ); Tue, 14 Mar 2023 01:38:20 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DA0F6A9D4 for ; Mon, 13 Mar 2023 22:38:05 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id k2so7542563pll.8 for ; Mon, 13 Mar 2023 22:38:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FI19SzWU19Jvwkg3ef2zRaEcka9BD7PAMWjZH4lQqmU=; b=VehbRZ9HI2q25B4xg7E8Jfa/ygNAp+s0KAwxKx+kKk4J4Vl3IQB7eaQMNY10EVQ7sf N+PnFR8ojSrT36Tji5CIyMz7uzVRX81HaLIewO8I/jL5XdAUTtScqS/MbScm1f2eFCIY Al0ZYjLlnURB8MR+kWkchaULqd3u4Z3SV3kyfxHR5ptJI/LuJ/BPij+UAlt+y6thDUNz imqZcK3EEnImSqiY2HXUHTSAHm5SVeGTvMLW/OGdOBaHikByZVPH0hKWWBwoi8O8L4bh U2KDwF/CQkphEGgN0cqVb4eDmwdOkDn1pT+P8tAain2jdbCtuC+VKWcMabZr68dbr+yI PfFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772285; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FI19SzWU19Jvwkg3ef2zRaEcka9BD7PAMWjZH4lQqmU=; b=NCLKjRr0UMiCTuxkYSkt+2ncAelW9/tmhYkPjpo5t4kLF79vu8cjfivH9yS+fO/fku eF4O4GMV6gYwChDG7YQIICK/lu5TOBYctfZ/fCLAUg9CBWE5n6DAbG/TcyTkQI3sn8Yw le1xiNNdfDZ+YODtdzYxpScWIJk2H7RRksN5W6yBEYpcPV5X7qtubeR0zprWbvgpmijx Z60lwdcZ6RLcWoaC5lnNGnCgxGIt8Piw/D6fKmfw8CHY1CWtjgAuESf0D3kZmhXS8Uup rXEBhQQ34ThohnQO/nmUwqyZQwk1ex2wC5s9anji8zFl3C2fDraG39b2ZX6UFDNB+HRV dRyA== X-Gm-Message-State: AO0yUKUTKiVBDktKpXpEm1sanm4RmAI5szrMYtyWEjOmEsBj8qdmgOml R+mO/ngSA3kMin19NMa0V4anWWm2DgOchFckLQ== X-Google-Smtp-Source: AK7set/eXfChg5Yn1tYaNg26DAfAkIgkEqbtc6Wi/ANEtvdhyowyjk3Djb+lMgwKHQnDaSM7DRmbeQ== X-Received: by 2002:a17:90b:4a04:b0:233:d10f:5236 with SMTP id kk4-20020a17090b4a0400b00233d10f5236mr38003944pjb.28.1678772285127; Mon, 13 Mar 2023 22:38:05 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:38:04 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 06/13] arm64: dts: qcom: sc8280xp: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 11:07:18 +0530 Message-Id: <20230314053725.13623-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index 0d02599d8867..f5262ac64a36 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -2983,8 +2983,14 @@ opp-6 { system-cache-controller@9200000 { compatible = "qcom,sc8280xp-llcc"; - reg = <0 0x09200000 0 0x58000>, <0 0x09600000 0 0x58000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09400000 0 0x58000>, <0 0x09480000 0 0x58000>, + <0 0x09500000 0 0x58000>, <0 0x09580000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc4_base", "llcc5_base", + "llcc6_base", "llcc7_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Tue Mar 14 05:37:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173688 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C413DC6FD1F for ; Tue, 14 Mar 2023 05:38:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230162AbjCNFic (ORCPT ); Tue, 14 Mar 2023 01:38:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230155AbjCNFi3 (ORCPT ); Tue, 14 Mar 2023 01:38:29 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E9ED695BF7 for ; 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So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8150.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi b/arch/arm64/boot/dts/qcom/sm8150.dtsi index fd20096cfc6e..e316a4e4b5aa 100644 --- a/arch/arm64/boot/dts/qcom/sm8150.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi @@ -1772,8 +1772,11 @@ mmss_noc: interconnect@1740000 { system-cache-controller@9200000 { compatible = "qcom,sm8150-llcc"; - reg = <0 0x09200000 0 0x200000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Tue Mar 14 05:37:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173689 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18D24C6FD1F for ; Tue, 14 Mar 2023 05:38:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229934AbjCNFim (ORCPT ); Tue, 14 Mar 2023 01:38:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230200AbjCNFii (ORCPT ); Tue, 14 Mar 2023 01:38:38 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E9D39608D for ; Mon, 13 Mar 2023 22:38:16 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id u3-20020a17090a450300b00239db6d7d47so13994223pjg.4 for ; Mon, 13 Mar 2023 22:38:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KbEuZ8x9epY4wczXQcJX335FU4iMuAmx2Igvv4w4MY4=; b=yA43PiAKeBNB8a9B6Y9lwaxQHQDbCrpQuXRvkAKWd3GnsAjpNQLvvd86Sw3jpAlIhi YUAWNcQJYsrpiLBRZWuxQyGFY3pSGoOvbzw30iINyA2iZrPnYCfJOvYXewyxt6a+A208 hnNdiJcdBR27i3K9Ght+Hhyklf08p/yrCdUGTkf3QtH5VKEA52Hme4euS81EWeXotQWH sEkIRZZgcLbbj0rMN66m9CGeUAAd2Yf1pehASAvozn328yR9qNbUYZ9GS6djpHNuO/Mf xdzzzp2nn5hss7+A65tSlr0czbPvOKcY6r72hg9RxqDYEqe19zXQV+uKZWUfUVrPYCS8 2jsA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772295; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KbEuZ8x9epY4wczXQcJX335FU4iMuAmx2Igvv4w4MY4=; b=DokozxIx2p/PkZlRvw7I2oKfDvZF6DrQu5nkJKCMJ3W1VsvOSNBaHAD6yBl7JdclAo vKp3SE3/LmPwD/dX9J827D4uXG5KTHFt1LtHsucKgBfZ2oHdis7Po/3tM/y/AfqWfkCW Yp3+D/VqFrgYVIoh+t2YgAkubkBrnfagN8xBUX8n/Upo3t2s3b+1xmv71SnmaAvTmClh 9m4w5YKLTeh7GyqSIqB1CuTG2y69EAiHW3J98YOVlKbGnRBtl/6GYpijvTGYrzL4o+i7 9SeDc1yhzL7BG2eCSNYTa+FeEDTSy7TnLt49ROp0Vvwk18ObRT4KUyEs9YjVxLDXZNhq gfRA== X-Gm-Message-State: AO0yUKXp6RNCqd2d3TMmtbqGOeabRPcFNb8bbfKUJSfse3k+lbisuCQG ZM/5217IYKj+k92g66ERf2VZ X-Google-Smtp-Source: AK7set9H6xnqZ0On6L7Kyi90nbJH7+hMfh4yWgx7eNUysp95rLxfqxE7afD+EGpzhePwKw7STUsm9g== X-Received: by 2002:a05:6a21:6da6:b0:cb:e8c6:26a0 with SMTP id wl38-20020a056a216da600b000cbe8c626a0mr48838687pzb.11.1678772295257; Mon, 13 Mar 2023 22:38:15 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.38.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:38:14 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 08/13] arm64: dts: qcom: sm8250: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 11:07:20 +0530 Message-Id: <20230314053725.13623-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8250.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi index 2f0e460acccd..a13cf98b1ac3 100644 --- a/arch/arm64/boot/dts/qcom/sm8250.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi @@ -3559,8 +3559,11 @@ usb_1_dwc3: usb@a600000 { system-cache-controller@9200000 { compatible = "qcom,sm8250-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x50000>, <0 0x09280000 0 0x50000>, + <0 0x09300000 0 0x50000>, <0 0x09380000 0 0x50000>, + <0 0x09600000 0 0x50000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; usb_2: usb@a8f8800 { From patchwork Tue Mar 14 05:37:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173690 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 01C33C6FD1F for ; Tue, 14 Mar 2023 05:38:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230201AbjCNFiv (ORCPT ); Tue, 14 Mar 2023 01:38:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230186AbjCNFip (ORCPT ); Tue, 14 Mar 2023 01:38:45 -0400 Received: from mail-pj1-x1034.google.com (mail-pj1-x1034.google.com [IPv6:2607:f8b0:4864:20::1034]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C03F7BA08 for ; Mon, 13 Mar 2023 22:38:20 -0700 (PDT) Received: by mail-pj1-x1034.google.com with SMTP id cn6so1699049pjb.2 for ; Mon, 13 Mar 2023 22:38:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WM/W3mGHWee04PiGhWaePDSEFLq+5Xz9JBoWs5RSs+4=; b=JzMSob1P4e3VwB0wL6lNs4Pa+MXu0mZYABvUByRuQD9G3tRF3fed1F70Df/U+C5rnt /vjrHfiOXf0cnrJUD+3UiCGbQdM3S2nSrUVZ70QaRO5cUW/xSpS6M9VGjlrB5Hx5txG6 GjZI+B78ehVktIWhsjYQfYVYNVl8jOp01zhoy5wi+7EkchQkvQ18ZabH5aF2H83kTezH ixGX4dRqpYzid8VAn395TqP3IpDv5GdfePsNFytWEnddGeUB5TVWwyEQIBXrDFNQY6G4 gCzNU2WgUtbhG1pYKg5B7CPJLStTgaDmGHqeSDO9LYsBut6u1qzK9eqbUifxkUNY+1oi bZ5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772300; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WM/W3mGHWee04PiGhWaePDSEFLq+5Xz9JBoWs5RSs+4=; b=sBMfMLYoDasqClleQVL2t6isHJwI3Bkxett4pkkle25/Gr3zkd/CVd9lzPJOjdgW6b cK3GcmeW+JwNP6bDOGBR2m7Oh+nzQ8qx7tljY6Qtc2EZtWUX2WV6Qqj8ma0zKYPLwph/ 4W4uZPyJ8v4u1n8o9eYSMxiuOzYxx//zcKokbjRVcCRg+1zUlak+Zkg6Bs5szFtRmezQ HKJdT9DfUQ2B9zikFe7ytRlZGGl7sQlghH8KSuBpw+FsDJqmDievKVWvgNsVx7uu4I81 owSK89SMeX3P6NzScsw3QitIG+YCHW+R7wgCKmGMCBlNht7+sCauynpMIV4cbFMTI8Ar NllQ== X-Gm-Message-State: AO0yUKUlrPtQMgbbqf1sb++jp6FylYB8d64um2/sPFk5xHHGxtOMhjq0 Dm0ge7jQXZ4BEo8MDHGyO9bn X-Google-Smtp-Source: AK7set+O3FjaSdx4s856WeTSbgqP2xfnipXrZ4jwl5Xpb6TCluAKJ//9cVKxjpInG9aYEZvNf5mARw== X-Received: by 2002:a17:90b:1b52:b0:22b:b82a:f3a2 with SMTP id nv18-20020a17090b1b5200b0022bb82af3a2mr37908027pjb.11.1678772300272; Mon, 13 Mar 2023 22:38:20 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.38.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:38:19 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 09/13] arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 11:07:21 +0530 Message-Id: <20230314053725.13623-10-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8350.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi index 1c97e28da6ad..3fefd8cbba6d 100644 --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi @@ -2204,8 +2204,11 @@ gem_noc: interconnect@9100000 { system-cache-controller@9200000 { compatible = "qcom,sm8350-llcc"; - reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, + <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>, + <0 0x09600000 0 0x58000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; }; compute_noc: interconnect@a0c0000 { From patchwork Tue Mar 14 05:37:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173691 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 548B4C74A5B for ; Tue, 14 Mar 2023 05:38:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230135AbjCNFi4 (ORCPT ); Tue, 14 Mar 2023 01:38:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55224 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230178AbjCNFiv (ORCPT ); Tue, 14 Mar 2023 01:38:51 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B0262CDCB for ; Mon, 13 Mar 2023 22:38:26 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id u3-20020a17090a450300b00239db6d7d47so13994535pjg.4 for ; Mon, 13 Mar 2023 22:38:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yqwK6TcGjAz04KGXLoszY4ospGxs4tGDAzQeGyANDbE=; b=ZdG7vKoqgh7TLFE5DkTjS8lZMZZ4fYvaX+ZAa5JUaX7njeWUBsK0TwE9uu4jPM/k6M MRsIUbyomZdq12tYQPcfd0u4jRRxzSYfKlepDEv5yJ7xQ/NyTbrVTHBk0HJBb2rrgOHQ h4TXpL8f8nRKOYYgE0pQtKzpmNomchpoLCqMXl86YKUnIFjuW91rSAv41SnGZFv5WB8k bSJqBrit69KKWEHJErhWCmmhoXtZna+xDxzj4YNfV/Yv1c+s45YgtDWhX+/g/7icbtFU ZuQP0Xep8MpIva7udnuc84/wWudb4TmMDbKQ5ryQkic16bzvNqFTwn3upia/x+sdW42N VS1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772305; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yqwK6TcGjAz04KGXLoszY4ospGxs4tGDAzQeGyANDbE=; b=HR70MGQz/D0TqGQXcWCKrAxAfr00HWYmEC6Ln12jZ71fq4ysr13drnI4FvfvHSLOg9 jZEDwS4j/+d8z0dsAFrZzSN+1KUm4u/3MLrqai+XEACn1U99B6O72FMKvEWgPR6yuQ/A jGZ8Y77UDTQb5NA8m2boQxRn1995V/Qg4UhYt/ey8kBsRXbbx3VltsdY9oDnlVQ8O2U7 /oqVvELwWXaS0qAKiCt5omxwVdHh5NaTW5c4HY2fmdWRO9vd1rsvxRfWYdblQmg9+lGF mMXPPKt2awiOyX77g0cIvV1CUt6VTz+f5fGcjUMh5qCcOdhqN9GmbEqujw4dJqPy4Y29 1AZw== X-Gm-Message-State: AO0yUKVjgugdok0iMk0NllEEb6Kszjzhh+t4z70xVdYIkMtSURYmrD31 A9TpiwMWWrM66oNqpXXM4w9N X-Google-Smtp-Source: AK7set/INcAL/XhbTRZrdf8CPE6qbsudRjLaC2QYDBO0o0H4NLZzIYbtXxXor2+c3PaD2Cdi5tsnDQ== X-Received: by 2002:a17:902:ecc1:b0:19d:ee88:b4d7 with SMTP id a1-20020a170902ecc100b0019dee88b4d7mr45413170plh.25.1678772305294; Mon, 13 Mar 2023 22:38:25 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.38.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:38:24 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 10/13] arm64: dts: qcom: sm8450: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 11:07:22 +0530 Message-Id: <20230314053725.13623-11-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. Reported-by: Parikshit Pareek Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 1a744a33bcf4..636dc6823d4c 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -3981,8 +3981,11 @@ gem_noc: interconnect@19100000 { system-cache-controller@19200000 { compatible = "qcom,sm8450-llcc"; - reg = <0 0x19200000 0 0x580000>, <0 0x19a00000 0 0x80000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg = <0 0x19200000 0 0x80000>, <0 0x19600000 0 0x80000>, + <0 0x19300000 0 0x80000>, <0 0x19700000 0 0x80000>, + <0 0x19a00000 0 0x80000>; + reg-names = "llcc0_base", "llcc1_base", "llcc2_base", + "llcc3_base", "llcc_broadcast_base"; interrupts = ; }; From patchwork Tue Mar 14 05:37:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173692 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52509C74A5B for ; Tue, 14 Mar 2023 05:39:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230215AbjCNFi6 (ORCPT ); Tue, 14 Mar 2023 01:38:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230152AbjCNFiz (ORCPT ); Tue, 14 Mar 2023 01:38:55 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82C3559E1 for ; Mon, 13 Mar 2023 22:38:31 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id y2so14286059pjg.3 for ; Mon, 13 Mar 2023 22:38:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sggevdgcbKkipnWP4TBoy7JyP1Clj0YxXKdQjrw2BUc=; b=yt8ROJAiLtl01UPND6vY+ee9uaQi/8WI/fmaFZjd+WARpr5QhAwJlxkaCLRVUsV45J a/Im2ar7+D6BWDGaYyDPOQYIuvjqwu/lMDtXS6HYLpkOTK9SlaJorjDwY4AiBfuixPgK n+Rrc7U4EyZhLQD5bK8QzEIXujYC7WctbXNgznPZM0GnLDjV+bJeU9+GZTysKDloY9ot 84UquxeZdLt/QYItlA4PEQBvSstAkEaizAiEXJys9iqwHBkANYNFC5UzdTGNtdiun+kN SvOY+stsGovsfH2kC7y74gY7l6XnlJeRuepqSZ8nvcWiIu8+IRjJtfqTfjErVoFSveiE 8c0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772310; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sggevdgcbKkipnWP4TBoy7JyP1Clj0YxXKdQjrw2BUc=; b=yJv8KCMnuTi0e98X9mD9hGfDdHu/VDVXKiF7Roddh0l4RCJvryfGpeD22wPfdCa8of zjJB2OqzwdJrjV8SU6ajNncRNcVgxqGnmMx7R0XoZP6pZObKJYOi0WeRCYvCtScH9GYe DqpWKSqdBqqAkCvEuh0JBgDAeWNbjjJUVr4QK5K9Cx90db7TwlUdQb43Ft7kXCGepSOf uxUILYtXbT96k3JK8VcCoAgUHHY+ObAzdJlgytDISBAKHQYqUzrDfo3vCXQpsN9WqYPQ Yzc6+TeqEjWOFxvipa9Vp46PH1Rj9nV+lN8o2SPsmvJA3PirQ50w4m/4Tg0gwHA95/NQ kaUQ== X-Gm-Message-State: AO0yUKWgTVaqEoNjkRA9JChNAqG+7KD/FNsAQtulv48O8q5fAqZgvHIw 4so4cWGCHOTqwS63TVBBmwwL X-Google-Smtp-Source: AK7set8J2YOqM/obKfneF5oJ4/irJ0MnLg0HnPZ1wHK5/1ZdM7yRo+pq4RNQgDr5hGXicXYW19sPIA== X-Received: by 2002:a05:6a20:4c2a:b0:d4:b5dc:2909 with SMTP id fm42-20020a056a204c2a00b000d4b5dc2909mr3342007pzb.28.1678772310119; Mon, 13 Mar 2023 22:38:30 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.38.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:38:29 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 11/13] arm64: dts: qcom: sm6350: Fix the base addresses of LLCC banks Date: Tue, 14 Mar 2023 11:07:23 +0530 Message-Id: <20230314053725.13623-12-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The LLCC block has several banks each with a different base address and holes in between. So it is not a correct approach to cover these banks with a single offset/size. Instead, the individual bank's base address needs to be specified in devicetree with the exact size. On SM6350, there is only one LLCC bank available. So let's just pass that as "llcc0_base". Reported-by: Parikshit Pareek Tested-by: Luca Weiss Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi index 1e1d366c92c1..63e55579e9c4 100644 --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi @@ -1348,7 +1348,7 @@ dc_noc: interconnect@9160000 { system-cache-controller@9200000 { compatible = "qcom,sm6350-llcc"; reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>; - reg-names = "llcc_base", "llcc_broadcast_base"; + reg-names = "llcc0_base", "llcc_broadcast_base"; }; gem_noc: interconnect@9680000 { From patchwork Tue Mar 14 05:37:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 13173693 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DF36C74A44 for ; Tue, 14 Mar 2023 05:39:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230239AbjCNFjJ (ORCPT ); Tue, 14 Mar 2023 01:39:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230227AbjCNFjB (ORCPT ); Tue, 14 Mar 2023 01:39:01 -0400 Received: from mail-pl1-x635.google.com (mail-pl1-x635.google.com [IPv6:2607:f8b0:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AEDE162FF3 for ; Mon, 13 Mar 2023 22:38:37 -0700 (PDT) Received: by mail-pl1-x635.google.com with SMTP id k2so7543445pll.8 for ; Mon, 13 Mar 2023 22:38:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1678772315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nUusDRy45tnE3HpdbouewJfbkC176V5vp9gS5W4zqOI=; b=zhrN1SROlXfEfmMz3cmRtkdT5LoRkXRh9pIauzB1JbeA0hM22fZtSOsxUkuZSvwEyA PWEnbpxRU0HPqyxr9Dnrt8hxyyoDkYRLEI+5ygY+9gY2tqbz6Tx0FvFExjl4gTwjGpjx cZC/8/s2lO9UxWGSMLEaP6+zLCc5M1fSrB28cnVpYdWoydHfkT9nCke/mq9PAonbFY8k dgqxPfMFsJZ4+AItj3oPe1HatJbdFBGj2zlpSNq/sRALULo+SliAfk+ZEoi7ybUNN0JC BZ5qtB/4QfdAsJ0aWN7NEJSN4Eyz+fkHafKWgzga5OUkiFNxb0roY/TGnYjVhhkfELM/ jACg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678772315; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nUusDRy45tnE3HpdbouewJfbkC176V5vp9gS5W4zqOI=; b=Ln7xp8QoQGxuGfdwzWrcCmFx1ztTd/NP1yBQVYXBd+BHbdf3inOeNOUjcnDXpksnie 7FcMA9Xwl4QWcEIIvNIHfcFg6GyXEScuEvJF7w5ASjwmc3oF9XIp6/qXugyf+Q5FLFwR 6Niv1b9PfuBrCVZlUlGDUug27smMWUw/7cwpabNzEhCJrk9yILz5euB7d3b3M0U1M+E+ m1nBJiw5dE33FOxS0+4DntgnB9kY2834XwVWTg89Y9dzRuvpt0Juo5KDJikDNNHsViY4 BxpgImPA0l+9MHY3P29uetapJjibTTP5mriI33AhCyeFXf9nJXvYq9Nn033OiOXlyILF 5lbg== X-Gm-Message-State: AO0yUKWhve/l/Zkeab9YU6TW9G+IXfIiazz5YmyA3sIGUU5Jgb3wCjY5 7WyrpnxiAVBvpOWG3KZ6zNw+ X-Google-Smtp-Source: AK7set9xLZrKnSqAb3b5q47zu++kSVCw0JssxfuggfVE30w0pEXHimjZWEmRnwS6JlxIuck8yXxHvQ== X-Received: by 2002:a05:6a21:338d:b0:cc:491e:1a1d with SMTP id yy13-20020a056a21338d00b000cc491e1a1dmr13652750pzb.22.1678772315357; Mon, 13 Mar 2023 22:38:35 -0700 (PDT) Received: from localhost.localdomain ([117.217.177.49]) by smtp.gmail.com with ESMTPSA id n126-20020a634084000000b005034a46fbf7sm675093pga.28.2023.03.13.22.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Mar 2023 22:38:34 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam Subject: [PATCH v7 12/13] qcom: llcc/edac: Fix the base address used for accessing LLCC banks Date: Tue, 14 Mar 2023 11:07:24 +0530 Message-Id: <20230314053725.13623-13-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The Qualcomm LLCC/EDAC drivers were using a fixed register stride for accessing the (Control and Status Registers) CSRs of each LLCC bank. This stride only works for some SoCs like SDM845 for which driver support was initially added. But the later SoCs use different register stride that vary between the banks with holes in-between. So it is not possible to use a single register stride for accessing the CSRs of each bank. By doing so could result in a crash. For fixing this issue, let's obtain the base address of each LLCC bank from devicetree and get rid of the fixed stride. This also means, there is no need to rely on reg-names property and the base addresses can be obtained using the index. First index is LLCC bank 0 and last index is LLCC broadcast. If the SoC supports more than one bank, then those need to be defined in devicetree for index from 1..N-1. Reported-by: Parikshit Pareek Tested-by: Luca Weiss Tested-by: Steev Klimaszewski # Thinkpad X13s Tested-by: Andrew Halaney # sa8540p-ride Reviewed-by: Borislav Petkov (AMD) Signed-off-by: Manivannan Sadhasivam --- drivers/edac/qcom_edac.c | 14 +++--- drivers/soc/qcom/llcc-qcom.c | 72 +++++++++++++++++------------- include/linux/soc/qcom/llcc-qcom.h | 6 +-- 3 files changed, 48 insertions(+), 44 deletions(-) diff --git a/drivers/edac/qcom_edac.c b/drivers/edac/qcom_edac.c index 3256254c3722..1d3cc1930a74 100644 --- a/drivers/edac/qcom_edac.c +++ b/drivers/edac/qcom_edac.c @@ -213,7 +213,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) for (i = 0; i < reg_data.reg_cnt; i++) { synd_reg = reg_data.synd_reg + (i * 4); - ret = regmap_read(drv->regmap, drv->offsets[bank] + synd_reg, + ret = regmap_read(drv->regmaps[bank], synd_reg, &synd_val); if (ret) goto clear; @@ -222,8 +222,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) reg_data.name, i, synd_val); } - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.count_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.count_status_reg, &err_cnt); if (ret) goto clear; @@ -233,8 +232,7 @@ dump_syn_reg_values(struct llcc_drv_data *drv, u32 bank, int err_type) edac_printk(KERN_CRIT, EDAC_LLCC, "%s: Error count: 0x%4x\n", reg_data.name, err_cnt); - ret = regmap_read(drv->regmap, - drv->offsets[bank] + reg_data.ways_status_reg, + ret = regmap_read(drv->regmaps[bank], reg_data.ways_status_reg, &err_ways); if (ret) goto clear; @@ -296,8 +294,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) /* Iterate over the banks and look for Tag RAM or Data RAM errors */ for (i = 0; i < drv->num_banks; i++) { - ret = regmap_read(drv->regmap, - drv->offsets[i] + DRP_INTERRUPT_STATUS, + ret = regmap_read(drv->regmaps[i], DRP_INTERRUPT_STATUS, &drp_error); if (!ret && (drp_error & SB_ECC_ERROR)) { @@ -312,8 +309,7 @@ llcc_ecc_irq_handler(int irq, void *edev_ctl) if (!ret) irq_rc = IRQ_HANDLED; - ret = regmap_read(drv->regmap, - drv->offsets[i] + TRP_INTERRUPT_0_STATUS, + ret = regmap_read(drv->regmaps[i], TRP_INTERRUPT_0_STATUS, &trp_error); if (!ret && (trp_error & SB_ECC_ERROR)) { diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 23ce2f78c4ed..72f3f2a9aaa0 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -62,8 +62,6 @@ #define LLCC_TRP_WRSC_CACHEABLE_EN 0x21f2c #define LLCC_TRP_ALGO_CFG8 0x21f30 -#define BANK_OFFSET_STRIDE 0x80000 - #define LLCC_VERSION_2_0_0_0 0x02000000 #define LLCC_VERSION_2_1_0_0 0x02010000 #define LLCC_VERSION_4_1_0_0 0x04010000 @@ -898,8 +896,8 @@ static int qcom_llcc_remove(struct platform_device *pdev) return 0; } -static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, - const char *name) +static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, u8 index, + const char *name) { void __iomem *base; struct regmap_config llcc_regmap_config = { @@ -909,7 +907,7 @@ static struct regmap *qcom_llcc_init_mmio(struct platform_device *pdev, .fast_io = true, }; - base = devm_platform_ioremap_resource_byname(pdev, name); + base = devm_platform_ioremap_resource(pdev, index); if (IS_ERR(base)) return ERR_CAST(base); @@ -927,6 +925,7 @@ static int qcom_llcc_probe(struct platform_device *pdev) const struct llcc_slice_config *llcc_cfg; u32 sz; u32 version; + struct regmap *regmap; drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL); if (!drv_data) { @@ -934,21 +933,51 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; } - drv_data->regmap = qcom_llcc_init_mmio(pdev, "llcc_base"); - if (IS_ERR(drv_data->regmap)) { - ret = PTR_ERR(drv_data->regmap); + /* Initialize the first LLCC bank regmap */ + regmap = qcom_llcc_init_mmio(pdev, 0, "llcc0_base"); + if (IS_ERR(regmap)) { + ret = PTR_ERR(regmap); goto err; } - drv_data->bcast_regmap = - qcom_llcc_init_mmio(pdev, "llcc_broadcast_base"); + cfg = of_device_get_match_data(&pdev->dev); + + ret = regmap_read(regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], &num_banks); + if (ret) + goto err; + + num_banks &= LLCC_LB_CNT_MASK; + num_banks >>= LLCC_LB_CNT_SHIFT; + drv_data->num_banks = num_banks; + + drv_data->regmaps = devm_kcalloc(dev, num_banks, sizeof(*drv_data->regmaps), GFP_KERNEL); + if (!drv_data->regmaps) { + ret = -ENOMEM; + goto err; + } + + drv_data->regmaps[0] = regmap; + + /* Initialize rest of LLCC bank regmaps */ + for (i = 1; i < num_banks; i++) { + char *base = kasprintf(GFP_KERNEL, "llcc%d_base", i); + + drv_data->regmaps[i] = qcom_llcc_init_mmio(pdev, i, base); + if (IS_ERR(drv_data->regmaps[i])) { + ret = PTR_ERR(drv_data->regmaps[i]); + kfree(base); + goto err; + } + + kfree(base); + } + + drv_data->bcast_regmap = qcom_llcc_init_mmio(pdev, i, "llcc_broadcast_base"); if (IS_ERR(drv_data->bcast_regmap)) { ret = PTR_ERR(drv_data->bcast_regmap); goto err; } - cfg = of_device_get_match_data(&pdev->dev); - /* Extract version of the IP */ ret = regmap_read(drv_data->bcast_regmap, cfg->reg_offset[LLCC_COMMON_HW_INFO], &version); @@ -957,15 +986,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) drv_data->version = version; - ret = regmap_read(drv_data->regmap, cfg->reg_offset[LLCC_COMMON_STATUS0], - &num_banks); - if (ret) - goto err; - - num_banks &= LLCC_LB_CNT_MASK; - num_banks >>= LLCC_LB_CNT_SHIFT; - drv_data->num_banks = num_banks; - llcc_cfg = cfg->sct_data; sz = cfg->size; @@ -973,16 +993,6 @@ static int qcom_llcc_probe(struct platform_device *pdev) if (llcc_cfg[i].slice_id > drv_data->max_slices) drv_data->max_slices = llcc_cfg[i].slice_id; - drv_data->offsets = devm_kcalloc(dev, num_banks, sizeof(u32), - GFP_KERNEL); - if (!drv_data->offsets) { - ret = -ENOMEM; - goto err; - } - - for (i = 0; i < num_banks; i++) - drv_data->offsets[i] = i * BANK_OFFSET_STRIDE; - drv_data->bitmap = devm_bitmap_zalloc(dev, drv_data->max_slices, GFP_KERNEL); if (!drv_data->bitmap) { diff --git a/include/linux/soc/qcom/llcc-qcom.h b/include/linux/soc/qcom/llcc-qcom.h index ad1fd718169d..423220e66026 100644 --- a/include/linux/soc/qcom/llcc-qcom.h +++ b/include/linux/soc/qcom/llcc-qcom.h @@ -120,7 +120,7 @@ struct llcc_edac_reg_offset { /** * struct llcc_drv_data - Data associated with the llcc driver - * @regmap: regmap associated with the llcc device + * @regmaps: regmaps associated with the llcc device * @bcast_regmap: regmap associated with llcc broadcast offset * @cfg: pointer to the data structure for slice configuration * @edac_reg_offset: Offset of the LLCC EDAC registers @@ -129,12 +129,11 @@ struct llcc_edac_reg_offset { * @max_slices: max slices as read from device tree * @num_banks: Number of llcc banks * @bitmap: Bit map to track the active slice ids - * @offsets: Pointer to the bank offsets array * @ecc_irq: interrupt for llcc cache error detection and reporting * @version: Indicates the LLCC version */ struct llcc_drv_data { - struct regmap *regmap; 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Mon, 13 Mar 2023 22:38:40 -0700 (PDT) From: Manivannan Sadhasivam To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, bp@alien8.de, tony.luck@intel.com Cc: konrad.dybcio@linaro.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, james.morse@arm.com, mchehab@kernel.org, rric@kernel.org, linux-edac@vger.kernel.org, quic_ppareek@quicinc.com, luca.weiss@fairphone.com, ahalaney@redhat.com, steev@kali.org, Manivannan Sadhasivam , stable@vger.kernel.org Subject: [PATCH v7 13/13] soc: qcom: llcc: Do not create EDAC platform device on SDM845 Date: Tue, 14 Mar 2023 11:07:25 +0530 Message-Id: <20230314053725.13623-14-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> References: <20230314053725.13623-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-edac@vger.kernel.org The platforms based on SDM845 SoC locks the access to EDAC registers in the bootloader. So probing the EDAC driver will result in a crash. Hence, disable the creation of EDAC platform device on all SDM845 devices. The issue has been observed on Lenovo Yoga C630 and DB845c. While at it, also sort the members of `struct qcom_llcc_config` to avoid any holes in-between. Cc: # 5.10 Reported-by: Steev Klimaszewski Signed-off-by: Manivannan Sadhasivam --- drivers/soc/qcom/llcc-qcom.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/drivers/soc/qcom/llcc-qcom.c b/drivers/soc/qcom/llcc-qcom.c index 72f3f2a9aaa0..a5140f19f200 100644 --- a/drivers/soc/qcom/llcc-qcom.c +++ b/drivers/soc/qcom/llcc-qcom.c @@ -120,10 +120,11 @@ struct llcc_slice_config { struct qcom_llcc_config { const struct llcc_slice_config *sct_data; - int size; - bool need_llcc_cfg; const u32 *reg_offset; const struct llcc_edac_reg_offset *edac_reg_offset; + int size; + bool need_llcc_cfg; + bool no_edac; }; enum llcc_reg_offset { @@ -452,6 +453,7 @@ static const struct qcom_llcc_config sdm845_cfg = { .need_llcc_cfg = false, .reg_offset = llcc_v1_reg_offset, .edac_reg_offset = &llcc_v1_edac_reg_offset, + .no_edac = true, }; static const struct qcom_llcc_config sm6350_cfg = { @@ -1011,7 +1013,14 @@ static int qcom_llcc_probe(struct platform_device *pdev) goto err; drv_data->ecc_irq = platform_get_irq_optional(pdev, 0); - if (drv_data->ecc_irq >= 0) { + + /* + * On some platforms, the access to EDAC registers will be locked by + * the bootloader. So probing the EDAC driver will result in a crash. + * Hence, disable the creation of EDAC platform device for the + * problematic platforms. + */ + if (!cfg->no_edac) { llcc_edac = platform_device_register_data(&pdev->dev, "qcom_llcc_edac", -1, drv_data, sizeof(*drv_data));