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Tue, 14 Mar 2023 09:42:25 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT025.mail.protection.outlook.com (10.13.172.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6178.25 via Frontend Transport; Tue, 14 Mar 2023 09:42:25 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 14 Mar 2023 04:42:24 -0500 From: Nava kishore Manne To: , , , , , , , Subject: [PATCH] fpga: zynqmp: Make word align the configuration data Date: Tue, 14 Mar 2023 15:12:22 +0530 Message-ID: <20230314094222.66916-1-nava.kishore.manne@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT025:EE_|CY8PR12MB8196:EE_ X-MS-Office365-Filtering-Correlation-Id: 25c6848b-b32d-4f30-4be9-08db24706b1e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Mar 2023 09:42:25.4360 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25c6848b-b32d-4f30-4be9-08db24706b1e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT025.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB8196 Precedence: bulk List-ID: X-Mailing-List: linux-fpga@vger.kernel.org To avoid unwanted copies at firmware(PMUFW) this patch provides a fix to align programmable logic(PL) configuration data if the data is not word-aligned. To align the configuration data this patch adds a few padding bytes and these additional padding bytes will not create any functional impact on the PL configuration. Signed-off-by: Nava kishore Manne --- drivers/fpga/zynqmp-fpga.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/drivers/fpga/zynqmp-fpga.c b/drivers/fpga/zynqmp-fpga.c index c60f20949c47..70a12dc6e15c 100644 --- a/drivers/fpga/zynqmp-fpga.c +++ b/drivers/fpga/zynqmp-fpga.c @@ -15,6 +15,9 @@ /* Constant Definitions */ #define IXR_FPGA_DONE_MASK BIT(3) +#define DUMMY_PAD_BYTE 0xFF +#define FPGA_WORD_SIZE 4 + /** * struct zynqmp_fpga_priv - Private data structure * @dev: Device data structure @@ -41,18 +44,26 @@ static int zynqmp_fpga_ops_write(struct fpga_manager *mgr, const char *buf, size_t size) { struct zynqmp_fpga_priv *priv; + int word_align, ret, index; dma_addr_t dma_addr; u32 eemi_flags = 0; char *kbuf; - int ret; priv = mgr->priv; + word_align = size % FPGA_WORD_SIZE; + if (word_align) + word_align = FPGA_WORD_SIZE - word_align; + + size = size + word_align; kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, GFP_KERNEL); if (!kbuf) return -ENOMEM; - memcpy(kbuf, buf, size); + for (index = 0; index < word_align; index++) + kbuf[index] = DUMMY_PAD_BYTE; + + memcpy(&kbuf[index], buf, size - index); wmb(); /* ensure all writes are done before initiate FW call */