From patchwork Tue Mar 14 16:49:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBEC0C6FD1F for ; Tue, 14 Mar 2023 16:51:19 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7qc-0005Jv-ES; Tue, 14 Mar 2023 12:50:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qa-0005JG-QI for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:00 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qY-0002bj-IP for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:00 -0400 Received: by mail-ot1-x329.google.com with SMTP id o4-20020a9d6d04000000b00694127788f4so8739140otp.6 for ; Tue, 14 Mar 2023 09:49:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NyW3QIKPbWEcW/stEjEFae0dbXr8H0CnZzp+jGMhTkc=; b=nkVzHaXNH+WPq0G9E8kSvrpNkqRDbEs8Yn2Gg3/9DdTl0pJWrnXZq0XddA1rPwsnzD KvtiH6F1cN1SA+WGFQNqYCol+XDJot8rwpFjk9tNzkYJMa8xKHtQdg8EM6lZ6pbdqhcO lntKCGdkPTfJaCjyZ0aTMzw5IQCy7axz05+rFhA04tbFs9P9WSrD/9n4MBmCw5Z5s4Sl jtGxFFDFqCCbWTrfiM389d0YZ2xAmcSGgy45FEpXtdRHAZApiTXXR7gqwZBEEpfhBxmU UJPK3W9KgzSorssBq0co1aIY19r+2Cc8uE35v0+FA2GRLH0vjhbGtnF+H/yff4aaLair LbqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812597; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NyW3QIKPbWEcW/stEjEFae0dbXr8H0CnZzp+jGMhTkc=; b=hE0RbW/hVCvlfeZheyfCR6xTQnMOy/SoFGPkSe8xEbq1ZDlPoIfFnymVlZpaf+mDiT M6YlPTqQY/ZlUlNl6xmdf70K3EGEDyg/RLBWhAyqs3L7SAtaIU9EJ8e9xAaB+IDNLLMf lE4fzjm5jFKgmbgb9y/bHIFo2ulM/eiGiCjK2BwI689NKd6YPbafHoVlC0vckfgNB8+q 7zwpMoGybVAcF3clm5GfjgsCEyQUHk/2g208oAmL68/qy9EMpcXvC/0FV0FSrtoYrerM i4q66zKML8J9qOpLrak2MjaKO/S7iTBSf7ySM93QrqHGm06hbNRwnav1BFI++L925Y/I CKZA== X-Gm-Message-State: AO0yUKWAectXAc3ltoHNYgY0YipI3vJiFD53nrSiN4Gz6ZoUhqZ2DtGP SXVFS7SAsJtwjcwgLOupv2c18txXm7Wvx2hmZtk= X-Google-Smtp-Source: AK7set+buopGjvfnI0LCaYBcusEjiyI3j0uTGcu5FQrBcbpkMR6J6S8VpLBZLR6XzN15qv71LoUxDw== X-Received: by 2002:a9d:153:0:b0:697:ef66:e7f4 with SMTP id 77-20020a9d0153000000b00697ef66e7f4mr1169965otu.24.1678812597154; Tue, 14 Mar 2023 09:49:57 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.49.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:49:56 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 01/26] target/riscv/cpu.c: add riscv_cpu_validate_v() Date: Tue, 14 Mar 2023 13:49:23 -0300 Message-Id: <20230314164948.539135-2-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The RVV verification will error out if fails and it's being done at the end of riscv_cpu_validate_set_extensions(). Let's put it in its own function and do it earlier. We'll move it out of riscv_cpu_validate_set_extensions() in the near future, but for now this is enough to clean the code a bit. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 86 ++++++++++++++++++++++++++-------------------- 1 file changed, 49 insertions(+), 37 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1e97473af2..18591aa53a 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -802,6 +802,46 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } +static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, + Error **errp) +{ + int vext_version = VEXT_VERSION_1_00_0; + + if (!is_power_of_2(cfg->vlen)) { + error_setg(errp, "Vector extension VLEN must be power of 2"); + return; + } + if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLEN " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cfg->elen)) { + error_setg(errp, "Vector extension ELEN must be power of 2"); + return; + } + if (cfg->elen > 64 || cfg->elen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELEN " + "in the range [8, 64]"); + return; + } + if (cfg->vext_spec) { + if (!g_strcmp0(cfg->vext_spec, "v1.0")) { + vext_version = VEXT_VERSION_1_00_0; + } else { + error_setg(errp, "Unsupported vector spec version '%s'", + cfg->vext_spec); + return; + } + } else { + qemu_log("vector version is not specified, " + "use the default value v1.0\n"); + } + set_vext_version(env, vext_version); +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. @@ -809,6 +849,7 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env = &cpu->env; + Error *local_err = NULL; uint32_t ext = 0; /* Do some ISA extension error checking */ @@ -939,6 +980,14 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } + if (cpu->cfg.ext_v) { + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; @@ -993,44 +1042,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) ext |= RVH; } if (cpu->cfg.ext_v) { - int vext_version = VEXT_VERSION_1_00_0; ext |= RVV; - if (!is_power_of_2(cpu->cfg.vlen)) { - error_setg(errp, - "Vector extension VLEN must be power of 2"); - return; - } - if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { - error_setg(errp, - "Vector extension implementation only supports VLEN " - "in the range [128, %d]", RV_VLEN_MAX); - return; - } - if (!is_power_of_2(cpu->cfg.elen)) { - error_setg(errp, - "Vector extension ELEN must be power of 2"); - return; - } - if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { - error_setg(errp, - "Vector extension implementation only supports ELEN " - "in the range [8, 64]"); - return; - } - if (cpu->cfg.vext_spec) { - if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { - vext_version = VEXT_VERSION_1_00_0; - } else { - error_setg(errp, - "Unsupported vector spec version '%s'", - cpu->cfg.vext_spec); - return; - } - } else { - qemu_log("vector version is not specified, " - "use the default value v1.0\n"); - } - set_vext_version(env, vext_version); } if (cpu->cfg.ext_j) { ext |= RVJ; From patchwork Tue Mar 14 16:49:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174770 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73E79C7618A for ; Tue, 14 Mar 2023 16:53:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7qg-0005Lp-4b; Tue, 14 Mar 2023 12:50:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qd-0005KJ-30 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:03 -0400 Received: from mail-oo1-xc2f.google.com ([2607:f8b0:4864:20::c2f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qb-0002cL-DT for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:02 -0400 Received: by mail-oo1-xc2f.google.com with SMTP id n27-20020a4ad63b000000b005252709efdbso2403906oon.4 for ; Tue, 14 Mar 2023 09:50:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EV5OEE/WdNMUI185IdCQ9kgxw43fPzMUW63mdVe54zA=; b=aVKTnDy634MpT8saqpASr3tczPSnCOXZuXVJNRKbetRghkmlZgPT8iGpmJf16gV7GD C2VzYDMgibJ74E8fPRewk2jO6jQDg4h1pyB5UKI9gVhuPW3g5fLnr18/gxUxwxbprqtx nph0pNalexQfLk6+kJ26My1SrQ1gO4U9ub6ZaaXWf+jfyxs8iBIYNwQcxIDNk6BuwQqi QpdBLX3d4c2asjgxjdiiwhbdr7TzEN9HbLwcgO1IK6Cl5ghUWwwLM2Z6Q4lAY3Enel87 3NoZSOtcqrN3j3cEpEXl6f1TGN1E2kWJyeRVnmzU+xvBLnqb/Q7qSQxOPWeg0KMARuKs caWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812600; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EV5OEE/WdNMUI185IdCQ9kgxw43fPzMUW63mdVe54zA=; b=RibiCUgqtMmo9tmKKJ/r18TxIsLPxHFTHGbrZ34UN5cGzNxP0XZRF9qolFKd14A25L FcRb7MDq0Egg05wPr3s3p8EWHLY6KXldnqjElaTxdTyJ1eXIBbTJDTLlZ28whRHdlRAb MEGmhmYD15t8E2ELqOxKWriok424YeDDp/WJlhDF3XCoR0+fxE25GEn/MuKpzjiZuFIG J1Tfx1lzZCGQcseTPsgpmiUxQUiKb+8gv9ksfCcdFane9tOyDQiUiw4eMqaILYgQiFMi hCA817bq/wIBq4k9yTQSYlHf2Mgu0h71Rjx+apV7vS0S3QgzMBigFcWhTdLO8oEGXRaX XruA== X-Gm-Message-State: AO0yUKWKZlgFvY7SjewoLrI04Iw8qUuN/+MdgQF9D2p8D0YZBNeH3bIH pN+Z70urSyCx6zVZaaz+oJRC2z30b5wtJJpJZYg= X-Google-Smtp-Source: AK7set8PNo0pjDwN1W0QkDtEpYVY93rXUEOZDEWm8X5GeuNDLjGpWrAOcag+4ZVP0g8V6fhBJHjRig== X-Received: by 2002:a05:6820:1522:b0:520:f76:11e2 with SMTP id ay34-20020a056820152200b005200f7611e2mr19104844oob.9.1678812600132; Tue, 14 Mar 2023 09:50:00 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.49.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:49:59 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 02/26] target/riscv/cpu.c: remove set_vext_version() Date: Tue, 14 Mar 2023 13:49:24 -0300 Message-Id: <20230314164948.539135-3-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2f; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This setter is doing nothing else but setting env->vext_ver. Assign the value directly. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 18591aa53a..2752efe1eb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -245,11 +245,6 @@ static void set_priv_version(CPURISCVState *env, int priv_ver) env->priv_ver = priv_ver; } -static void set_vext_version(CPURISCVState *env, int vext_ver) -{ - env->vext_ver = vext_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -839,7 +834,7 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, qemu_log("vector version is not specified, " "use the default value v1.0\n"); } - set_vext_version(env, vext_version); + env->vext_ver = vext_version; } /* From patchwork Tue Mar 14 16:49:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFD87C6FD1F for ; Tue, 14 Mar 2023 16:51:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7qg-0005M0-Pe; Tue, 14 Mar 2023 12:50:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qf-0005Lj-UF for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:05 -0400 Received: from mail-ot1-x331.google.com ([2607:f8b0:4864:20::331]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qe-0002bQ-5F for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:05 -0400 Received: by mail-ot1-x331.google.com with SMTP id w21-20020a9d6755000000b00698853a52c7so768177otm.11 for ; Tue, 14 Mar 2023 09:50:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812603; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=y4yZ3wAir0o7gPbOYm0TNhTOmu7uQyMFvLvYKMxOY/Q=; b=QQqJjv3bB0AT64UkXTDXC6oJ2s2T+/YMGmE3iL7ZkYjTIkDPeT+Jr0Wz4/PHCyGdXg 1CpKr34pJMDGoi6LrBGF480rFe6+TRnePWC9xDfLN+foCzd2TmeStOFzaauQLZf9HRqv 8eOTFSKscLAc1nPnfxD93A0tPsEcISg1Lnj1UBSKkuhYwJC85NPklggL8MMSVrdSOMT5 FPG/ai9R6TD4AWnayBCZzVFfO2MyYcYuVQ/Q6YPUoin1xAm7IqrMXbya1I4fSghJevJm 9L9lnOCk3qjWQF1mb6TgFiFWij/eNfSMMM6F5F3pH5trJKappiptdiQUouSirTHQIIT7 OvUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812603; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y4yZ3wAir0o7gPbOYm0TNhTOmu7uQyMFvLvYKMxOY/Q=; b=Y+poYSP5B/5mHvIzAqgdx8UheXa9YlUiiir46L7CV27OjVWPKxbQGmFLpptWnP4IbZ xSrDdrpTL0XFWWFB3RZsV+gwTethYa7OQWvrO03XQewdcunWcIzvvN6qEowNYhWvecYb D1N7vUmOswNTvZunmbbHHfLV4WGWea7iXw/lqwyKfqbREtmbEr+5LolVsRe9vk0vneAd 2L/Sgiqev/nkPQFZ0ZGffzHSvTdD7GcLMd40JmzZIhBtKs9nqMkHcaURs32/9twU7bvZ WL+1XhXyOPMr28ouCgQpTrvr/SF4hchzrUIJvWvUcqhuuTmMKG/pwevaf5yI2K7ir0Un aaaw== X-Gm-Message-State: AO0yUKXvbOeaS0I5//BrA9Nx87/6hsVtbJ9Uo/oASIeQXWG5b0K4fHYe nhxc52PCyBUAE4w6ulYbfGV8ULpAXXzi6uLUJUQ= X-Google-Smtp-Source: AK7set8Pes9JnGSAlgi8N4NBz/XBFxz3OQffhipcjLqEASgYAOMhc2ORgLGTNHvhnw3QrQmtvpuZJw== X-Received: by 2002:a05:6830:71b:b0:694:88fa:b82f with SMTP id y27-20020a056830071b00b0069488fab82fmr12624360ots.27.1678812603086; Tue, 14 Mar 2023 09:50:03 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:02 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 03/26] target/riscv/cpu.c: remove set_priv_version() Date: Tue, 14 Mar 2023 13:49:25 -0300 Message-Id: <20230314164948.539135-4-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The setter is doing nothing special. Just set env->priv_ver directly. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2752efe1eb..18032dfd4e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -240,11 +240,6 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) env->misa_ext_mask = env->misa_ext = ext; } -static void set_priv_version(CPURISCVState *env, int priv_ver) -{ - env->priv_ver = priv_ver; -} - #ifndef CONFIG_USER_ONLY static uint8_t satp_mode_from_str(const char *satp_mode_str) { @@ -343,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver = PRIV_VERSION_1_12_0; register_cpu_props(obj); } @@ -355,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -366,7 +361,7 @@ static void rv64_sifive_u_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif @@ -379,7 +374,7 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -392,7 +387,7 @@ static void rv64_thead_c906_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver = PRIV_VERSION_1_11_0; cpu->cfg.ext_g = true; cpu->cfg.ext_c = true; @@ -431,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -444,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - set_priv_version(env, PRIV_VERSION_1_12_0); + env->priv_ver = PRIV_VERSION_1_12_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -454,8 +449,9 @@ static void rv32_sifive_u_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif @@ -468,7 +464,7 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -482,7 +478,7 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_11_0); + env->priv_ver = PRIV_VERSION_1_11_0; cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -497,7 +493,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); register_cpu_props(obj); - set_priv_version(env, PRIV_VERSION_1_10_0); + env->priv_ver = PRIV_VERSION_1_10_0; cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -1160,7 +1156,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } if (priv_version >= PRIV_VERSION_1_10_0) { - set_priv_version(env, priv_version); + env->priv_ver = priv_version; } /* Force disable extensions if priv spec version does not match */ From patchwork Tue Mar 14 16:49:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0114EC6FD1F for ; Tue, 14 Mar 2023 16:53:58 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7ql-0005Oz-1w; Tue, 14 Mar 2023 12:50:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qj-0005NK-2R for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:09 -0400 Received: from mail-ot1-x32e.google.com ([2607:f8b0:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qh-0002bO-2e for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:08 -0400 Received: by mail-ot1-x32e.google.com with SMTP id w21-20020a9d6755000000b00698853a52c7so768264otm.11 for ; Tue, 14 Mar 2023 09:50:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LzC32kwhNKZwr0ZLWy81R08TnwzFOSQXtssAv+2bDbg=; b=E14NW/xGqMs6wPcYWpEW+sY6K6Xyj6B/YETVtHlFNfBhiluZaLqmNVkvnPzZSTV+Mm Jv0wt7sYaHSOnuAnK1MbM43WzcNOwWqGIcKAXj+bfrmXfuUzZhXl7n0cVCVVi+p/B/QE NWBL4iJtOumJB7L5ZBIUwFOSFWnXRW/IOTETWwFy2MLcBsuyWtRlZovyLBJ1DrMN/mYS euDZlxt4ustVcKsUhPFCubVo/bg7l372ImdVGA0hU6TVvVSmmLv9WzhLFX9Zvje7p4qz 85K7INYDO9mOSgHuEUDuEvg+xvchO09lzuNt3yuAwppnJv2A7XpWf/0A7dACJNJNTHhv Ot7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812606; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LzC32kwhNKZwr0ZLWy81R08TnwzFOSQXtssAv+2bDbg=; b=CTfZD8K+WMJjQeFxORFIaG61d/oWtbNIt+Nfhc0O9ShrSRwlmMUEiOCNC+DiBGwjyo uDVEpjWc6cv0nqSOQDZKDWGP6uO0BX/NguT9GVIQ1PbzEDRhP9J7FerR0CbPQGJXuVSh fF2enDtedZcZ+SzdbHsKSvQMlvFSdWQDm6XyJEZlFtDTD2PnvJkR6lr/wX9G9kO3e49X UaXp7oGOnCTgAP3E0g/y3EW3aXtcry59yn2rHwrsnEVKVM7oAAfK59sqvDSnGWAFl8wz 9kEbnfLd34Xbx1TYGMmB1mzOT7Tf920/tSi9NN0SZKBJbPlTHg6pKy5j4uLbzrzyNfhb 5m7A== X-Gm-Message-State: AO0yUKUhR1S9yntQTKic67rTRRvsfoEuksGwThBy3GbCRE2ySMuDVzpq xDwLo5q4VmXlQAKdDYPKKuLC/xA810Dx94mkEvk= X-Google-Smtp-Source: AK7set/xAcSMxl3cUNrixp1o5UpPXWHvyVHofmVreGpu8e6zrVTRUVmGoMV2gBYic7LK7T8maIml2g== X-Received: by 2002:a9d:487:0:b0:696:13be:c37a with SMTP id 7-20020a9d0487000000b0069613bec37amr1684137otm.22.1678812606087; Tue, 14 Mar 2023 09:50:06 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 04/26] target/riscv: add PRIV_VERSION_LATEST Date: Tue, 14 Mar 2023 13:49:26 -0300 Message-Id: <20230314164948.539135-5-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org All these generic CPUs are using the latest priv available, at this moment PRIV_VERSION_1_12_0: - riscv_any_cpu_init() - rv32_base_cpu_init() - rv64_base_cpu_init() - rv128_base_cpu_init() Create a new PRIV_VERSION_LATEST enum and use it in those cases. I'll make it easier to update everything at once when a new priv version is available. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 8 ++++---- target/riscv/cpu.h | 2 ++ 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 18032dfd4e..1ee322001b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -338,7 +338,7 @@ static void riscv_any_cpu_init(Object *obj) VM_1_10_SV32 : VM_1_10_SV57); #endif - env->priv_ver = PRIV_VERSION_1_12_0; + env->priv_ver = PRIV_VERSION_LATEST; register_cpu_props(obj); } @@ -350,7 +350,7 @@ static void rv64_base_cpu_init(Object *obj) set_misa(env, MXL_RV64, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - env->priv_ver = PRIV_VERSION_1_12_0; + env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -426,7 +426,7 @@ static void rv128_base_cpu_init(Object *obj) set_misa(env, MXL_RV128, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - env->priv_ver = PRIV_VERSION_1_12_0; + env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif @@ -439,7 +439,7 @@ static void rv32_base_cpu_init(Object *obj) set_misa(env, MXL_RV32, 0); register_cpu_props(obj); /* Set latest version of privileged specification */ - env->priv_ver = PRIV_VERSION_1_12_0; + env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 638e47c75a..76f81c6b68 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -88,6 +88,8 @@ enum { PRIV_VERSION_1_10_0 = 0, PRIV_VERSION_1_11_0, PRIV_VERSION_1_12_0, + + PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0, }; #define VEXT_VERSION_1_00_0 0x00010000 From patchwork Tue Mar 14 16:49:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 70A04C7618A for ; Tue, 14 Mar 2023 16:51:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7qn-0005Pa-Pe; Tue, 14 Mar 2023 12:50:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qm-0005P7-8E for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:12 -0400 Received: from mail-ot1-x335.google.com ([2607:f8b0:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qk-0002q2-Ib for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:12 -0400 Received: by mail-ot1-x335.google.com with SMTP id b26-20020a9d755a000000b006972b28ae37so1312804otl.4 for ; Tue, 14 Mar 2023 09:50:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812609; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9X/RtTs+28g3ykhi3pLH1l3iYUDqblx0oOtf2WwshWM=; b=Otp3pM99YEGJnoUIXg4hQ4qT5uvqb7avcOoonOii15x1xm/xoQM6r8aGVHrsVweJn6 F1MRjn07sW8V7sRVLy2qBDbQi/uSi+de3PYxYxGWul49vh6SKiBSQm9iiZq7gyufgWYD twUUqkbdVrVCLCRgmbZKKaVfNVS0m3H9FJlhEG+QezkAn6NeC3/Q2sLgmMdy2GAWBZOy Rfu2fOV2YOqRINvsAij/iQjngEl2mEzYb1JqDQZYIWiDBvSs/10CEkGxkGo9r3YbjvuK 6alSujiFGfh6mRPqnYPiQjk/Gmht1qbC+AeGIZ0oZiNat901kaCewqFx3gebZ06xcXSC qpEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812609; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9X/RtTs+28g3ykhi3pLH1l3iYUDqblx0oOtf2WwshWM=; b=WllLrQijs3OWLqk67xLIl9xoyNiYURwczm5+BTVnJIsviMB3Qk9szGibq2hxyfolud XlUGXEz/i3wfp4FW/N+3VG1PjuLEgyZtPNEbCIyW/qF2Ke2/yI3q+vw3VamciDb55PuO Vne6NSmb9PRGL9o1SowSyq59pE9r6217Sj1vmjyzcVe5hkaLpMycP/cfAqlOebnFQfRt Vwuq90MUEL9CZhaNBqx41i3C2el3AiZGqwMOCh91nyZjIV6Ss4Nf0qHz/pV8lz+HpEjT CCNRO8Lr9ThEQ/EF+5HMCXrj7zlAWtW9/xNHXajd9glbs3+7KLVJSTLQl8Q0SKbuyrH8 edrw== X-Gm-Message-State: AO0yUKX3HblbGLkbQDNHcxA1ApwpPiKlT7uXbrppsS5ZvrSvX0DPU2k5 q50mpCsLkVTgx5Zj6iQdxZ/p7BPksEe7RSmqI7E= X-Google-Smtp-Source: AK7set9vj8Acp08Ojoo8HPfjgeDlnHd4EcOWoIKhfthdT1rnQonAs8vVhBpofqvn7yrkWsafZaug5g== X-Received: by 2002:a9d:662:0:b0:68d:3fe1:710e with SMTP id 89-20020a9d0662000000b0068d3fe1710emr18469911otn.7.1678812609149; Tue, 14 Mar 2023 09:50:09 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 05/26] target/riscv/cpu.c: add priv_spec validate/disable_exts helpers Date: Tue, 14 Mar 2023 13:49:27 -0300 Message-Id: <20230314164948.539135-6-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We're doing env->priv_spec validation and assignment at the start of riscv_cpu_realize(), which is fine, but then we're doing a force disable on extensions that aren't compatible with the priv version. This second step is being done too early. The disabled extensions might be re-enabled again in riscv_cpu_validate_set_extensions() by accident. A better place to put this code is at the end of riscv_cpu_validate_set_extensions() after all the validations are completed. Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the extesions after the validation is done. While we're at it, create a riscv_cpu_validate_priv_spec() helper to host all env->priv_spec related validation to unclog riscv_cpu_realize a bit. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 91 ++++++++++++++++++++++++++++------------------ 1 file changed, 56 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ee322001b..17b301967c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -833,6 +833,52 @@ static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, env->vext_ver = vext_version; } +static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) +{ + CPURISCVState *env = &cpu->env; + int priv_version = -1; + + if (cpu->cfg.priv_spec) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version = PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + priv_version = PRIV_VERSION_1_11_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { + priv_version = PRIV_VERSION_1_10_0; + } else { + error_setg(errp, + "Unsupported privilege spec version '%s'", + cpu->cfg.priv_spec); + return; + } + + env->priv_ver = priv_version; + } +} + +static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) +{ + CPURISCVState *env = &cpu->env; + int i; + + /* Force disable extensions if priv spec version does not match */ + for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && + (env->priv_ver < isa_edata_arr[i].min_version)) { + isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); +#ifndef CONFIG_USER_ONLY + warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx + " because privilege spec version does not match", + isa_edata_arr[i].name, env->mhartid); +#else + warn_report("disabling %s extension because " + "privilege spec version does not match", + isa_edata_arr[i].name); +#endif + } + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. @@ -1002,6 +1048,12 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zksh = true; } + /* + * Disable isa extensions based on priv spec after we + * validated and set everything we need. + */ + riscv_cpu_disable_priv_spec_isa_exts(cpu); + if (cpu->cfg.ext_i) { ext |= RVI; } @@ -1131,7 +1183,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); CPUClass *cc = CPU_CLASS(mcc); - int i, priv_version = -1; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -1140,40 +1191,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { - priv_version = PRIV_VERSION_1_12_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { - priv_version = PRIV_VERSION_1_11_0; - } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { - priv_version = PRIV_VERSION_1_10_0; - } else { - error_setg(errp, - "Unsupported privilege spec version '%s'", - cpu->cfg.priv_spec); - return; - } - } - - if (priv_version >= PRIV_VERSION_1_10_0) { - env->priv_ver = priv_version; - } - - /* Force disable extensions if priv spec version does not match */ - for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && - (env->priv_ver < isa_edata_arr[i].min_version)) { - isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); -#ifndef CONFIG_USER_ONLY - warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx - " because privilege spec version does not match", - isa_edata_arr[i].name, env->mhartid); -#else - warn_report("disabling %s extension because " - "privilege spec version does not match", - isa_edata_arr[i].name); -#endif - } + riscv_cpu_validate_priv_spec(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; } if (cpu->cfg.epmp && !cpu->cfg.pmp) { From patchwork Tue Mar 14 16:49:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174771 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 3E5D4C05027 for ; Tue, 14 Mar 2023 16:53:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7qq-0005QK-Bz; Tue, 14 Mar 2023 12:50:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qp-0005Q5-7Q for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:15 -0400 Received: from mail-ot1-x32e.google.com ([2607:f8b0:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qn-0002qQ-LV for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:14 -0400 Received: by mail-ot1-x32e.google.com with SMTP id r23-20020a05683001d700b00690eb18529fso8761257ota.1 for ; Tue, 14 Mar 2023 09:50:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=edyvksieWPeu1SW2+k+C41ShJ9HM1xvZ3+am3Bxgf3Y=; b=Ku/pPJ3ifUcvVnhxN4r2/dGMB43qfMdkZlHbM/BfmO4Of4zuc2iFXToDpMFNF9oJoe vHc5j7alpcg9AP3Zp7JNAjJJdt+HvbApH5umxgDFdokIaHcwcQAQCrHWoSd9JE6Qbcw7 Zj07eOcOdU/J69erXHXLmpsuODhncHJqT11oc/Xwl5mZbE8lMCnN28uZ1P0FYCFClyPr P71d/FyN66cI4/83KO5YrhzNM+8vXuBUt6JMR0EpoL+Ce40laPBprK9tSHA+a55/n7by pjyHKrzOlj8vltiKvjMTYORHtAenmyIcDvc/FmpiP7FlRHUuWaSVhLYqmg5ICO97pviE uGWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812612; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=edyvksieWPeu1SW2+k+C41ShJ9HM1xvZ3+am3Bxgf3Y=; b=H8W5uOdur4XikNqUoddFpVjciXxib80uEw+9DsXneoMJ/LNcZ0kERVsDl5Fbjfo+O0 0vIvPVQHnwGwDz3tft/p67jlAfD8lc3t+qgpOEsWTxMKJ1EYrAbNsKbESsO4ki2jnz36 VXc+pZk6YaGKaPUhPwAq/l/PNfHnkZz76KTpMo66YUjmBpqudBZjD6NKVHQQkJYQk3zc 8HyqrPI348kfKl8YmTpcyqEWTfdYi4F46Hl1ZNKbRgbbMVM/a2CX3NZsuOQVCxBkqnVP P7aLWTFnjvWoyE6Y6m+Rimx7BTwT5W+9WIFGnrhI47cr1kiT51FmVD7LvkPZTc0hxeeb MyQA== X-Gm-Message-State: AO0yUKVcZiETc0b7a6I5328j5zK0DFDbiYjwT/q5ZO+bjukW9TjRd6/t SJI7snxDh8we4hKK6ZZFDLITsqONaMS3PrLqCiM= X-Google-Smtp-Source: AK7set9NDg96Wf08CGf2sstvRBf47MNTiZT7aLrn8/C2ZrPIBfwiohHTScOohf/mfdRiqSET9VGkDA== X-Received: by 2002:a05:6830:3687:b0:68b:dfc9:c41c with SMTP id bk7-20020a056830368700b0068bdfc9c41cmr22763230otb.9.1678812612300; Tue, 14 Mar 2023 09:50:12 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:11 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 06/26] target/riscv/cpu.c: add riscv_cpu_validate_misa_mxl() Date: Tue, 14 Mar 2023 13:49:28 -0300 Message-Id: <20230314164948.539135-7-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Let's remove more code that is open coded in riscv_cpu_realize() and put it into a helper. Let's also add an error message instead of just asserting out if env->misa_mxl_max != env->misa_mlx. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 51 ++++++++++++++++++++++++++++++---------------- 1 file changed, 33 insertions(+), 18 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 17b301967c..1a298e5e55 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -879,6 +879,33 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } } +static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) +{ + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); + CPUClass *cc = CPU_CLASS(mcc); + CPURISCVState *env = &cpu->env; + + /* Validate that MISA_MXL is set properly. */ + switch (env->misa_mxl_max) { +#ifdef TARGET_RISCV64 + case MXL_RV64: + case MXL_RV128: + cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; + break; +#endif + case MXL_RV32: + cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; + break; + default: + g_assert_not_reached(); + } + + if (env->misa_mxl_max != env->misa_mxl) { + error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); + return; + } +} + /* * Check consistency between chosen extensions while setting * cpu->cfg accordingly, doing a set_misa() in the end. @@ -1180,9 +1207,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); RISCVCPU *cpu = RISCV_CPU(dev); - CPURISCVState *env = &cpu->env; RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); - CPUClass *cc = CPU_CLASS(mcc); Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -1197,6 +1222,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + riscv_cpu_validate_misa_mxl(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available @@ -1213,22 +1244,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #endif /* CONFIG_USER_ONLY */ - /* Validate that MISA_MXL is set properly. */ - switch (env->misa_mxl_max) { -#ifdef TARGET_RISCV64 - case MXL_RV64: - case MXL_RV128: - cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; - break; -#endif - case MXL_RV32: - cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; - break; - default: - g_assert_not_reached(); - } - assert(env->misa_mxl_max == env->misa_mxl); - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); From patchwork Tue Mar 14 16:49:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 25B69C6FD1F for ; Tue, 14 Mar 2023 16:50:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7qu-0005cM-51; Tue, 14 Mar 2023 12:50:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qs-0005Uv-Hj for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:18 -0400 Received: from mail-oa1-x35.google.com ([2001:4860:4864:20::35]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qr-0002qi-0R for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:18 -0400 Received: by mail-oa1-x35.google.com with SMTP id 586e51a60fabf-17711f56136so17949850fac.12 for ; Tue, 14 Mar 2023 09:50:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=x65YaMF/q551T09YOmWRrKe4JEANKzCqnWd/M7vc3rI=; b=OMgoS9JklXoXl4Fem5uyAGscJ+kGX0hj5e14KHIUTRz1MDNzY3zjeFtfbNGV4NlwEj xe8PENcpDSKmjW4Px7DbZ/pfHziiFJqheZLYYIA/CIEuLAwT8GNdZjVzNjQ7avNaXHNL 3+2XW2KEmhMr+quWWFuMyXQn9bjdyNzLvVmyffGllpO1Euu9UQy4178NQSkGErl48WQx xsqAdei9wd+q5/9scEjebGMzfqQLiCQE6mxt29/aRPiW+34T6V5qYxb0WbUbqPpz11Wu BlmEzO/283T/gRs4oD7JfwtDn7Ymfx/ML0ACF9AXkUdVsEaEhq9eiYugQ7vnRXEEifod 0fRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=x65YaMF/q551T09YOmWRrKe4JEANKzCqnWd/M7vc3rI=; b=BjqLGmtchp/+ahRcbyn7Y8VRIO8z7KIhgXvLvhphKy3wP0I9aEjHzJIsrWL2H2P49a 2H49567JE+mKNJPvTW7x93bpztHuCXTXMpdvcGQHBgONxanIhnuO7GtjMYekP6SZKTb9 6JGRpNbtU/xcMsQporVzM71gIagILSOAhfcuFTIK5neBGkEdU6+Hc3hsUPbOOnuZdBYn +PGDfC0vjypylCF7DkobzmsIhIzOeC57WEdz+c9Qj3T5K/1vgE48eS57OXTvsRjxoWw3 qBcpY+QBKh8ysPpN5L44RiHg16Z1G5Pym4ZfiIlTPSzvQFjSnemGqYhhyiTbArurtZ4k kSlg== X-Gm-Message-State: AO0yUKUN79ShiHYBdw17qZd0p/SYtQQdhBvsaHllneEStYrlpZ8hcF09 LB70R4TRksoXdlQ4FRNBiOJN2NkDjs58E8ocMSY= X-Google-Smtp-Source: AK7set+7CIYv7yQhzU/aIaLMLfYeYa7PwfAPTXhoU9zkLO2wfL4DoV7BzQ2QSuv7QgaPRxSLpgQ32w== X-Received: by 2002:a05:6870:d0c6:b0:17a:a7af:6cf3 with SMTP id k6-20020a056870d0c600b0017aa7af6cf3mr1693734oaa.56.1678812615491; Tue, 14 Mar 2023 09:50:15 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:15 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 07/26] target/riscv: move pmp and epmp validations to validate_set_extensions() Date: Tue, 14 Mar 2023 13:49:29 -0300 Message-Id: <20230314164948.539135-8-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::35; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x35.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the near future, write_misa() will use a variation of what we have now as riscv_cpu_validate_set_extensions(). The pmp and epmp validation will be required in write_misa() and it's already required here in riscv_cpu_realize(), so move it to riscv_cpu_validate_set_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1a298e5e55..7458845fec 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -916,6 +916,15 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) Error *local_err = NULL; uint32_t ext = 0; + if (cpu->cfg.epmp && !cpu->cfg.pmp) { + /* + * Enhanced PMP should only be available + * on harts with PMP support + */ + error_setg(errp, "Invalid configuration: EPMP requires PMP support"); + return; + } + /* Do some ISA extension error checking */ if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && cpu->cfg.ext_a && cpu->cfg.ext_f && @@ -1228,16 +1237,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - if (cpu->cfg.epmp && !cpu->cfg.pmp) { - /* - * Enhanced PMP should only be available - * on harts with PMP support - */ - error_setg(errp, "Invalid configuration: EPMP requires PMP support"); - return; - } - - #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu); From patchwork Tue Mar 14 16:49:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB2E7C05027 for ; Tue, 14 Mar 2023 16:51:49 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7qw-0005fZ-5V; Tue, 14 Mar 2023 12:50:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qv-0005f9-Dn for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:21 -0400 Received: from mail-ot1-x32b.google.com ([2607:f8b0:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qt-0002r9-Tg for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:21 -0400 Received: by mail-ot1-x32b.google.com with SMTP id a4-20020a056830008400b0069432af1380so8726296oto.13 for ; Tue, 14 Mar 2023 09:50:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jEPTSkB86BpaaFtLEftxltn8EEKuvxXM6fE3vNx61Lo=; b=fpWKw43tCsx4KsHBe1RMU0JERuP45w8ETz1ISz01xdUyFhgSDTvfQDChuX8X4wK+ks GJQ9qdOtWNYk+aBaUgAbwPKJEnCL70zshRZIEQvADsVwhtskqdhC4KkRnpDsALcWBGoV jEcEa9Fecgv+7XR5wq6RGBUA7kvNY2cDo9lXjlXy4bfSkkBcsLhZ1AIzwkQKLFElMBQ1 u8ppMttpS8/ZynfJkEpI+PZGEkDXo5ENYPwOVzOiIqYac0Ecf3qaulGilyYW7BLHeW3I WVOZP7IFFJDqKgDGbVIMmUx29zjgxIxNK+ky5Tjz2AWqfM+5MovbX10a+JnOTSLD7zB3 KhEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jEPTSkB86BpaaFtLEftxltn8EEKuvxXM6fE3vNx61Lo=; b=LDNrb1k13QNe3XeFrCKvZ3u6JMRIbqmVuY+41Y1LLvPNksibAqu+iQ17jVeRSTF0iZ SprYdh3cPn9x2x2pFr2qHDejpadqi8/bpA+aq9XQqXONs1Veu9v09ZJmESrz3OZGW9Rd 8emY/OnY4LD5dNx9Q10p+zp1Ayl6+BMUJixSGxOFe7yoAt+SUZDMk8YG3dObWzPnpAHo oHt8aeCianb+gBLNZpBKJ1Ww9VKa08uXfgbpPK2gKiYlUG8YllHX2qaIQcHY7l2PsQIs 6uF71h4ChMLKpV084nTLOBFqLhYgqA7XjpYDCwIDMt78RtPafGIkWK0Wiio08SWTKmT3 VpiA== X-Gm-Message-State: AO0yUKXCYrabnIT+b8y9R2KquPYNS6tbY/EaZ0VNC08xRMTspx8KDQa+ IT48BJ8vk2fQY5S4iwHcTa3gocfedm0rYIJuNQs= X-Google-Smtp-Source: AK7set8/Dv5qXrwIAP4VzTz52mUuIO3F0g5vjQMfVbsVlvpmBlSM0xL1AdLXiSrGtMAB9TUdyNwwlQ== X-Received: by 2002:a9d:6106:0:b0:693:cb03:e7e8 with SMTP id i6-20020a9d6106000000b00693cb03e7e8mr17098118otj.6.1678812618454; Tue, 14 Mar 2023 09:50:18 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:18 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 08/26] target/riscv/cpu.c: validate extensions before riscv_timer_init() Date: Tue, 14 Mar 2023 13:49:30 -0300 Message-Id: <20230314164948.539135-9-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32b; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There is no need to init timers if we're not even sure that our extensions are valid. Execute riscv_cpu_validate_set_extensions() before riscv_timer_init(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7458845fec..fef55d7d79 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1237,12 +1237,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } -#ifndef CONFIG_USER_ONLY - if (cpu->cfg.ext_sstc) { - riscv_timer_init(cpu); - } -#endif /* CONFIG_USER_ONLY */ - riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -1250,6 +1244,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) } #ifndef CONFIG_USER_ONLY + if (cpu->cfg.ext_sstc) { + riscv_timer_init(cpu); + } + if (cpu->cfg.pmu_num) { if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, From patchwork Tue Mar 14 16:49:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE582C05027 for ; Tue, 14 Mar 2023 16:50:59 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7r0-0005jr-PK; Tue, 14 Mar 2023 12:50:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7qy-0005gm-JM for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:24 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7qw-0002rb-TV for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:24 -0400 Received: by mail-ot1-x334.google.com with SMTP id e9-20020a056830200900b00694651d19f6so8720254otp.12 for ; Tue, 14 Mar 2023 09:50:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1LxDIouyTmW6CIiqQuxLm5ivPOp4dewieXsHrUESWZw=; b=Q5n9JiDrqQMWMX5/acvOdZz9gQAEoqZz1DqEB7YswRcLWzomqmXjXqkWBfXDgGceBH GFIoqrjHpVQImnidbMxWk+6V5Xpen1cpvQP0p+esYxjsMQkeGfNenEfVAX8/Q8p4OdZg GY2HqFmUkMT2GBXr/SEICh6+W7d7VEHbHQ5HEQPpptpu8GeZLIOJb933rHIhjwc8ubtq dOm3BvUrYkkILfv7nBM57KUb0mUkRAzoD5smGkMBEIzxhjd+HWggzd8O0WD73CA8P8lU XJEgupDbW2L2I2RkalV9b8lsRu/lhn2BqUCbIEHaGM+F4X7uWkDHGNpuPuarqJprdODW xN3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812621; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1LxDIouyTmW6CIiqQuxLm5ivPOp4dewieXsHrUESWZw=; b=wjww2r4CvtIRUSCkmKbk2VxpL3jsx67oMbumLTO8PVfvfsBnd73Ev6C9pQ7HIx1Hse gjPxObe8RfDd+y4SF44ffMwLz4Zsqd8VrWFboRduC9x6l9S8vMHqFBGrloIUKSoCtey5 pB0OP2MdZ5rlviXg5Y+np3FVMNDFXr2EkIHYtBlVoUHkxDfrBJp30OsfA21ycQ3k1jle 0tkHGoxcDIGjOLctImR5MwZUj4cgEcNcsaqsVVtm+8wKs9o2Q6zIqCNUnN9BVpSZoUkr r7d4gtb8FJMJiC5VBpT4JTzk4bxJI2OjH8I7xkpiMjg7FvsscFVCVAO8fZNCRWDCUi2E u+vQ== X-Gm-Message-State: AO0yUKUMSyxTb9YaRmGjSfgINwKSmaqdgrR98qusJNn4YNO9wzdKnpdb yE2zBZsv7tmhp/fH536nEqtXCvYobefrDhC9dUI= X-Google-Smtp-Source: AK7set/3XFglYTuKoZs/JRDSe9QLEgFdAeGARodl8ivUSBEPQ9ddWS8M1Z7sM9UECQ7toVRhjJJq5g== X-Received: by 2002:a9d:610:0:b0:694:359e:b9c8 with SMTP id 16-20020a9d0610000000b00694359eb9c8mr19729497otn.22.1678812621503; Tue, 14 Mar 2023 09:50:21 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:21 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 09/26] target/riscv/cpu.c: remove cfg setup from riscv_cpu_init() Date: Tue, 14 Mar 2023 13:49:31 -0300 Message-Id: <20230314164948.539135-10-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We have 4 config settings being done in riscv_cpu_init(): ext_ifencei, ext_icsr, mmu and pmp. This is also the constructor of the "riscv-cpu" device, which happens to be the parent device of every RISC-V cpu. The result is that these 4 configs are being set every time, and every other CPU should always account for them. CPUs such as sifive_e need to disable settings that aren't enabled simply because the parent class happens to be enabling it. Moving all configurations from the parent class to each CPU will centralize the config of each CPU into its own init(), which is clearer than having to account to whatever happens to be set in the parent device. These settings are also being set in register_cpu_props() when no 'misa_ext' is set, so for these CPUs we don't need changes. Named CPUs will receive all cfgs that the parent were setting into their init(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++---------- 1 file changed, 48 insertions(+), 12 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fef55d7d79..c7b6e7b84b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -325,7 +325,8 @@ static void set_satp_mode_default_map(RISCVCPU *cpu) static void riscv_any_cpu_init(Object *obj) { - CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; #if defined(TARGET_RISCV32) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #elif defined(TARGET_RISCV64) @@ -340,6 +341,12 @@ static void riscv_any_cpu_init(Object *obj) env->priv_ver = PRIV_VERSION_LATEST; register_cpu_props(obj); + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.mmu = true; + cpu->cfg.pmp = true; } #if defined(TARGET_RISCV64) @@ -358,13 +365,20 @@ static void rv64_base_cpu_init(Object *obj) static void rv64_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.mmu = true; + cpu->cfg.pmp = true; } static void rv64_sifive_e_cpu_init(Object *obj) @@ -375,10 +389,14 @@ static void rv64_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; - cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.pmp = true; } static void rv64_thead_c906_cpu_init(Object *obj) @@ -411,6 +429,10 @@ static void rv64_thead_c906_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_SV39); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei = true; + cpu->cfg.pmp = true; } static void rv128_base_cpu_init(Object *obj) @@ -447,7 +469,8 @@ static void rv32_base_cpu_init(Object *obj) static void rv32_sifive_u_cpu_init(Object *obj) { - CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + CPURISCVState *env = &cpu->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); register_cpu_props(obj); @@ -455,6 +478,12 @@ static void rv32_sifive_u_cpu_init(Object *obj) #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.mmu = true; + cpu->cfg.pmp = true; } static void rv32_sifive_e_cpu_init(Object *obj) @@ -465,10 +494,14 @@ static void rv32_sifive_e_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; - cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.pmp = true; } static void rv32_ibex_cpu_init(Object *obj) @@ -479,11 +512,15 @@ static void rv32_ibex_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_11_0; - cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif cpu->cfg.epmp = true; + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.pmp = true; } static void rv32_imafcu_nommu_cpu_init(Object *obj) @@ -494,10 +531,14 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; - cpu->cfg.mmu = false; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); #endif + + /* inherited from parent obj via riscv_cpu_init() */ + cpu->cfg.ext_ifencei = true; + cpu->cfg.ext_icsr = true; + cpu->cfg.pmp = true; } #endif @@ -1384,11 +1425,6 @@ static void riscv_cpu_init(Object *obj) { RISCVCPU *cpu = RISCV_CPU(obj); - cpu->cfg.ext_ifencei = true; - cpu->cfg.ext_icsr = true; - cpu->cfg.mmu = true; - cpu->cfg.pmp = true; - cpu_set_cpustate_pointers(cpu); #ifndef CONFIG_USER_ONLY From patchwork Tue Mar 14 16:49:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 76063C6FD1F for ; Tue, 14 Mar 2023 16:52:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7r3-0005kt-FS; Tue, 14 Mar 2023 12:50:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7r2-0005kE-0c for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:28 -0400 Received: from mail-oa1-x2b.google.com ([2001:4860:4864:20::2b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7r0-0002tP-99 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:27 -0400 Received: by mail-oa1-x2b.google.com with SMTP id 586e51a60fabf-176eae36feaso17988729fac.6 for ; Tue, 14 Mar 2023 09:50:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KGHUYpVmGV+OzIAgNAop0j4Vk4kPrXqyPo/RElMU7P0=; b=NVhY0krX+sAIZbPDXLRVgDkxHcdEalhTTWyH+e6xZUTt0VaH9EBR8/S84i1yG067L5 1914s9b5RCpRddUpqVfFOViCLBcZ3CColq2gzuaTjowKFZUIUVHJKK+56mHmZ76fF+nQ VJ8KMAoigwkvKPmv1EKAuFGw5VD6S5C3UP1W/CNzCTVP5ltUvPjL1v52wx1m7KhHIv+p J2mABVtbdKtXGCIF0d9FTv3YaiLgwoFu6fEQO49i1lA1co9sDrtHy91WX5U8Jdq5Bu/a llQVg3e5etdi9rd4tl1J5s79g5SSqfdx5d9zkhwD8vQiD+LeZDSd29SWgOdv8/xieI5V dDdQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812624; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KGHUYpVmGV+OzIAgNAop0j4Vk4kPrXqyPo/RElMU7P0=; b=XH7H0c/Fh+no3nM0OWm7ppZhjKQwFHe7lnSmCJe3WQMn/8Ntkt28RTnRUGLxycd95B KV0K01euZUVkui07vtHFBP0xFJiuqi6ee8tYjsG63HS/Y4jIuCpY2GFFlokU93kM+WiZ wpiYarNJExBJLRiN3DcBFrEA8jnvqhok5JkHbhof7fcKL7p5vBYIxJys9ckmtafsy6xI TY3dfVQRZrReXn9YYp/wYjxUdUSCNNdyHLq/2jUj29yByV34GxE/x/xKqwOJAuhkyJL4 QZ9u174NHlCaV79OINkcN8jzDI3UjH5icC3FwdQ1yaeStnbEwvyhkeJtnc+In7Kpbrf1 enwQ== X-Gm-Message-State: AO0yUKVTEAv9USKbavvpurOdpXcQthNCtq68u7K27C2DaV4G5HxoPIUA G+iQxz2u9V0UgvuJHV9/KohvRo6XwCIdoojlkNY= X-Google-Smtp-Source: AK7set/mc19q8UN02Hle/UuD600deeagzwb7KWE1EKmtLfKi+9lJ1QONzrqGmg8W3R75WkF/5KGpMQ== X-Received: by 2002:a05:6871:6a2:b0:172:80f6:9368 with SMTP id l34-20020a05687106a200b0017280f69368mr13707231oao.22.1678812624737; Tue, 14 Mar 2023 09:50:24 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:24 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 10/26] target/riscv/cpu.c: avoid set_misa() in validate_set_extensions() Date: Tue, 14 Mar 2023 13:49:32 -0300 Message-Id: <20230314164948.539135-11-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2b; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org set_misa() will be tuned up to do more than it's already doing and it will be redundant to what riscv_cpu_validate_set_extensions() does. Note that we don't ever change env->misa_mlx in this function, so set_misa() can be replaced by just assigning env->misa_ext and env->misa_ext_mask to 'ext'. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c7b6e7b84b..36c55abda0 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -949,7 +949,8 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, doing a set_misa() in the end. + * cpu->cfg accordingly, setting env->misa_ext and + * misa_ext_mask in the end. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { @@ -1168,7 +1169,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) ext |= RVJ; } - set_misa(env, env->misa_mxl, ext); + env->misa_ext_mask = env->misa_ext = ext; } #ifndef CONFIG_USER_ONLY From patchwork Tue Mar 14 16:49:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 35A1BC05027 for ; Tue, 14 Mar 2023 16:55:08 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7r6-0005ls-4P; Tue, 14 Mar 2023 12:50:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7r4-0005lG-Re for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:30 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7r3-0002tn-4k for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:30 -0400 Received: by mail-ot1-x334.google.com with SMTP id p13-20020a9d744d000000b0069438f0db7eso8752887otk.3 for ; Tue, 14 Mar 2023 09:50:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n1KnuQqgygOO2YMozmY3X/7U/lNxPcvXX1UiChgZSKA=; b=DaoPeFH5NyIpgc9gQtfxzqs1cG+4y9U9QGI06mj/tsjmDMMUaKm6r0SB2Z8e5Rc4W8 VXY4kIUUmkd9XVEmtBV70sEgjfwISkUn8SpQrKWLocbEoeQACxCB57kj5bjkUp+WaU2c EFfPOvbbjJyRfHD9HpNvO0eeTumxA/Bbfy3xHHSiPCQXzkgDncncUxezNRFHvWA6KdKZ jvLyvpndoT82A/Q6z1n0CJuHgj/H4YJWQEkxR68I04GVOtwWOWFDQHBwk0li3mOghiEL JSIg8saxPXLEsZc05PHiXl2RmuUg/BoZ7fSa2H7k3JEYOP8fyAq0dnGWuHXidcnL0+Zd 2+2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812627; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n1KnuQqgygOO2YMozmY3X/7U/lNxPcvXX1UiChgZSKA=; b=Nlan69mjP6/F182idp8f4t3tbOb2TIKyIFkS43J60HqXFMjHxXLk2vun8BWKJYLmHS sTWCS7XyYbDrgQ+vmroFdVQpAZcZX2IdVw9wYPO4UpcNVS7k/MAxo4TQsf09DS36VmTy +wUmw1ffCFuvAwFZMJjj45SZB6Gx1t6aOdaqDG+pRSOdo5IJfuMI/hpsd1vsaya3aClv yDtOiHv5cLedmWXGLRzkctd7JJkwEBzqmcYiNnD9MPKIpAGhtvA7lkl7gMCq3iBjpidN Qp4+3OSOeg3Agh0aZulP6qKPCH8xfD/gpFPOmxtQCoI56T9BQ9kg68YxInHQK09AbAFC Ha7g== X-Gm-Message-State: AO0yUKVgtHDRkjFv02tohpuhre7kBxtlDNsDbYaEIWC0ML5gP2iJvaSn svwWldJpoc+ppwXqNHnZWnUHNHpIpSDHhGGEAKw= X-Google-Smtp-Source: AK7set+1HaF5LMbRnzuvZfjiOtl0SQjMNrrRQ4cDaJ4lD5zdFgzspwQlvkxasec2EfcKmJDKJC6NwA== X-Received: by 2002:a05:6830:912:b0:693:d263:5976 with SMTP id v18-20020a056830091200b00693d2635976mr11251364ott.1.1678812627734; Tue, 14 Mar 2023 09:50:27 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:27 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 11/26] target/riscv/cpu.c: set cpu config in set_misa() Date: Tue, 14 Mar 2023 13:49:33 -0300 Message-Id: <20230314164948.539135-12-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org set_misa() is setting all 'misa' related env states and nothing else. But other functions, namely riscv_cpu_validate_set_extensions(), uses the config object to do its job. This creates a need to set the single letter extensions in the cfg object to keep both in sync. At this moment this is being done by register_cpu_props(), forcing every CPU to do a call to this function. Let's beef up set_misa() and make the function do the sync for us. This will relieve named CPUs to having to call register_cpu_props(), which will then be redesigned to a more specialized role next. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 40 ++++++++++++++++++++++++++++++++-------- target/riscv/cpu.h | 4 ++-- 2 files changed, 34 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 36c55abda0..7841676473 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -236,8 +236,40 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) { + RISCVCPU *cpu; + env->misa_mxl_max = env->misa_mxl = mxl; env->misa_ext_mask = env->misa_ext = ext; + + /* + * ext = 0 will only be a thing during cpu_init() functions + * as a way of setting an extension-agnostic CPU. We do + * not support clearing misa_ext* and the ext_N flags in + * RISCVCPUConfig in regular circunstances. + */ + if (ext == 0) { + return; + } + + /* + * We can't use riscv_cpu_cfg() in this case because it is + * a read-only inline and we're going to change the values + * of cpu->cfg. + */ + cpu = env_archcpu(env); + + cpu->cfg.ext_i = ext & RVI; + cpu->cfg.ext_e = ext & RVE; + cpu->cfg.ext_m = ext & RVM; + cpu->cfg.ext_a = ext & RVA; + cpu->cfg.ext_f = ext & RVF; + cpu->cfg.ext_d = ext & RVD; + cpu->cfg.ext_v = ext & RVV; + cpu->cfg.ext_c = ext & RVC; + cpu->cfg.ext_s = ext & RVS; + cpu->cfg.ext_u = ext & RVU; + cpu->cfg.ext_h = ext & RVH; + cpu->cfg.ext_j = ext & RVJ; } #ifndef CONFIG_USER_ONLY @@ -340,7 +372,6 @@ static void riscv_any_cpu_init(Object *obj) #endif env->priv_ver = PRIV_VERSION_LATEST; - register_cpu_props(obj); /* inherited from parent obj via riscv_cpu_init() */ cpu->cfg.ext_ifencei = true; @@ -368,7 +399,6 @@ static void rv64_sifive_u_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); @@ -387,7 +417,6 @@ static void rv64_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -472,8 +501,6 @@ static void rv32_sifive_u_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); CPURISCVState *env = &cpu->env; set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); - - register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); @@ -492,7 +519,6 @@ static void rv32_sifive_e_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); - register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -510,7 +536,6 @@ static void rv32_ibex_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); - register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_11_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); @@ -529,7 +554,6 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) RISCVCPU *cpu = RISCV_CPU(obj); set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); - register_cpu_props(obj); env->priv_ver = PRIV_VERSION_1_10_0; #ifndef CONFIG_USER_ONLY set_satp_mode_max_supported(cpu, VM_1_10_MBARE); diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 76f81c6b68..ebe0fff668 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,8 +66,8 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) /* - * Consider updating register_cpu_props() when adding - * new MISA bits here. + * Consider updating set_misa() when adding new + * MISA bits here. */ #define RVI RV('I') #define RVE RV('E') /* E and I are mutually exclusive */ From patchwork Tue Mar 14 16:49:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174769 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 50040C05027 for ; Tue, 14 Mar 2023 16:53:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rA-0005nS-B1; Tue, 14 Mar 2023 12:50:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7r8-0005ma-JM for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:34 -0400 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7r6-0002uz-PL for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:34 -0400 Received: by mail-oi1-x236.google.com with SMTP id bi17so12255964oib.3 for ; Tue, 14 Mar 2023 09:50:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CguAyFnXN900gJ747DQtBtymkQ6WmWSHf4CsQ4yPU5I=; b=jZvCh3f5R397M3w+Rc5N9aH52D5cDrJGyeefBkReTZhYY+y2rIWtIciMQrkoMMNE6f 77OG3ZOEmywoD3lC8QS2ashfDnI180QGkgARWr3FFf2aU2bbKlhPrgAAdUEjWdqPYwYZ sxzsYBDpq4Svh56TLp6NOJw6x2qESjLQbteaH6HFk+Ga1spFdX8MrB6dOmv4OIUI8Dzd oChagtBqr0f+qmup70dkOQC1MAsTW8Zjs4H7pgkcwlCsm7P/OP4xiJgu8naPZ+cBPCgh cjmdtEMf2kA8C1bBcG3ljiygbpgzKTDtZIbWBDaK58dGhvdXdEkIjOUPj1HMUGQWoAGe iQpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812630; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CguAyFnXN900gJ747DQtBtymkQ6WmWSHf4CsQ4yPU5I=; b=dPAkf+TwDIzMf1WoGLOE85lfVK1I/Kk+fRG0BHax/ytE78MCu68kw1yNeK7FE9Xzws jprmam5xYePfzBBocI3GHzyeVtk5K5emlYXrYrCgp0tegHkXFdOTpTwFmsAR5dZ48h6J dSeBbh8einCCPnDzdJLE8Yy9hww19+zJDgWXKz0ZTdOuDqlmgVXkCUlX6RsjX101YUtN 79lnufZRTToUhCqhlo+jMWaXZWiB3LlwzrrNqbx/IqiE5eiE1dWRwDq6hqaf3M+KSyT9 KPojOrQQqNIotrVoB7eMZeewosnqfBYUSflbbqRrEOL87AW1NJQifRKbAhE1NO4NO8+V dEaQ== X-Gm-Message-State: AO0yUKVMAEXpUqmynUo4PCU2XOrhtXTw8aiXIcys+eIussxDmJNM5jvg NepekbSJICvcaKcCHehiUuy3LrscmMfBU6/hIfE= X-Google-Smtp-Source: AK7set9yrCyWA4Ns7p2siXy+faTCMHM8pblMB0143VcuPCbKZMO94Y8hIKJvAIPHtJuTXBNt7osynA== X-Received: by 2002:aca:d09:0:b0:384:36f2:5109 with SMTP id 9-20020aca0d09000000b0038436f25109mr17433185oin.6.1678812630648; Tue, 14 Mar 2023 09:50:30 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:30 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 12/26] target/riscv/cpu.c: redesign register_cpu_props() Date: Tue, 14 Mar 2023 13:49:34 -0300 Message-Id: <20230314164948.539135-13-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that the function is a no-op if 'env.misa_ext != 0', and no one that are setting misa_ext != 0 is calling it because set_misa() is setting the cpu cfg accordingly, remove the now deprecated code and rename the function to register_generic_cpu_props(). This function is now doing exactly what the name says: it is creating user-facing properties to allow changes in the CPU cfg via the QEMU command line, setting default values if no user input is provided. Note that there's the possibility of a CPU to set a certain misa value and, at the same, also want user-facing flags and defaults from this function. This is not the case since commit 26b2bc58599c ("target/riscv: Don't expose the CPU properties on names CPUs"), but given that this is also a possibility, clarify in the function that using this function will overwrite existing values in cpu->cfg. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 48 ++++++++++------------------------------------ 1 file changed, 10 insertions(+), 38 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 7841676473..6b5096d25e 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -221,7 +221,7 @@ static const char * const riscv_intr_names[] = { "reserved" }; -static void register_cpu_props(Object *obj); +static void register_generic_cpu_props(Object *obj); const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) { @@ -386,7 +386,7 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); - register_cpu_props(obj); + register_generic_cpu_props(obj); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -475,7 +475,7 @@ static void rv128_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV128, 0); - register_cpu_props(obj); + register_generic_cpu_props(obj); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -488,7 +488,7 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env = &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); - register_cpu_props(obj); + register_generic_cpu_props(obj); /* Set latest version of privileged specification */ env->priv_ver = PRIV_VERSION_LATEST; #ifndef CONFIG_USER_ONLY @@ -575,7 +575,7 @@ static void riscv_host_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, 0); #endif - register_cpu_props(obj); + register_generic_cpu_props(obj); } #endif @@ -1557,44 +1557,16 @@ static Property riscv_cpu_extensions[] = { }; /* - * Register CPU props based on env.misa_ext. If a non-zero - * value was set, register only the required cpu->cfg.ext_* - * properties and leave. env.misa_ext = 0 means that we want - * all the default properties to be registered. + * Register generic CPU props with user-facing flags declared + * in riscv_cpu_extensions[]. + * + * Note that this will overwrite existing values in cpu->cfg. */ -static void register_cpu_props(Object *obj) +static void register_generic_cpu_props(Object *obj) { - RISCVCPU *cpu = RISCV_CPU(obj); - uint32_t misa_ext = cpu->env.misa_ext; Property *prop; DeviceState *dev = DEVICE(obj); - /* - * If misa_ext is not zero, set cfg properties now to - * allow them to be read during riscv_cpu_realize() - * later on. - */ - if (cpu->env.misa_ext != 0) { - cpu->cfg.ext_i = misa_ext & RVI; - cpu->cfg.ext_e = misa_ext & RVE; - cpu->cfg.ext_m = misa_ext & RVM; - cpu->cfg.ext_a = misa_ext & RVA; - cpu->cfg.ext_f = misa_ext & RVF; - cpu->cfg.ext_d = misa_ext & RVD; - cpu->cfg.ext_v = misa_ext & RVV; - cpu->cfg.ext_c = misa_ext & RVC; - cpu->cfg.ext_s = misa_ext & RVS; - cpu->cfg.ext_u = misa_ext & RVU; - cpu->cfg.ext_h = misa_ext & RVH; - cpu->cfg.ext_j = misa_ext & RVJ; - - /* - * We don't want to set the default riscv_cpu_extensions - * in this case. - */ - return; - } - for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { qdev_property_add_static(dev, prop); } From patchwork Tue Mar 14 16:49:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B5410C05027 for ; Tue, 14 Mar 2023 16:51:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rC-0005oO-BG; Tue, 14 Mar 2023 12:50:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rA-0005na-FD for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:36 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7r8-0002tn-O9 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:36 -0400 Received: by mail-ot1-x334.google.com with SMTP id p13-20020a9d744d000000b0069438f0db7eso8753030otk.3 for ; Tue, 14 Mar 2023 09:50:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=oYMlE/F1S0n9ko7FKmrIGnYN/pdSAseR81vgrE7fIjY=; b=iz6Q/HzY9A8Iq0JiWP3kdbgXLdhRbKgy0wC7PSxZtR/9uYNJyIrU+xw1QhpYdbNl3R zLayJC5ceEvHiWlE+n49j23AQyRCzI1yUCPxYClzQg083ts4OhaylyRcEXonNoct5hsV q7fLRBS7eaXSrdaJK9hMEoZDaqLSMvVuevytn1dVGwhSVetIY/4yPRNq2bsYazElIftW 2ShQzj2N+zULcnCi5xObZVYtTq306M2uPKAbUgWXyHFad0BZIE2JdIO9buLiRF4hbzxU 5d1WmzzbwLdVJTigvBivspTddtExKXfjUyfF0jjpjZDrhNGQZN75FykN8kq/Wtedo9Ph UyMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812633; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=oYMlE/F1S0n9ko7FKmrIGnYN/pdSAseR81vgrE7fIjY=; b=ie397kxC8JVlUy85iPX7925K/4Q8WpoEQbIne9Ge5Ni3p9UOTn6m8RrKJudu+hno65 ZFCO4qHKgHRKtNZnMPrOAG/AnlIdNIU2UVFtDhWQveYwifmnUSlBd77nzSw+yMvXPqS9 kXhVNi6BKpK8WXuhD9adfZgvtjHMOps83cYI7XJ/T0ADcrQu+KCxpGXR0PxbuArjt7Rx YG9+E0Y5X+rD6P2HgTXlnIxogua7gpeVO8Wtq54IF2qcw5RC9w/lKbH4jykHWzpUmo/U n+ab/+1/9EDIdw0Ar9VZjjWdiiS9QusP2c5vYYhMVqv4gw5XzaoOBaSN0JWkY2T777Ae KgxQ== X-Gm-Message-State: AO0yUKUQ2HEP3yHkk+m3qtUMiTDqWTEUzwcoPW2C9Kijqc2tc7bQLxyd 5HlwxkzWOrSWVKNPdhBH8fm6TULcDyYm7MHxJ8A= X-Google-Smtp-Source: AK7set9YNR3zbPeh6kI/YAfAtPUldmbDTsFwaC5vTo2gzE9x25WXJK5pQbzRkUxVaKC+OI6lgS4ZuA== X-Received: by 2002:a9d:5f9d:0:b0:694:2f51:129b with SMTP id g29-20020a9d5f9d000000b006942f51129bmr17465901oti.24.1678812633643; Tue, 14 Mar 2023 09:50:33 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:33 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 13/26] target/riscv: put env->misa_ext <-> cpu->cfg code into helpers Date: Tue, 14 Mar 2023 13:49:35 -0300 Message-Id: <20230314164948.539135-14-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The extremely tedious code that sets cpu->cfg based on misa_ext, and vice-versa, is scattered around riscv_cpu_validate_set_extensions() and set_misa(). Introduce helpers to do this work, cleaning up the logic of both functions a bit. While we're at it, add a note in cpu.h informing that any future change in MISA RV* bits should also be reflected in the helpers as well. We'll want to keep env->misa_ext changes in sync with cpu->cfg during realize() in the next patches, and both helpers will have a role to play in that. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 120 ++++++++++++++++++++++++--------------------- target/riscv/cpu.h | 3 +- 2 files changed, 65 insertions(+), 58 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b5096d25e..28d4c5f768 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -234,10 +234,69 @@ const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) } } -static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg) { - RISCVCPU *cpu; + uint32_t ext = 0; + if (cfg->ext_i) { + ext |= RVI; + } + if (cfg->ext_e) { + ext |= RVE; + } + if (cfg->ext_m) { + ext |= RVM; + } + if (cfg->ext_a) { + ext |= RVA; + } + if (cfg->ext_f) { + ext |= RVF; + } + if (cfg->ext_d) { + ext |= RVD; + } + if (cfg->ext_c) { + ext |= RVC; + } + if (cfg->ext_s) { + ext |= RVS; + } + if (cfg->ext_u) { + ext |= RVU; + } + if (cfg->ext_h) { + ext |= RVH; + } + if (cfg->ext_v) { + ext |= RVV; + } + if (cfg->ext_j) { + ext |= RVJ; + } + + return ext; +} + +static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, + uint32_t misa_ext) +{ + cfg->ext_i = misa_ext & RVI; + cfg->ext_e = misa_ext & RVE; + cfg->ext_m = misa_ext & RVM; + cfg->ext_a = misa_ext & RVA; + cfg->ext_f = misa_ext & RVF; + cfg->ext_d = misa_ext & RVD; + cfg->ext_v = misa_ext & RVV; + cfg->ext_c = misa_ext & RVC; + cfg->ext_s = misa_ext & RVS; + cfg->ext_u = misa_ext & RVU; + cfg->ext_h = misa_ext & RVH; + cfg->ext_j = misa_ext & RVJ; +} + +static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) +{ env->misa_mxl_max = env->misa_mxl = mxl; env->misa_ext_mask = env->misa_ext = ext; @@ -251,25 +310,7 @@ static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) return; } - /* - * We can't use riscv_cpu_cfg() in this case because it is - * a read-only inline and we're going to change the values - * of cpu->cfg. - */ - cpu = env_archcpu(env); - - cpu->cfg.ext_i = ext & RVI; - cpu->cfg.ext_e = ext & RVE; - cpu->cfg.ext_m = ext & RVM; - cpu->cfg.ext_a = ext & RVA; - cpu->cfg.ext_f = ext & RVF; - cpu->cfg.ext_d = ext & RVD; - cpu->cfg.ext_v = ext & RVV; - cpu->cfg.ext_c = ext & RVC; - cpu->cfg.ext_s = ext & RVS; - cpu->cfg.ext_u = ext & RVU; - cpu->cfg.ext_h = ext & RVH; - cpu->cfg.ext_j = ext & RVJ; + riscv_set_cpucfg_with_misa(&env_archcpu(env)->cfg, ext); } #ifndef CONFIG_USER_ONLY @@ -1156,42 +1197,7 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) */ riscv_cpu_disable_priv_spec_isa_exts(cpu); - if (cpu->cfg.ext_i) { - ext |= RVI; - } - if (cpu->cfg.ext_e) { - ext |= RVE; - } - if (cpu->cfg.ext_m) { - ext |= RVM; - } - if (cpu->cfg.ext_a) { - ext |= RVA; - } - if (cpu->cfg.ext_f) { - ext |= RVF; - } - if (cpu->cfg.ext_d) { - ext |= RVD; - } - if (cpu->cfg.ext_c) { - ext |= RVC; - } - if (cpu->cfg.ext_s) { - ext |= RVS; - } - if (cpu->cfg.ext_u) { - ext |= RVU; - } - if (cpu->cfg.ext_h) { - ext |= RVH; - } - if (cpu->cfg.ext_v) { - ext |= RVV; - } - if (cpu->cfg.ext_j) { - ext |= RVJ; - } + ext = riscv_get_misa_ext_with_cpucfg(&cpu->cfg); env->misa_ext_mask = env->misa_ext = ext; } diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ebe0fff668..2263629332 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -66,7 +66,8 @@ #define RV(x) ((target_ulong)1 << (x - 'A')) /* - * Consider updating set_misa() when adding new + * Consider updating riscv_get_misa_ext_with_cpucfg() + * and riscv_set_cpucfg_with_misa() when adding new * MISA bits here. */ #define RVI RV('I') From patchwork Tue Mar 14 16:49:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174762 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1354FC6FD1F for ; Tue, 14 Mar 2023 16:52:35 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rE-0005qz-AM; Tue, 14 Mar 2023 12:50:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rD-0005pH-1d for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:39 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rB-0002bj-IH for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:38 -0400 Received: by mail-ot1-x329.google.com with SMTP id o4-20020a9d6d04000000b00694127788f4so8740222otp.6 for ; Tue, 14 Mar 2023 09:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K6ZtRqLm3B8SDR32oQ4sLJQ9pfzzGuemgvRzywYt9gA=; b=NGt3OjmdKLORQRSXqQ8xyKvIl7wdG1EcYGy/qlSZV4EFezjPYWigr/AhuhSNHOpbM9 cjfAp3w6UJhY8+h5X7QyNF7rqChWclI+ndnowFuU3YU9lzGgBrk6gPFPa/SUUbKpcgMB pv9Ambyxj3Mq1G6zjCH/XMzPO9JyyJP4oA2au+09YYZgAyrTURtfPjOcyaYaD9sW02KH zvJA4bCOtkFUkYEDmtHJz4ZV8yt5LsT1VS2wkA8RKoBPmfuHd6t3rEKTx/Zphbv01bg8 +DqXUzX/Nf5PK2AKp1db2PlfbldxDIj1KV2bOCQ91/PrHxPOPMuKTW90RkNZJmYgYbmK BwTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K6ZtRqLm3B8SDR32oQ4sLJQ9pfzzGuemgvRzywYt9gA=; b=y0BBqa7F+eCha9ECQQXX16ViHVtjeTBI1bjJL47Con6TFxxdsbGJwFk9XyF9W9Zy3Z j0daum9OByc6w7LpFzv9PDk2h4x4SpLCWx1OaLGD5ucJq2xFzu7GzeigNLIv1J7EZ1xA ZgGPl0RN41bn7p/GsEDYwwCv41tNzU0WKCtIs+nket8YBxAOQPsi1fVYeDkNBGntCZ7S 67vWls9d0A+afc/u+6rc4ArstOQKlcPRoVUp56lqOofz/G5qXehbIbbkqPYm1/iyLm+Z AkYUR6fGpvZCWye0t4qDk1PrSJ4bkgyj+/MZAx1ME3zU/G/FqidC21mP0UKmtQw6p21D RqdQ== X-Gm-Message-State: AO0yUKXTcDfiVTYtRx4aolfn+TPODDFgrMpVh6vDTYy9AJ/M6uyeigxw RglEUswTpePG32hI5aEt5B7wD7Wis7nCJEmT3Jw= X-Google-Smtp-Source: AK7set9Yd5chxIQr49mSKr85W59WTCivGr57nlRb0phmiCHaVd6QnFOGZD0CtKjcDrJbgT64MQSuMw== X-Received: by 2002:a05:6830:2706:b0:696:e664:6894 with SMTP id j6-20020a056830270600b00696e6646894mr2140142otu.34.1678812636552; Tue, 14 Mar 2023 09:50:36 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:36 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 14/26] target/riscv: add RVG Date: Tue, 14 Mar 2023 13:49:36 -0300 Message-Id: <20230314164948.539135-15-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The 'G' bit in misa_ext is a virtual extension that enables a set of extensions (i, m, a, f, d, icsr and ifencei). We'll want to avoid setting it for write_misa(). Add it so we can gate write_misa() properly against it. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 1 + 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 28d4c5f768..48ad7372b9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -274,6 +274,9 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg) if (cfg->ext_j) { ext |= RVJ; } + if (cfg->ext_g) { + ext |= RVG; + } return ext; } @@ -293,6 +296,7 @@ static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, cfg->ext_u = misa_ext & RVU; cfg->ext_h = misa_ext & RVH; cfg->ext_j = misa_ext & RVJ; + cfg->ext_g = misa_ext & RVG; } static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2263629332..dbb4df9df0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,6 +82,7 @@ #define RVU RV('U') #define RVH RV('H') #define RVJ RV('J') +#define RVG RV('G') /* Privileged specification version */ From patchwork Tue Mar 14 16:49:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174754 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 160C0C05027 for ; Tue, 14 Mar 2023 16:51:29 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rH-0005tc-Es; Tue, 14 Mar 2023 12:50:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rG-0005tA-FA for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:42 -0400 Received: from mail-ot1-x329.google.com ([2607:f8b0:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rE-0002ti-O9 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:42 -0400 Received: by mail-ot1-x329.google.com with SMTP id t10-20020a9d774a000000b00698d7d8d512so588982otl.10 for ; Tue, 14 Mar 2023 09:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rRdtt58Q8y4eJQCf9Cy8TeGZOFv7f1nClPt2O+Z3IH4=; b=iK3+dqRwxiKcRkgZ7IrbYS09Ibz5c50PY9hr/kbhaS/FHQuQJ7ln3ZDYoOSbtCyhjj deoj1BA+cbu/A6/fim5ayk+Anq9TXCslU+JYYfbU+ORzzZ3asOPzEwrqkiknlRYU0Yjl sOKoYy5+JPZyCNB10rsevj+m3iqcg0AiVfcIpq9Rc6W2iIluKFqPMx1iSMzetdGszhXX AsBpBwfWO8t7wjnaIB6vuADSuNizVInkMq6wKdsQDFlov2o1EoTE8AL/QYOjY7Wza+Vp jF8ZovbZmOzR6d3F4c6UlfaOjpTQptJvA/z4XtY/df9+uR9oDXLdlxVzTQ6rDfQxouZA e5yA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812639; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rRdtt58Q8y4eJQCf9Cy8TeGZOFv7f1nClPt2O+Z3IH4=; b=GV7dpEy/SMhnt7B1Hw7mWHQYmgsMHVpykxCPlBV3kb58XhQSz+PaLaGUdBXHwCYZuE vLvxKUvqvUjxrBvulGZrGuSJNk9aXvfVaSidad9JlVFVOVHRl0UZYGOZ/aKKFCAaRRwl RP9kswuZaqKWXAU+6FYDZ1glbVTxeFvYRDAYwDWvW6hXFA9ImkFCcji5eGcABdWmhCSv T2T/VSHIqRdXub4TgEgmiOMO7Ym2VQSfp2ZdAkgfgbcLmJr12xGs+rM+usZInMGPLrrA CM6BUyy6WFbD+0WVSGGg8DC/mMfH5qsPIJPsewhRee2wryR90MmUzyGaGa3qhQLzWlXc NfWQ== X-Gm-Message-State: AO0yUKXOAA8+Ap/GUh/eSXAa1TIcPj3XlJo4j14Ptz2lOjLCT2JHbMKq LmAbV9nSm0Nxf01jVHPzomrYpW/CfZz7b7W1bSA= X-Google-Smtp-Source: AK7set/VwUH5yq5mGmba7EsLFXvdbNP8I2mYzusbC4tq5QsKwj1ipdaCbgK+D+OAnYdz3zRhCJd9NQ== X-Received: by 2002:a9d:4111:0:b0:694:3972:db96 with SMTP id o17-20020a9d4111000000b006943972db96mr19139427ote.0.1678812639784; Tue, 14 Mar 2023 09:50:39 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:39 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 15/26] target/riscv: do not allow RVG in write_misa() Date: Tue, 14 Mar 2023 13:49:37 -0300 Message-Id: <20230314164948.539135-16-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::329; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We're getting ready to use riscv_cpu_validate_set_extensions() to unify the handling of write_misa() with the rest of the code base. But first we need to deal with RVG. The 'G' virtual extension enables a set of extensions in the CPU. At this moment, this is done at the start of our validation step in riscv_cpu_validate_set_extensions(). This means that enabling G will enable other extensions in the CPU before resuming the validation. This also means that, in case a write_misa() validation fails, we're going to set cpu->cfg attributes that are unrelated to misa_ext bits (icsr and ifencei). These would be 2 extra states that we would need to store to fallback from a validation failure. Since write_misa() is still on experimental state let's make our lives easier for now and disable RVG updates. Signed-off-by: Daniel Henrique Barboza --- target/riscv/csr.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d522efc0b6..918d442ebd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1348,6 +1348,11 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } + /* Changing 'G' state is unsupported */ + if (val & RVG) { + return RISCV_EXCP_NONE; + } + /* 'I' or 'E' must be present */ if (!(val & (RVI | RVE))) { /* It is not, drop write to misa */ From patchwork Tue Mar 14 16:49:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174761 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6725C05027 for ; Tue, 14 Mar 2023 16:52:31 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rM-0006B3-Js; Tue, 14 Mar 2023 12:50:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rK-00065S-4I for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:46 -0400 Received: from mail-oo1-xc2e.google.com ([2607:f8b0:4864:20::c2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rI-00032E-9V for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:45 -0400 Received: by mail-oo1-xc2e.google.com with SMTP id n27-20020a4ad63b000000b005252709efdbso2404172oon.4 for ; Tue, 14 Mar 2023 09:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UkqYwjMeffkjPjp5cMWVsaWAzAtPS7xe9pFJYyoNEaE=; b=IfIjmZgQBovpc1OGxZhoUuywmV6BjZZ6WqB+1tnpE0Djnn5J47xI2XPRkaUGklZ9B2 zYw5ObXLx6oEVf+5rfSpVXlglZL42fNXHhjpyuFl5a/fEBW9Enj48//WDJjh7Z04ppec CEuouwVTwQbpYMY8427MrRE4FVDfJbnUZnTdc9LP+6dnrCWGdP4MzAYZsscmX5MGZPt9 9pQ8tjF353gD/y65HJVp+N5OnOy9o8BFUbLZiPRA9grmCa2XB7UU4/cf35yqTkVXjVfg dN1XsTsZhHy0foI2ShCv3vRO+G4CxS91SJH2gDh68oLyHsT0GoUNnJXiZ+pdKJcoBOjS +Czg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812643; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UkqYwjMeffkjPjp5cMWVsaWAzAtPS7xe9pFJYyoNEaE=; b=n/yAkY8QCNXStwqqs1miMTGjP3avEtsZgC48gg3xthkhtWDKMOpwNidNeCbMBy0bT1 YcMuwZEVqO6vwgMsgaEuu/DxeSyNLlvdo2A9yS0qDvwWqrHqrY4CTX9I7BGySf7KUh0B z0FercTL/3m3cqEXuaBxZlZpsmmU0FqUQE93eQXrO28jP4TJI6OUfGADR9C5WrNDMxx9 qQVngr8H2H3kO7jkPss/HdQbx31WijFqNtWs2IrdyfYvtv4n8nCgjIyZ3wfLWkpGJBb3 t3Ta5/9huaxXJkMh5yw24ZJ9wAkczadqANk9UYovpirjWpkTzOYrYLIa9mxImfH2pnsR WoBg== X-Gm-Message-State: AO0yUKVZYWwo7pndNLbtPkm0GZAZeK2Zqhc4cU140LEBoFmUjAeWqHPM EgpIU/iWaRT33KAJYp6XP4Krx6lsbNXmspC472U= X-Google-Smtp-Source: AK7set+gte7C+eU4YZsUqbvakrIvdiZTBVsU+BADHhQavPYGw5mlQaULBlPq3SFvKCwYcdUSI5byJg== X-Received: by 2002:a05:6820:150b:b0:525:42c7:9a5f with SMTP id ay11-20020a056820150b00b0052542c79a5fmr20315906oob.6.1678812642823; Tue, 14 Mar 2023 09:50:42 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:42 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 16/26] target/riscv/cpu.c: split RVG code from validate_set_extensions() Date: Tue, 14 Mar 2023 13:49:38 -0300 Message-Id: <20230314164948.539135-17-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We can set all RVG related extensions during realize time, before validate_set_extensions() itself. It will also avoid re-enabling RVG via write_misa() when the CSR start to using the same validation code realize() does. Note that we're setting both cfg->ext_N and env->misa_ext bits, instead of just setting cfg->ext_N. The intention here is to start syncing all misa_ext operations with its cpu->cfg flags, in preparation to allow for the validate function to operate using a misa_ext. This doesn't make any difference for the current code state, but will be a requirement for write_misa() later on. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 55 +++++++++++++++++++++++++++++++++------------- 1 file changed, 40 insertions(+), 15 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 48ad7372b9..133807e39f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -281,6 +281,42 @@ static uint32_t riscv_get_misa_ext_with_cpucfg(RISCVCPUConfig *cfg) return ext; } +static void riscv_set_G_virt_ext(RISCVCPU *cpu) +{ + CPURISCVState *env = &cpu->env; + RISCVCPUConfig *cfg = &cpu->cfg; + + if (!(cfg->ext_i && cfg->ext_m && cfg->ext_a && + cfg->ext_f && cfg->ext_d && + cfg->ext_icsr && cfg->ext_ifencei)) { + + warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); + cfg->ext_i = true; + env->misa_ext |= RVI; + + cfg->ext_m = true; + env->misa_ext |= RVM; + + cfg->ext_a = true; + env->misa_ext |= RVA; + + cfg->ext_f = true; + env->misa_ext |= RVF; + + cfg->ext_d = true; + env->misa_ext |= RVD; + + cfg->ext_icsr = true; + cfg->ext_ifencei = true; + + /* + * Update misa_ext_mask since this is called + * only during riscv_cpu_realize(). + */ + env->misa_ext_mask = env->misa_ext; + } +} + static void riscv_set_cpucfg_with_misa(RISCVCPUConfig *cfg, uint32_t misa_ext) { @@ -1036,21 +1072,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - /* Do some ISA extension error checking */ - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && - cpu->cfg.ext_a && cpu->cfg.ext_f && - cpu->cfg.ext_d && - cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { - warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); - cpu->cfg.ext_i = true; - cpu->cfg.ext_m = true; - cpu->cfg.ext_a = true; - cpu->cfg.ext_f = true; - cpu->cfg.ext_d = true; - cpu->cfg.ext_icsr = true; - cpu->cfg.ext_ifencei = true; - } - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); @@ -1313,6 +1334,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + if (cpu->cfg.ext_g) { + riscv_set_G_virt_ext(cpu); + } + riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); From patchwork Tue Mar 14 16:49:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 75A08C05027 for ; Tue, 14 Mar 2023 16:52:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rP-0006Kw-Hc; Tue, 14 Mar 2023 12:50:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rM-0006BQ-Vy for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:49 -0400 Received: from mail-oo1-xc34.google.com ([2607:f8b0:4864:20::c34]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rL-000336-CM for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:48 -0400 Received: by mail-oo1-xc34.google.com with SMTP id u3-20020a4ad0c3000000b0052541ef0bafso2404472oor.5 for ; Tue, 14 Mar 2023 09:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5ZchHCpbCNurGYGzCknrdABpRZLtEe8JKLQAwB+SapM=; b=a71moXEMoBE8kVC6fGZX2kkBJUHVsG0NJmF1WoqI1PKMqLQwWewtQpD6qlPaU04Ljc KMyheISz04y+wBqG2Plna/pFpcsriNl40qtdb4fZ9Mjn0kiO+rg0u1GYm/N9lMOy+OeO v62l6LbPcpfciwIz/X8bxte8zUVRP3+UCcL+Gk2wtd9KgM/tgaAIyPKrWkLqOlZplK88 N79Adn+eRmv7YCn/rTMXjzj6z/H+QxWvPiioIOk5hb66LwXwS+2ll5ny3f5BBJ+ghdWb yxX/iY+EDo0b9iSgeUoambb6tyVY+IUSQI9zYZc5IkPS/BvDpYyO851Cx5E3tfT1+G6d 8K2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812646; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5ZchHCpbCNurGYGzCknrdABpRZLtEe8JKLQAwB+SapM=; b=BXrUySpuu33TSXSv3lAqs/Blxpn0AF4P8lukL48/0Fux09gWjDjWzKPi5ej97WHk45 DqnnPofVTGWJtPy4Ab3qml1bQo2j37wS+nk569kVFO3VWJB17zIH3yrRZpsy7Zz+mqEr s02qh3CRaNsWY4s9LthgXwnYHR7W7cLfkSkMTuuGasHZB6xKeG5u/YynmnBfpO5UHNhz hZTyiNMFBSsRRn+K3ZaEiFJA9v9RNPhtZPcEAqeyVRYhwt7l7VqnwQIoKGX/WnxbwIix 3VgcpH27gpb3oi1gHTOQhPPMRAeN14ISaDrlbaNh3f50G1rQOKzUtkwQ5mAvBorfbtHi fTWg== X-Gm-Message-State: AO0yUKW8ZhD44ZIjLOJXEsd2h89rswaZtm+N0UMzxqpkduIH17Ra1fVc PWlcVVorFgQGJaA7UlJuoJTP+D+VzKcsxyhx1RM= X-Google-Smtp-Source: AK7set9EH8gpWkHUcbyaWGzntxCB7zD18TLyg5o7p2yz86rta3e38fFLQ7F2LiyiOZAK7ZxOPsFRpw== X-Received: by 2002:a4a:b78c:0:b0:525:2d37:5335 with SMTP id a12-20020a4ab78c000000b005252d375335mr18448613oop.8.1678812645909; Tue, 14 Mar 2023 09:50:45 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:45 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 17/26] target/riscv: write env->misa_ext* in register_generic_cpu_props() Date: Tue, 14 Mar 2023 13:49:39 -0300 Message-Id: <20230314164948.539135-18-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c34; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org In the process of creating the user-facing flags in register_generic_cpu_props() we're also setting default values for the cpu->cfg flags that represents MISA bits. Leaving it as is will cause a discrepancy between users of this function (at this moment the non-named CPUs) and named CPUs. Named CPUs are using set_misa() with a non-zero 'ext' value, writing cpu->cfg in the process. They'll reach riscv_cpu_realize() in a state where env->misa_ext will reflect cpu->cfg, allowing functions to choose whether to use env->misa_ext or cpu->cfg to validate MISA bits. If we guarantee that env->misa_ext will always reflect cpu->cfg at the start of riscv_cpu_realize(), functions will be able to no longer rely on cpu->cfg for MISA validation. This happens to be one blocker we have to properly support write_misa(). Sync env->misa_ext* in register_generic_cpu_props(). This will leave only a single place where there's a cpu->cfg change that needs to be converted back to env->misa_ext*: right after disabling priv spec extensions, at the end of riscv_cpu_validate_set_extensions(). We'll deal with it shortly. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 133807e39f..af5a1e6a43 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1595,10 +1595,12 @@ static Property riscv_cpu_extensions[] = { * Register generic CPU props with user-facing flags declared * in riscv_cpu_extensions[]. * - * Note that this will overwrite existing values in cpu->cfg. + * Note that this will overwrite existing values in cpu->cfg + * and MISA. */ static void register_generic_cpu_props(Object *obj) { + RISCVCPU *cpu = RISCV_CPU(obj); Property *prop; DeviceState *dev = DEVICE(obj); @@ -1609,6 +1611,10 @@ static void register_generic_cpu_props(Object *obj) #ifndef CONFIG_USER_ONLY riscv_add_satp_mode_properties(obj); #endif + + /* Keep env->misa_ext and misa_ext_mask updated */ + cpu->env.misa_ext = riscv_get_misa_ext_with_cpucfg(&cpu->cfg); + cpu->env.misa_ext_mask = cpu->env.misa_ext; } static Property riscv_cpu_properties[] = { From patchwork Tue Mar 14 16:49:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7A6FFC05027 for ; Tue, 14 Mar 2023 16:54:52 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rR-0006SK-9n; Tue, 14 Mar 2023 12:50:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rQ-0006OD-59 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:52 -0400 Received: from mail-oi1-x231.google.com ([2607:f8b0:4864:20::231]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rO-000342-7J for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:51 -0400 Received: by mail-oi1-x231.google.com with SMTP id bh20so12248753oib.9 for ; Tue, 14 Mar 2023 09:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kKsj1Bf1nRdbbtRMBsx4PpI7751/nt1s+yAwKgnlL9Y=; b=KYPg9h1gRrjKz9XB1ZQSEY01UnVVZ6AmL7EjNk9tRNQl2gaPsPNYEg61A0QEO26y0G sL+FOZIP8GgS5F+qNYDjVWa8bQ04K7s1GjMRWswCgtu6QQ163igXqZ275e+d09xMCmu2 jVEL8sMx4AF9OF990VwKxYh0bqlcNPGrKgD7DhvXEdXs6gs83sKPyxIdQppiOd1ZpNni KWBcziftfZE1/hydWh+pfZjgsLSjcBXO2uJO2aJXxz68p8AWpfgFOHPQx2PVoiD0qjWp 3BOaZXVQ6I0FQWxWtPNB8cAATGwYi5n3OcDSn123Z25C82f9izfTEBKQmItEy6VNA2pq ji4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812649; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kKsj1Bf1nRdbbtRMBsx4PpI7751/nt1s+yAwKgnlL9Y=; b=sMwMeM+Lm2xwXAHamPIGSC7yZOgiPlFf3dQrOJrCkxLglu+0mX/qY9JSBZBQqyO7ni g2XjnFxSIzxEpVdsg2EHwHKso2EOU6wdwnHu2BEO7ejrtAGIfSW/ov5fpojfcZfnzanC L/XAFf5WyQcF3JZdvF5Aainv/E4LDsjxzZRDgJizoWcgHEcfHfXn6n6PkG4viKmlfjz5 VJFssCy/KheLBzlFzCnKetmcyGtFKKla+q9QYZ22DnLX7KORXvZxqRkEFyCFLl0eXbGw i9oiwEWCkxAC8oUr6zsyPlhs7vuX1ZqN4OoVQw2zlz9OHdzQrrFOuy9uF0muQnTYuNdW QzQw== X-Gm-Message-State: AO0yUKVYsA7OSEhBRtm2D3YiwtmcZVlUzRD6FFjSe+2SWj+EkhrIWKIl CqjcVYoNIH+PrFgxv1kZVEMf8m1pjCzulz7UGgs= X-Google-Smtp-Source: AK7set9GEHAlWeiCTzf1rD93I/oyui6zEhlsFeJsbTCrnK9NT+x8wJoMxEZLAZ+fik8ibsqxlLo2rw== X-Received: by 2002:a54:4799:0:b0:386:9f86:cadd with SMTP id o25-20020a544799000000b003869f86caddmr223536oic.30.1678812648834; Tue, 14 Mar 2023 09:50:48 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:48 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 18/26] target/risc/cpu.c: add riscv_cpu_validate_misa_ext() Date: Tue, 14 Mar 2023 13:49:40 -0300 Message-Id: <20230314164948.539135-19-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=dbarboza@ventanamicro.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Even after taking RVG off from riscv_cpu_validate_set_extensions(), the function is still doing too much. It is validating misa bits, then validating named extensions, and if the validation succeeds it's doing more changes in both cpu->cfg and MISA bits. It works for the support we have today, since we'll error out during realize() time. This is not enough to support write_misa() though - we don't want to error out if userspace writes something odd in the CSR. This patch starts splitting riscv_cpu_validate_set_extensions() into a three step process: validate misa_ext, validate cpu->cfg, then commit the configuration. This separation will allow us to use these functions in write_misa() without having to worry about saving CPU state during runtime because the function changed state but failed to validate. riscv_cpu_validate_misa_ext() will host all validations related to misa bits only. Validations using misa bits + name extensions will remain in validate_set_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 77 ++++++++++++++++++++++++++-------------------- 1 file changed, 43 insertions(+), 34 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index af5a1e6a43..83b1b874ee 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1025,6 +1025,43 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } } +static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) +{ + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + error_setg(errp, + "I and E extensions are incompatible"); + return; + } + + if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + error_setg(errp, + "Either I or E extension must be set"); + return; + } + + if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + error_setg(errp, + "Setting S extension without U extension is illegal"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + error_setg(errp, + "H depends on an I base integer ISA with 32 x registers"); + return; + } + + if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + error_setg(errp, "H extension implicitly requires S-mode"); + return; + } + + if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + error_setg(errp, "D extension requires F extension"); + return; + } +} + static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) { RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); @@ -1072,35 +1109,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { - error_setg(errp, - "I and E extensions are incompatible"); - return; - } - - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { - error_setg(errp, - "Either I or E extension must be set"); - return; - } - - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { - error_setg(errp, - "Setting S extension without U extension is illegal"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { - error_setg(errp, - "H depends on an I base integer ISA with 32 x registers"); - return; - } - - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { - error_setg(errp, "H extension implicitly requires S-mode"); - return; - } - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; @@ -1120,11 +1128,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { - error_setg(errp, "D extension requires F extension"); - return; - } - /* The V vector extension depends on the Zve64d extension */ if (cpu->cfg.ext_v) { cpu->cfg.ext_zve64d = true; @@ -1338,6 +1341,12 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_G_virt_ext(cpu); } + riscv_cpu_validate_misa_ext(cpu, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } + riscv_cpu_validate_set_extensions(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); From patchwork Tue Mar 14 16:49:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174766 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 82FC0C6FD1F for ; Tue, 14 Mar 2023 16:53:01 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rU-0006c4-AX; Tue, 14 Mar 2023 12:50:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rS-0006Z1-MD for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:54 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rR-0002tn-6b for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:54 -0400 Received: by mail-ot1-x334.google.com with SMTP id p13-20020a9d744d000000b0069438f0db7eso8753451otk.3 for ; Tue, 14 Mar 2023 09:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qe/ggxZ5kkULljr/heGGR8TpE8MwTlFD99D/rf5EvYk=; b=WRW+IBUdpVhYLfkhGdb7q2UfNv0CampnYzPO+YhEonW4zfvBbrDJcmQrLzzfZSP76P WMJt9FkM8dvbAF1jl0KDjii6j6revy3EE02cRyhF6Xg4qTjrK/31oaWNPXizPEcxo0Gn fH3qdXstdLkbcw43Z92p/nEH1EJtLos5ezV0TqSU3QQUahsseUKRYArH1bclUK9Qostt UOEpkvQLOYpZnfViFhqNDZgBzKWvmAJDiBW6cV8PrORl1RHiJJtxT05w/fsO89kWYPQP TP6nEexvHQczE7FKvDUHaToGK2osNc7KaOxhxd7LPFs81YRufqZ45eZDPngUmTsGAU1r 4StQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812652; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qe/ggxZ5kkULljr/heGGR8TpE8MwTlFD99D/rf5EvYk=; b=Tak9RDwfAvQsadP9cw2yBrraGMpZpVqGcSj+My1HeUp8W8FPJS6GrVXPMrr3nc0+S2 clT3qXZA7BgMWjXnJrUW2Ao0HmDxx3ezLyVBaJn5JvWu2HS/s2O/87L4/DV+Jm3liJ3w LIW2Nxi/PrIfRz+LiqThxUOhxtpzdj8843Q0+VZ0oJQpCI0aZu2SpQ7Qp+m2c31EiWOq BgnYaiLCc2s/AFtrpyQhHYlZMXdYhlqQQkvmZRJSoR8QD05OzlXHId8ZsXadNvfdn7YY +wzaEdnXK0x0PjAE4KV+unylFxU3fwsVnqOBFzYr4oIY6qmr5/FTYqxeFhFlAx8QFXs/ 47AQ== X-Gm-Message-State: AO0yUKU31OyTFA2ciMi3nUjjlpOvGCLTJyknJXUP9lL7wP8h0svRPemW OhJpOvMtmpbo50O5oR7Q1xSfdvNvVBWrgJ+/gaQ= X-Google-Smtp-Source: AK7set/CP6Ry0b+6ZRysif+X8NYWPRIXJnEBrylv3SKUq+CJ+CTVUi1CKxAQ/TLSw2bVzrnxw7K7bA== X-Received: by 2002:a05:6830:565:b0:694:88f5:f5ed with SMTP id f5-20020a056830056500b0069488f5f5edmr11705008otc.24.1678812652148; Tue, 14 Mar 2023 09:50:52 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:51 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 19/26] target/riscv/cpu:c add misa_ext V-> D & F dependency Date: Tue, 14 Mar 2023 13:49:41 -0300 Message-Id: <20230314164948.539135-20-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We have a chained dependency in riscv_cpu_validate_set_extensions() related to RVV. If RVV is set, we enable other extensions such as Zve64d, Zve64f and Zve32f, and these depends on misa bits RVD and RVF. Thus, we're making RVV depend on RVD and RVF. Let's add this dependency in riscv_cpu_validate_misa_ext() to fail earlier. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 83b1b874ee..fa1954a850 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1060,6 +1060,20 @@ static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) error_setg(errp, "D extension requires F extension"); return; } + + if (cpu->cfg.ext_v) { + /* + * V depends on Zve64d, which requires D. It also + * depends on Zve64f, which depends on Zve32f, + * which requires F. + * + * This means that V depends on both D and F. + */ + if (!(cpu->cfg.ext_d && cpu->cfg.ext_f)) { + error_setg(errp, "V extension requires D and F extensions"); + return; + } + } } static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) From patchwork Tue Mar 14 16:49:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174763 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C181DC6FD1F for ; Tue, 14 Mar 2023 16:52:38 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7rZ-0006nC-Oy; Tue, 14 Mar 2023 12:51:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rW-0006dl-3v for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:59 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rU-0002ba-FE for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:50:57 -0400 Received: by mail-ot1-x334.google.com with SMTP id f19-20020a9d5f13000000b00693ce5a2f3eso8743352oti.8 for ; Tue, 14 Mar 2023 09:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kVgmWGGBS3g3g08u5Ikz0Maj9Bf5PK3Kg5I4B2Hm1eU=; b=Q1yksMQGMccm4/kJI07WHIV8UxUXixVSinoFjgi8Un4XocUYg9zqfX1Tk/KQo6kqIa dB5CqD6VTamQmRxDGIIrpbtfATqxptysb2J+L386F05medyyT8Ljj1/RN0arNtTO12s7 PlS887nKg6QQ3mPR+Qbd13ECUR8pJAFXQsuap4f5YtlricCI+zvbnMSWYBR359uQiBLg 8zSKIIxnHq3VIvJAkwakVBQFr/bxBcDL1KVqXPW18ORPd7Ygopsfe4z1AtWx+pGbdiqI AfDsFM7yimlyA8qT1kM3mawCb09frXZGgiNp7clBuitmSWyiBIDKBzTJyEHYFJUJ0BzY U3lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812655; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kVgmWGGBS3g3g08u5Ikz0Maj9Bf5PK3Kg5I4B2Hm1eU=; b=cdUQ3XHzNOL8c72mOQuIxnW88rtNfwyeD92AvnZipwekbQETs030l8/exFaIzK3vvo 2K98fQe0qIvnRKmZOLKm4j1qxj6L3JQ0vdT0OheM8ACh9eGhWuJ62Pw/dacXJ3lzewQj nxJO/iS2uecaxYJ2iwmatQp9jKtt+RlG4TUAhFlT6IVCrrf3W+sMaNkvliKEtWXxa/0U QkES4d/q9Bd5U4sS+KhAP482SYJzmxNZ8C37dug8e6iLLMWkHGU+4f8WNwk8rB6k1nfZ qD+mfMQ9YPlElzppshUUPI1urTr/F08UY2j7nHszSBgfLQifRfjbws54gLA7VsTA4Ev9 FTHw== X-Gm-Message-State: AO0yUKWrKC80cBBweD0niBf6jT1QIwoW0/7uEpdzkxp6IcHcx/erc3Wj Njy2dtaS7N5M6lxaxJoLi42tX3KRwXYnPPioww4= X-Google-Smtp-Source: AK7set9Z2wUBduJlE9+YpGN7bQOBQDDgX45zXYFRexnypsawNFnKJuPkj31O4bH4nYNnjaFoOgItpw== X-Received: by 2002:a9d:7206:0:b0:68b:dc52:10f9 with SMTP id u6-20020a9d7206000000b0068bdc5210f9mr19720752otj.5.1678812655420; Tue, 14 Mar 2023 09:50:55 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:54 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 20/26] target/riscv: move riscv_cpu_validate_v() to validate_misa_ext() Date: Tue, 14 Mar 2023 13:49:42 -0300 Message-Id: <20230314164948.539135-21-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org riscv_cpu_validate_v() consists of checking RVV related attributes, such as vlen and elen, and setting env->vext_spec. This can be done during riscv_cpu_validate_misa_ext() time, allowing us to fail earlier if RVV constrains are not met. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index fa1954a850..0d8524d0d9 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1027,6 +1027,9 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) { + CPURISCVState *env = &cpu->env; + Error *local_err = NULL; + if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); @@ -1073,6 +1076,12 @@ static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) error_setg(errp, "V extension requires D and F extensions"); return; } + + riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + if (local_err != NULL) { + error_propagate(errp, local_err); + return; + } } } @@ -1111,7 +1120,6 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { CPURISCVState *env = &cpu->env; - Error *local_err = NULL; uint32_t ext = 0; if (cpu->cfg.epmp && !cpu->cfg.pmp) { @@ -1202,14 +1210,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) } } - if (cpu->cfg.ext_v) { - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); - if (local_err != NULL) { - error_propagate(errp, local_err); - return; - } - } - if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; From patchwork Tue Mar 14 16:49:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174765 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD985C6FD1F for ; Tue, 14 Mar 2023 16:52:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7re-0006sQ-2D; Tue, 14 Mar 2023 12:51:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7ra-0006nN-KV for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:02 -0400 Received: from mail-ot1-x334.google.com ([2607:f8b0:4864:20::334]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rZ-0002tn-0F for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:02 -0400 Received: by mail-ot1-x334.google.com with SMTP id p13-20020a9d744d000000b0069438f0db7eso8753610otk.3 for ; Tue, 14 Mar 2023 09:50:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bXu2RGXcq0gqBcM4NKB9bkqVmtqDPomsLl3SXZ2K35Q=; b=PQ3hO1ERfXi4oqM5jrxnmbhLOPVaj5/jixoxdXjuzvQk7CNcfjjjy5vGEWEx9xnQ1I EZwqWqHGCCdAY5rzZ0ZFCwlm797CxHKf53LSlgluHVoywLk2QbgA7ZnQJEQunSJ6YiBo 1mfgATjyaSsl/HM/omNrlTvi3dmZJHKkhThRPsiSj0DSi96e4l8sh+edwLlD1AH9euFQ QH71Dg0zxQUBJikXY9MdVYOhCnaUWBOGPphb1FtJQTIGg0W58IyK4p4Nvg5Sq+yUFyMd Mg3gAJozJPQSd7YZvQ41xmwRS1h3oWBNncm+ibuwUnRnnV7zYNHYq1t/WgRY+Qj7xmNZ DsVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812659; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bXu2RGXcq0gqBcM4NKB9bkqVmtqDPomsLl3SXZ2K35Q=; b=4EMbNuZEOZ9z+0/gNGqLcXVNFwh7X+fiL2TfU91FlyDz02aij+U2HNhyeEq0NumcRb MtnbkbUnpFycAHBW7AShS7UU+m/m6pUhkSCJHN9SFCtIIU6TuMr1VABVMzot/gTzhDaF ABHrYSQTbMtLxnALAsXjRRtH7jtrX5jTP2u4K91r/mvJG5x3eCmIzzAqfjFuKQciX5jA yoQFkdqriqRuy6eNXWrLRvBtgvcwY2fASPl5Dr4/2MjF2u+Xh0hk6K36FZmjFgtfQUU0 ySh43TdX9R3HqzgAaTfQGibV39/n5ASb67L6ygOZLA4NLyGrYNLfLYG6VOtZwXgZaENg vEXA== X-Gm-Message-State: AO0yUKVg6+NP7dRsq77yUwNiwtA6WY+49fDtSvyTL6bri/jFFwYXgAoN IEA+Ga8SirJk/DqTMlQSn8XzgKHFI69I+e6kfSg= X-Google-Smtp-Source: AK7set+ZToiZ5QLpLcS4kPyCr8Pt43Rz6k+XSG9bLmkfEoOLwtC+CbanSBIeGILWJbmaIzFhZaQmPA== X-Received: by 2002:a9d:5f8a:0:b0:694:331d:8501 with SMTP id g10-20020a9d5f8a000000b00694331d8501mr19075057oti.21.1678812658936; Tue, 14 Mar 2023 09:50:58 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:50:58 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 21/26] target/riscv: validate_misa_ext() now validates a misa_ext val Date: Tue, 14 Mar 2023 13:49:43 -0300 Message-Id: <20230314164948.539135-22-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We have all MISA specific validations in riscv_cpu_validate_misa_ext(), and we have a guarantee that env->misa_ext will always be in sync with cpu->cfg at this point during realize time, so let's convert it to use a 'misa_ext' parameter instead of reading cpu->cfg. This will prepare the function to be used in write_misa() where we won't have an updated cpu->cfg object to work with. riscv_cpu_validate_v() is changed to receive a const pointer to the cpu->cfg object via riscv_cpu_cfg(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 0d8524d0d9..f8f416d6dd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -939,7 +939,8 @@ static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) } } -static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, +static void riscv_cpu_validate_v(CPURISCVState *env, + const RISCVCPUConfig *cfg, Error **errp) { int vext_version = VEXT_VERSION_1_00_0; @@ -1025,46 +1026,48 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } } -static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) + +static void riscv_cpu_validate_misa_ext(CPURISCVState *env, + uint32_t misa_ext, + Error **errp) { - CPURISCVState *env = &cpu->env; Error *local_err = NULL; - if (cpu->cfg.ext_i && cpu->cfg.ext_e) { + if (misa_ext & RVI && misa_ext & RVE) { error_setg(errp, "I and E extensions are incompatible"); return; } - if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { + if (!(misa_ext & RVI) && !(misa_ext & RVE)) { error_setg(errp, "Either I or E extension must be set"); return; } - if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { + if (misa_ext & RVS && !(misa_ext & RVU)) { error_setg(errp, "Setting S extension without U extension is illegal"); return; } - if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { + if (misa_ext & RVH && !(misa_ext & RVI)) { error_setg(errp, "H depends on an I base integer ISA with 32 x registers"); return; } - if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { + if (misa_ext & RVH && !(misa_ext & RVS)) { error_setg(errp, "H extension implicitly requires S-mode"); return; } - if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { + if (misa_ext & RVD && !(misa_ext & RVF)) { error_setg(errp, "D extension requires F extension"); return; } - if (cpu->cfg.ext_v) { + if (misa_ext & RVV) { /* * V depends on Zve64d, which requires D. It also * depends on Zve64f, which depends on Zve32f, @@ -1072,12 +1075,12 @@ static void riscv_cpu_validate_misa_ext(RISCVCPU *cpu, Error **errp) * * This means that V depends on both D and F. */ - if (!(cpu->cfg.ext_d && cpu->cfg.ext_f)) { + if (!(misa_ext & RVD && misa_ext & RVF)) { error_setg(errp, "V extension requires D and F extensions"); return; } - riscv_cpu_validate_v(env, &cpu->cfg, &local_err); + riscv_cpu_validate_v(env, riscv_cpu_cfg(env), &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; @@ -1331,6 +1334,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) CPUState *cs = CPU(dev); RISCVCPU *cpu = RISCV_CPU(dev); RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); + CPURISCVState *env = &cpu->env; Error *local_err = NULL; cpu_exec_realizefn(cs, &local_err); @@ -1355,7 +1359,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) riscv_set_G_virt_ext(cpu); } - riscv_cpu_validate_misa_ext(cpu, &local_err); + riscv_cpu_validate_misa_ext(env, env->misa_ext, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; From patchwork Tue Mar 14 16:49:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 67024C05027 for ; Tue, 14 Mar 2023 16:53:28 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7s3-0007Hp-T6; Tue, 14 Mar 2023 12:51:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rg-0006wo-P7 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:14 -0400 Received: from mail-oa1-x2e.google.com ([2001:4860:4864:20::2e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rc-000365-P6 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:07 -0400 Received: by mail-oa1-x2e.google.com with SMTP id 586e51a60fabf-1755e639b65so17998795fac.3 for ; Tue, 14 Mar 2023 09:51:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Hq9gu6gdQMKvyfHGOOHilBq8t2MGN+S8P1yZLlg/7J8=; b=fan1aJUarjHM4z8Dimno2vBi7Lq7p9Vs1zop2m+gYz0cBtJy8W/b+ftNgKDb39//Ua pQHFiQeAUmYu2siJcwL0CAKfdnxK6mqIg3JLOsCwA9kR43lnI7W7fv+IBKhg11KhpE4k 0AXM3EAN9D7mz7EcwBZ0emxSm3wbuV7R0Xg+s4LxoFGgWVlLG6JM8vhyb4TZ84KS0o1I /zixpNiItUIdeV02E76WWPZNw3gPni5+j9okOe/jr1zFqBEenO1IKC3UTXx8Yw4wYJ+d /muE3irZBIFHgy1+wzCpX2W4oU0MqxfI6+ms21KqfQuLI4teGQyj5TbrNtHlE0Lma+GE +x8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812662; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Hq9gu6gdQMKvyfHGOOHilBq8t2MGN+S8P1yZLlg/7J8=; b=XzWyvLO9FOsVbqg1tHBcNsRYQUDrmIeqUwwzGRP2p/kCkcpxiix7hPgf4nVpNiUmdF cSCegzZv2ab9Zv3JvvcSG04x1FWT1fTpsJsmbIGmtPZavpiDPPMrJdwBwc3A+QRh/4Yb ciNA9gVj6kuicyF2aZ2t5x8B6CE0iiB+A8AwPjbOVeF2jkVKjB62AJLlkHeQsQGQUmSe t5y03LLQi0SVC/Uojt54Q3Z1gS0jT362mRpbXqDbtV0wWiWqAcDIZFlgZtBqEJm5gOvo 5bRbvrCIxuydDTdZL05uDRncZixO0Jndz5+qjcSOm/tjqoHDzS9okDRgyoDyaCjm8aAT J53w== X-Gm-Message-State: AO0yUKXZd4Q5uNUoU9OeLm+mh1jibXa9Zmd8diQZ4yhnmnl7KSNcpj1F YBMDWXySTyn6kuvgALgaVvq3eGVbVWpvhEXN4uM= X-Google-Smtp-Source: AK7set/7r2Ej9UkkE01qmGQjtfTTY7VfoWfAY2uxENaH8ku3nh9+6Lqjzrnb2RYIzJFx0qZLU8DwUQ== X-Received: by 2002:a05:6870:b016:b0:177:896a:cb06 with SMTP id y22-20020a056870b01600b00177896acb06mr8626840oae.17.1678812662217; Tue, 14 Mar 2023 09:51:02 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:51:01 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 22/26] target/riscv: error out on priv failure for RVH Date: Tue, 14 Mar 2023 13:49:44 -0300 Message-Id: <20230314164948.539135-23-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2e; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We have one last case where we're changing env->misa_ext* during validation. riscv_cpu_disable_priv_spec_isa_exts(), at the end of riscv_cpu_validate_set_extensions(), will disable cpu->cfg.ext_h and cpu->cfg.ext_v if priv_ver check fails. This check can be done in riscv_cpu_validate_misa_ext(). The difference here is that we're not silently disable it: we'll error out. Silently disabling a MISA extension after all the validation is completed can can cause inconsistencies that we don't have to deal with. Verify ealier and fail faster. Note that we're ignoring RVV priv_ver validation since its minimal priv is also the minimal value we support. RVH will error out if enabled under priv_ver under 1_12_0. As a bonus, we're guaranteeing that all env->misa_ext* changes will happen up until riscv_set_G_virt_ext(). We don't have to worry about keeping env->misa_ext in sync with cpu->cfg. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f8f416d6dd..1f72e1b8ce 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1067,6 +1067,20 @@ static void riscv_cpu_validate_misa_ext(CPURISCVState *env, return; } + /* + * Check for priv spec version. RVH is 1_12_0, RVV is 1_10_0. + * We don't support anything under 1_10_0 so skip checking + * priv for RVV. + * + * We're hardcoding it here to avoid looping into the + * 50+ entries of isa_edata_arr[] just to check the RVH + * entry. + */ + if (misa_ext & RVH && env->priv_ver < PRIV_VERSION_1_12_0) { + error_setg(errp, "H extension requires priv spec 1.12.0"); + return; + } + if (misa_ext & RVV) { /* * V depends on Zve64d, which requires D. It also @@ -1117,14 +1131,10 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) /* * Check consistency between chosen extensions while setting - * cpu->cfg accordingly, setting env->misa_ext and - * misa_ext_mask in the end. + * cpu->cfg accordingly. */ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) { - CPURISCVState *env = &cpu->env; - uint32_t ext = 0; - if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* * Enhanced PMP should only be available @@ -1241,10 +1251,6 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) * validated and set everything we need. */ riscv_cpu_disable_priv_spec_isa_exts(cpu); - - ext = riscv_get_misa_ext_with_cpucfg(&cpu->cfg); - - env->misa_ext_mask = env->misa_ext = ext; } #ifndef CONFIG_USER_ONLY @@ -1355,6 +1361,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } + /* + * This is the last point where env->misa_ext* can + * be changed. + */ if (cpu->cfg.ext_g) { riscv_set_G_virt_ext(cpu); } From patchwork Tue Mar 14 16:49:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 690B6C6FD1F for ; Tue, 14 Mar 2023 16:55:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7s6-0007eL-RK; Tue, 14 Mar 2023 12:51:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rh-0006x4-Fj for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:19 -0400 Received: from mail-oo1-xc2c.google.com ([2607:f8b0:4864:20::c2c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7re-00036j-WE for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:08 -0400 Received: by mail-oo1-xc2c.google.com with SMTP id q79-20020a4a3352000000b0052fe885deddso180158ooq.0 for ; Tue, 14 Mar 2023 09:51:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8A4bMOdOlp/qGLIk/cJ34z337QI1i7O+DLs8TRcWY1g=; b=ORqeECt+415G0wOBlCoWNWg8aKDotjz5MyoNJJkd8VPK7RnmWwuS7QvKAwWtb3KmOb 77RAU8Ae+RFtoByQ7exryWbD4KW+XUw5MeBdd0m2r/KPmmSP5Dkc0pELTr8pShkmxt/i 8HI5g64BCIq5YI3rGzQZHzDdrUcH9+UoImfQJUQmcrFg4nvA/yNvXZuxR9H9apeotdRT yo7mWdqWb7vXCnXXPQLugmd9RqAZT+H50qa4pRcUy0Qbh4nrGwHkEAjpvLWERrHaVMPq jAV2U1pKLsdbfPkpG5X2LN/CECa58uarck9JMAIJfMpd8KokpBJm3KlxFWs0c6/jCtLv J1og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812665; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8A4bMOdOlp/qGLIk/cJ34z337QI1i7O+DLs8TRcWY1g=; b=aQaME8Y36BOjBBWm6dtrfTYANgYseyHb+hO336wX79lkhApB5pShbmHnx9oMybZgcM Hr29mhRh3iz+sk7R9nX1BAM3Ntp7CZ1iEteQgEHU56Tkrx9IpIRwAlkIhKNtEPidgmc3 vTRgk1Scq6vwl64D68FPoY0lmDK/VtWm8+ERb/ClqZT0GWRAOV4KUO9UnHiLVReKcwVV hAEiCVJXlCreL39XXCpfHkcruVKKVXyYjty4es9Me5CV/2OTSFPMtv7btic4QmE3WiRF J7BsNJBwYXH5OID/nad8cj7YLZ8nFHc9btTRm0vYtDQxE1HyoAJckgLB9WVBlsVl12nz 8uvg== X-Gm-Message-State: AO0yUKXuu6o1q2Q2zzg/CXrG1FDqxA0+xxs0fofYucXip7E0+3zTWOT+ J40Dy/sY5ck1JDmdVtiuGmeoID12VA4tzIQ2ZM4= X-Google-Smtp-Source: AK7set/Ql946wi5Yws02Kv5gzU9StoKoRjZJcvCbPIvWOOA7vPFfZYodjCHIFwyDUkHVX2nUm6KGZw== X-Received: by 2002:a4a:3018:0:b0:517:4020:60b6 with SMTP id q24-20020a4a3018000000b00517402060b6mr16028065oof.8.1678812665364; Tue, 14 Mar 2023 09:51:05 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.51.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:51:05 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 23/26] target/riscv: split riscv_cpu_validate_set_extensions() Date: Tue, 14 Mar 2023 13:49:45 -0300 Message-Id: <20230314164948.539135-24-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2c; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org We're now ready to split riscv_cpu_validate_set_extensions() in two. None of these steps are going to touch env->misa_ext*. riscv_cpu_validate_extensions() will take care of all validations based on cpu->cfg values. cpu->cfg changes that are required for the validation are being tolerated here. This is the case of extensions such as ext_zfh enabling ext_zfhmin. The RVV chain enablement (ext_zve64d, ext_zve64f and ext_zve32f) is also being tolerated because the risk of failure is being mitigated by the RVV -> RVD && RVF dependency in validate_misa_ext() done prior. In an ideal world we would have all these extensions declared as object properties, with getters and setters, and we would be able to, e.g., enable ext_zfhmin as soon as ext_zfh is enabled. This would avoid cpu->cfg changes during riscv_cpu_validate_extensions(). Easier said than done, not just because of the hundreds of lines involved in it, but also because we want these properties to be available just for generic CPUs (named CPUs don't want these properties exposed for users). For now we'll work with that we have. riscv_cpu_commit_cpu_cfg() is the last step of the validation where more cpu->cfg properties are set and disabling of extensions due to priv spec happens. We're already validated everything we wanted, so any cpu->cfg change made here is valid. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1f72e1b8ce..e423d3e2d2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1130,10 +1130,10 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) } /* - * Check consistency between chosen extensions while setting - * cpu->cfg accordingly. + * Check consistency between chosen extensions. No changes + * in env->misa_ext are made. */ -static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) { if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* @@ -1222,7 +1222,10 @@ static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } } +} +static void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu) +{ if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; @@ -1375,12 +1378,14 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - riscv_cpu_validate_set_extensions(cpu, &local_err); + riscv_cpu_validate_extensions(cpu, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; } + riscv_cpu_commit_cpu_cfg(cpu); + #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { riscv_timer_init(cpu); From patchwork Tue Mar 14 16:49:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53007C6FD1F for ; Tue, 14 Mar 2023 16:53:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7sD-00083b-7V; Tue, 14 Mar 2023 12:51:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rn-0006xQ-Cj for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:19 -0400 Received: from mail-oo1-xc2a.google.com ([2607:f8b0:4864:20::c2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7ri-00037J-1V for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:12 -0400 Received: by mail-oo1-xc2a.google.com with SMTP id h18-20020a4abb92000000b00525397f569fso2407339oop.3 for ; Tue, 14 Mar 2023 09:51:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kLvyrtSvvuZg8uzOBdjg6jj7IyKLzGPxs656bAqgPdU=; b=Nm8wUb8g7VLlnX30F+sN1Z94B3+a9XYGZmQZATifFay57iDQtCgfaNGPsC2ABfmRVJ KGXN3V+Pa8xRYfK5WaH6yYrFFNANoapjkrTZ0CBEbWrImLYUXTEGUbEYQZNUglRvhtB+ MTZlkR/tiR17tv/0BP2mqAMiJXfA2WMRjCnTwvgNjDzNUh5I4nYMC57zAhVlgQvmaw9o MqIppD1wY9423xba1rRuR1FakDO3LurncFUX4NChOibWc8sBsc19WiNaIsJvrxP6gbAN ymkrN0AEj4VfOjHZe7jOlzafbZuWqPhAwlLqRxE8BZ9GJ/SeL4aHr0ESvLDO1xjW9MWz W80w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812668; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kLvyrtSvvuZg8uzOBdjg6jj7IyKLzGPxs656bAqgPdU=; b=B1sjQqS1sy+i11us9oaft8lJ3vot4RD4xDcyloBf2iBtmPzy72llii911iO55xrvRH Zf1Q8umxUJIVt8Q1SiUXlFYHWsun9t6MBwQMw1chySS8LWk4+5n6yN02/y+ODpPoN7oR j6+c2hd6BlF2P5ZIVi/DBnjEACRWR7Xqzhdj4wVSo+nOKw6tvOxcDP6FMJmp5d5D2Usb mL3/nHT9XSueETlxHXWWBrvJm0EQa6PF00OvLxz2izeA10O6eUgU5agrgz7KTHsK1uSk 2FWtjHRpsrN3GHOwlKFCp5JNe8DSP/0NjqN4/NjT4lkHHQ8xeVJB+zsFKdw3jVTrbUOV ++uQ== X-Gm-Message-State: AO0yUKVAKfBTNls2QMRAr+/v9VdR0T8xdAqIs4yvB4nTJJa9eUUjN8m3 u5e3Oc/rxtOfPgWdQUJ/Uv5erb0jvSVrUsOZlXI= X-Google-Smtp-Source: AK7set80C+pAlSwk50L91T0H99QsHglogqf9bI9ewY0ab0ODjn1sjB5uxQ0EoFRDa4gPj9l7TuXuOg== X-Received: by 2002:a4a:95c6:0:b0:525:129c:6165 with SMTP id p6-20020a4a95c6000000b00525129c6165mr17589170ooi.6.1678812668646; Tue, 14 Mar 2023 09:51:08 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.51.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:51:08 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 24/26] target/riscv: use misa_ext val in riscv_cpu_validate_extensions() Date: Tue, 14 Mar 2023 13:49:46 -0300 Message-Id: <20230314164948.539135-25-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=dbarboza@ventanamicro.com; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Similar to what we did with riscv_cpu_validate_misa_ext(), let's read all MISA bits from a misa_ext val instead of reading from the cpu->cfg object. This will allow write_misa() to use riscv_cpu_validate_extensions(). Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 25 ++++++++++++++----------- 1 file changed, 14 insertions(+), 11 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e423d3e2d2..5bd92e1cda 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1130,10 +1130,13 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) } /* - * Check consistency between chosen extensions. No changes - * in env->misa_ext are made. + * Check consistency between cpu->cfg extensions and a + * candidate misa_ext value. No changes in env->misa_ext + * are made. */ -static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) +static void riscv_cpu_validate_extensions(RISCVCPU *cpu, + uint32_t misa_ext, + Error **errp) { if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* @@ -1144,12 +1147,12 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) return; } - if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { + if (misa_ext & RVF && !cpu->cfg.ext_icsr) { error_setg(errp, "F extension requires Zicsr"); return; } - if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { + if ((cpu->cfg.ext_zawrs) && !(misa_ext & RVA)) { error_setg(errp, "Zawrs extension requires A extension"); return; } @@ -1158,13 +1161,13 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zfhmin = true; } - if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zfhmin && !(misa_ext & RVF)) { error_setg(errp, "Zfh/Zfhmin extensions require F extension"); return; } /* The V vector extension depends on the Zve64d extension */ - if (cpu->cfg.ext_v) { + if (misa_ext & RVV) { cpu->cfg.ext_zve64d = true; } @@ -1178,12 +1181,12 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) cpu->cfg.ext_zve32f = true; } - if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { + if (cpu->cfg.ext_zve64d && !(misa_ext & RVD)) { error_setg(errp, "Zve64d/V extensions require D extension"); return; } - if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { + if (cpu->cfg.ext_zve32f && !(misa_ext & RVF)) { error_setg(errp, "Zve32f/Zve64f extensions require F extension"); return; } @@ -1216,7 +1219,7 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, Error **errp) error_setg(errp, "Zfinx extension requires Zicsr"); return; } - if (cpu->cfg.ext_f) { + if (misa_ext & RVF) { error_setg(errp, "Zfinx cannot be supported together with F extension"); return; @@ -1378,7 +1381,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - riscv_cpu_validate_extensions(cpu, &local_err); + riscv_cpu_validate_extensions(cpu, env->misa_ext, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); return; From patchwork Tue Mar 14 16:49:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174764 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2FA34C05027 for ; Tue, 14 Mar 2023 16:52:46 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7sG-00009B-HE; Tue, 14 Mar 2023 12:51:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7rw-00072K-J8 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:27 -0400 Received: from mail-ot1-x32e.google.com ([2607:f8b0:4864:20::32e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rm-0002qQ-3O for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:20 -0400 Received: by mail-ot1-x32e.google.com with SMTP id r23-20020a05683001d700b00690eb18529fso8762723ota.1 for ; Tue, 14 Mar 2023 09:51:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=r84xJtHoIGB7ABAqtSobwcdMIMD2s20w0sZHcVJeXVo=; b=ItIR+YA5L0bcz4od03u1DfYT9SY9zVYw/LDV9i+eVAZVl3P4Y5jX31Q6HQngwIp48P rwm0pSusDRtzk8wPTcFuA9iZfqyWhSBncIDHrxEgUkgiP4+GzLGSV38s82SWuJhQjoxr PafUxXvjHW2qeuGIAQ+IuALJ9vqS7t1VXOnrXXJMMfg4yHtpwS4unkcQx61FA4juIsyV NL9/gp1xan7tvbMcBgYt2xH8jANWQD2u3xJvuYDkE7w727wLj9OddC/WtMBRkXG/PbJn 8a9AiN9CHOwKQUhs9rnLSZqlu9DFg5VlL9JRqUvhYjldZJZBX/gS3GYfnvQcje35TuK2 79jA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812671; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=r84xJtHoIGB7ABAqtSobwcdMIMD2s20w0sZHcVJeXVo=; b=gHuQ1oc8NHsiAkC8aM9nD8oqY2hqY7o30gq51HSoTOSP7R8RNwWEBnwTYjkITqyzQs 3as4zLALR8lAcS6CkljMJHu98IqXatgZ8Hztax+TyVcdwbWfL8Q6GsUZjsgKXcqYqg2L 7V1sOWyfI3DhRGhjHEOtopW/qOoj7BN/9jGLVNfGj9KrAPRBDrvTKvjGrhJQBLhD3O2E oE+sl9DgLzvcCyd5iyxOtK+/rC490caV0WGGv/LatlNhPiuyQiBIbsbTvjU+aafP07yD s8w9E3wGlVZi54alUz+Cq450p/F1Xd8q8jdS5gf1uR92gI3Lt4dlWSOQFz2MBsb7Dwv2 I7Mw== X-Gm-Message-State: AO0yUKVHnTBXupJ9Pk2Jl4o84RFLv95fqPanuedKMAXU5XwQfMmL7yH+ oEslmvUSFvSh/ck92dGqeXORn9mnBuFQuO8W+FU= X-Google-Smtp-Source: AK7set/58BhPhTnbIMDODReUTIltqEECJW/MBpsQA0nDper8mptUMiBe1bM9Ljvnu000d5JNTV5i2w== X-Received: by 2002:a05:6830:24a4:b0:68b:e391:324d with SMTP id v4-20020a05683024a400b0068be391324dmr18934702ots.0.1678812671712; Tue, 14 Mar 2023 09:51:11 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.51.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:51:11 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 25/26] target/riscv: rework write_misa() Date: Tue, 14 Mar 2023 13:49:47 -0300 Message-Id: <20230314164948.539135-26-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32e; envelope-from=dbarboza@ventanamicro.com; helo=mail-ot1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org write_misa() must use as much common logic as possible. We want to open code just the bits that are exclusive to the CSR write operation and TCG internals. Rewrite write_misa() to work as follows: - supress RVC right after verifying that we're not updating RVG; - mask the write using misa_ext_mask to avoid enabling unsupported extensions; - emulate the steps done by realize(): validate the candidate misa_ext val, then validate the configuration with the candidate misa_ext val, and finally commit the changes to cpu->cfg. If any of the validation steps fails simply ignore the write operation. Let's keep write_misa() as experimental for now until this logic gains enough mileage. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 12 +++++------- target/riscv/cpu.h | 6 ++++++ target/riscv/csr.c | 47 +++++++++++++++++++++------------------------- 3 files changed, 32 insertions(+), 33 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5bd92e1cda..4789a7b70d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1027,9 +1027,8 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } -static void riscv_cpu_validate_misa_ext(CPURISCVState *env, - uint32_t misa_ext, - Error **errp) +void riscv_cpu_validate_misa_ext(CPURISCVState *env, uint32_t misa_ext, + Error **errp) { Error *local_err = NULL; @@ -1134,9 +1133,8 @@ static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) * candidate misa_ext value. No changes in env->misa_ext * are made. */ -static void riscv_cpu_validate_extensions(RISCVCPU *cpu, - uint32_t misa_ext, - Error **errp) +void riscv_cpu_validate_extensions(RISCVCPU *cpu, uint32_t misa_ext, + Error **errp) { if (cpu->cfg.epmp && !cpu->cfg.pmp) { /* @@ -1227,7 +1225,7 @@ static void riscv_cpu_validate_extensions(RISCVCPU *cpu, } } -static void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu) +void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu) { if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dbb4df9df0..ca2ba6a647 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -593,6 +593,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); +void riscv_cpu_validate_misa_ext(CPURISCVState *env, uint32_t misa_ext, + Error **errp); +void riscv_cpu_validate_extensions(RISCVCPU *cpu, uint32_t misa_ext, + Error **errp); +void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu); + #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 918d442ebd..6f26e7dbcd 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1343,6 +1343,9 @@ static RISCVException read_misa(CPURISCVState *env, int csrno, static RISCVException write_misa(CPURISCVState *env, int csrno, target_ulong val) { + RISCVCPU *cpu = env_archcpu(env); + Error *local_err = NULL; + if (!riscv_cpu_cfg(env)->misa_w) { /* drop write to misa */ return RISCV_EXCP_NONE; @@ -1353,47 +1356,39 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } - /* 'I' or 'E' must be present */ - if (!(val & (RVI | RVE))) { - /* It is not, drop write to misa */ - return RISCV_EXCP_NONE; - } - - /* 'E' excludes all other extensions */ - if (val & RVE) { - /* - * when we support 'E' we can do "val = RVE;" however - * for now we just drop writes if 'E' is present. - */ - return RISCV_EXCP_NONE; - } - /* - * misa.MXL writes are not supported by QEMU. - * Drop writes to those bits. + * Suppress 'C' if next instruction is not aligned + * TODO: this should check next_pc */ + if ((val & RVC) && (GETPC() & ~3) != 0) { + val &= ~RVC; + } /* Mask extensions that are not supported by this hart */ val &= env->misa_ext_mask; - /* 'D' depends on 'F', so clear 'D' if 'F' is not present */ - if ((val & RVD) && !(val & RVF)) { - val &= ~RVD; + /* If nothing changed, do nothing. */ + if (val == env->misa_ext) { + return RISCV_EXCP_NONE; } /* - * Suppress 'C' if next instruction is not aligned - * TODO: this should check next_pc + * This flow is similar to what riscv_cpu_realize() does, + * with the difference that we will update env->misa_ext + * value if everything is ok. */ - if ((val & RVC) && (GETPC() & ~3) != 0) { - val &= ~RVC; + riscv_cpu_validate_misa_ext(env, val, &local_err); + if (local_err != NULL) { + return RISCV_EXCP_NONE; } - /* If nothing changed, do nothing. */ - if (val == env->misa_ext) { + riscv_cpu_validate_extensions(cpu, val, &local_err); + if (local_err != NULL) { return RISCV_EXCP_NONE; } + riscv_cpu_commit_cpu_cfg(cpu); + if (!(val & RVF)) { env->mstatus &= ~MSTATUS_FS; } From patchwork Tue Mar 14 16:49:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Henrique Barboza X-Patchwork-Id: 13174775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8A9FFC6FD1F for ; Tue, 14 Mar 2023 16:54:51 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pc7sA-0007iD-7C; Tue, 14 Mar 2023 12:51:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pc7ry-00072s-3V for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:27 -0400 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pc7rw-00037n-96 for qemu-devel@nongnu.org; Tue, 14 Mar 2023 12:51:25 -0400 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-17683b570b8so17931582fac.13 for ; Tue, 14 Mar 2023 09:51:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1678812675; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gkB0vzqH+m6CKp6htpyofVNxkBL9rh1LR/W7819esvg=; b=ZLvosooEoS3DJpnQztGPBWtBHJCwE8HhEwrErmdxyenSCt7tJkF58d0VWmcYR2QDWL hOPMRKn6Og5S9nZVP3k6dWDNa1co51YQK04Zlr99jghOJe8mnzJSG+LGM6+mUyewXVGO hUU90DCzaW5/4n8G87UTQYGLOsAzys34Ow/9hBjSql8JL1EaiJhYh/EIUEVFClvVsM5L MscVRHh5ugJekII4cW4114dsLeAtZFsR8FEysRd5J9mv/3A50iczuq4lUl/BdOSNADgO uo6ic4UeIFr9sXwVe6/0rfWEJahWoQwplaonJ9qmcbqY7O7RBTxTYvH95LJtO7IDLjEF xGxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1678812675; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gkB0vzqH+m6CKp6htpyofVNxkBL9rh1LR/W7819esvg=; b=od9fVft55Xhccvt1cDlNVBpBJ5SCOwx8MU3TFOI+O5Haf82ogJmSmrBDoewK5+MF7P VIF0Sftfv22ZC6bpOsubmnC295H6bAjMEVyqMT8H4O/coLG36tVghrlm6GKApvH7CYaa APnC+JvHkFIAi2rAb4pVDDaNFRPsoKGbaTnBpDOC9WyMjKg2G+GsDxQgNt0Wti490kx5 jaFQPdln9/2uIfsCGwTjoImpS8zMrQdC46kyXNjhbwpr2oK1fSJnDwQqmD1e3tPMW6ti s286tTH26yzWiR3pz+Y0XzGQHwemC6xCpFVa59TwyaTtmIDAtSJotL6NzmVZuG/fyjif 0F1g== X-Gm-Message-State: AO0yUKWpXd/oA9r6yAWrzX8w8W1TLJsdI2pbLzOZSXa6ASg5QaFw/RWK 65sv+he3yt/R2ymOhh1QB4kI8n725isUU7E8c9E= X-Google-Smtp-Source: AK7set+x3zGNygrJLqPJVfp6zR52y2zDSQH8ehIMyuOty1ocsKSmQ6EoSEe6lr0qGIX1GZPdmBNK4Q== X-Received: by 2002:a05:6870:5703:b0:172:2d00:99f7 with SMTP id k3-20020a056870570300b001722d0099f7mr21206413oap.20.1678812674876; Tue, 14 Mar 2023 09:51:14 -0700 (PDT) Received: from grind.dc1.ventanamicro.com ([177.95.89.231]) by smtp.gmail.com with ESMTPSA id 96-20020a9d04e9000000b0069451a9274bsm348689otm.28.2023.03.14.09.51.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Mar 2023 09:51:14 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, bmeng@tinylab.org, liweiwei@iscas.ac.cn, zhiwei_liu@linux.alibaba.com, palmer@rivosinc.com, Daniel Henrique Barboza Subject: [PATCH for-8.1 v2 26/26] target/riscv: update cpu->cfg misa bits in commit_cpu_cfg() Date: Tue, 14 Mar 2023 13:49:48 -0300 Message-Id: <20230314164948.539135-27-dbarboza@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230314164948.539135-1-dbarboza@ventanamicro.com> References: <20230314164948.539135-1-dbarboza@ventanamicro.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=dbarboza@ventanamicro.com; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org write_misa() is able to use the same validation workflow riscv_cpu_realize() uses. But it's still not capable of updating cpu->cfg misa props yet. We have no way of blocking future (and current) code from checking env->misa_ext (via riscv_has_ext()) or reading cpu->cfg directly, so our best alternative is to keep everything in sync. riscv_cpu_commit_cpu_cfg() now receives an extra 'misa_ext' parameter. If this val is different from the existing env->misa_ext, update env->misa and cpu->cfg with the new value. riscv_cpu_realize() will ignore this code since env->misa_ext isn't touched during validation, but write_misa() will use it to keep cpu->cfg in sync with the new env->misa_ext value. Signed-off-by: Daniel Henrique Barboza --- target/riscv/cpu.c | 16 ++++++++++++++-- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 3 +-- 3 files changed, 16 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4789a7b70d..059931daea 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1225,8 +1225,20 @@ void riscv_cpu_validate_extensions(RISCVCPU *cpu, uint32_t misa_ext, } } -void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu) +void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu, uint32_t misa_ext) { + CPURISCVState *env = &cpu->env; + + /* + * write_misa() needs to update cpu->cfg with the new + * MISA bits. This is a no-op for the riscv_cpu_realize() + * path. + */ + if (env->misa_ext != misa_ext) { + env->misa_ext = misa_ext; + riscv_set_cpucfg_with_misa(&cpu->cfg, misa_ext); + } + if (cpu->cfg.ext_zk) { cpu->cfg.ext_zkn = true; cpu->cfg.ext_zkr = true; @@ -1385,7 +1397,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp) return; } - riscv_cpu_commit_cpu_cfg(cpu); + riscv_cpu_commit_cpu_cfg(cpu, env->misa_ext); #ifndef CONFIG_USER_ONLY if (cpu->cfg.ext_sstc) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ca2ba6a647..befc3b8fff 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -597,7 +597,7 @@ void riscv_cpu_validate_misa_ext(CPURISCVState *env, uint32_t misa_ext, Error **errp); void riscv_cpu_validate_extensions(RISCVCPU *cpu, uint32_t misa_ext, Error **errp); -void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu); +void riscv_cpu_commit_cpu_cfg(RISCVCPU *cpu, uint32_t misa_ext); #define cpu_list riscv_cpu_list #define cpu_mmu_index riscv_cpu_mmu_index diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6f26e7dbcd..0da0ffdaed 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1387,7 +1387,7 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, return RISCV_EXCP_NONE; } - riscv_cpu_commit_cpu_cfg(cpu); + riscv_cpu_commit_cpu_cfg(cpu, val); if (!(val & RVF)) { env->mstatus &= ~MSTATUS_FS; @@ -1395,7 +1395,6 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, /* flush translation cache */ tb_flush(env_cpu(env)); - env->misa_ext = val; env->xl = riscv_cpu_mxl(env); return RISCV_EXCP_NONE; }