From patchwork Fri Mar 17 16:54:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 13179298 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BECD1C6FD1D for ; Fri, 17 Mar 2023 16:55:32 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pdDMG-0002xY-96; Fri, 17 Mar 2023 12:55:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pdDME-0002wF-Tq for qemu-devel@nongnu.org; Fri, 17 Mar 2023 12:55:10 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pdDMC-0001hJ-VT for qemu-devel@nongnu.org; Fri, 17 Mar 2023 12:55:10 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PdVb16bZ9z6J7TT; Sat, 18 Mar 2023 00:54:05 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 17 Mar 2023 16:55:05 +0000 To: Michael Tsirkin , Igor Mammedov , CC: , , , Fan Ni , Dave Jiang Subject: [RFC PATCH 1/4] hw/acpi: Make Aml and / or crs_range_set optional in build_crs Date: Fri, 17 Mar 2023 16:54:37 +0000 Message-ID: <20230317165440.24846-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317165440.24846-1-Jonathan.Cameron@huawei.com> References: <20230317165440.24846-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml100005.china.huawei.com (7.191.160.25) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron X-Patchwork-Original-From: Jonathan Cameron via From: Jonathan Cameron Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org This allows the same code to be used for two purposes. 1) To fill in the crs_range_set as is later used to generate the actual AML for the primary PCI host bridge. 2) Create the _CRS AML for the PXB bridges. The separation is need to allow for DSDT to be generated before an SSDT for any PXB instances present. Signed-off-by: Jonathan Cameron --- This could be refactored so that the if (crs) and if (crs_range_set) checks only occur once, but that then separates the iterating over the groups and will leave us with two locations to keep up to date for any future changes. If we did that it would probably make sense to just split the function. --- hw/acpi/aml-build.c | 75 +++++++++++++++++++++---------------- hw/i386/acpi-build.c | 5 ++- hw/pci-host/gpex-acpi.c | 5 ++- include/hw/acpi/aml-build.h | 4 +- 4 files changed, 51 insertions(+), 38 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index ea331a20d1..918cbb5b9d 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2266,11 +2266,10 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, } #endif -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, +void build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, uint32_t mmio32_offset, uint64_t mmio64_offset, - uint16_t bus_nr_offset) + uint16_t bus_nr_offset, Aml *crs) { - Aml *crs = aml_resource_template(); CrsRangeSet temp_range_set; CrsRangeEntry *entry; uint8_t max_bus = pci_bus_num(host->bus); @@ -2380,12 +2379,16 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, crs_range_merge(temp_range_set.io_ranges); for (i = 0; i < temp_range_set.io_ranges->len; i++) { entry = g_ptr_array_index(temp_range_set.io_ranges, i); - aml_append(crs, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0, entry->base, entry->limit, io_offset, - entry->limit - entry->base + 1)); - crs_range_insert(range_set->io_ranges, entry->base, entry->limit); + if (crs) { + aml_append(crs, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0, entry->base, entry->limit, io_offset, + entry->limit - entry->base + 1)); + } + if (range_set) { + crs_range_insert(range_set->io_ranges, entry->base, entry->limit); + } } crs_range_merge(temp_range_set.mem_ranges); @@ -2393,39 +2396,47 @@ Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, entry = g_ptr_array_index(temp_range_set.mem_ranges, i); assert(entry->limit <= UINT32_MAX && (entry->limit - entry->base + 1) <= UINT32_MAX); - aml_append(crs, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, - AML_MAX_FIXED, AML_NON_CACHEABLE, - AML_READ_WRITE, - 0, entry->base, entry->limit, mmio32_offset, - entry->limit - entry->base + 1)); - crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); + if (crs) { + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, + 0, entry->base, entry->limit, mmio32_offset, + entry->limit - entry->base + 1)); + } + if (range_set) { + crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); + } } crs_range_merge(temp_range_set.mem_64bit_ranges); for (i = 0; i < temp_range_set.mem_64bit_ranges->len; i++) { entry = g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); - aml_append(crs, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, - AML_MAX_FIXED, AML_NON_CACHEABLE, - AML_READ_WRITE, - 0, entry->base, entry->limit, mmio64_offset, + if (crs) { + aml_append(crs, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, + 0, entry->base, entry->limit, mmio64_offset, entry->limit - entry->base + 1)); - crs_range_insert(range_set->mem_64bit_ranges, - entry->base, entry->limit); + } + if (range_set) { + crs_range_insert(range_set->mem_64bit_ranges, + entry->base, entry->limit); + } } crs_range_set_free(&temp_range_set); - aml_append(crs, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0, - pci_bus_num(host->bus), - max_bus, - bus_nr_offset, - max_bus - pci_bus_num(host->bus) + 1)); - - return crs; + if (crs) { + aml_append(crs, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0, + pci_bus_num(host->bus), + max_bus, + bus_nr_offset, + max_bus - pci_bus_num(host->bus) + 1)); + } } /* ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors */ diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index ec857a117e..d79d1d6f13 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1606,8 +1606,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } aml_append(dev, build_prt(false)); - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, - 0, 0, 0, 0); + crs = aml_resource_template(); + build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, + 0, 0, 0, 0, crs); aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); aml_append(dsdt, scope); diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 7c7316bc96..6a52d3ea77 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -181,8 +181,9 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) * 1. The resources the pci-brige/pcie-root-port need. * 2. The resources the devices behind pxb need. */ - crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, - cfg->pio.base, 0, 0, 0); + crs = aml_resource_template(); + build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, + cfg->pio.base, 0, 0, 0, crs); aml_append(dev, aml_name_decl("_CRS", crs)); if (is_cxl) { diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index d1fb08514b..fc2b949fb5 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -479,9 +479,9 @@ void crs_replace_with_free_ranges(GPtrArray *ranges, void crs_range_set_init(CrsRangeSet *range_set); void crs_range_set_free(CrsRangeSet *range_set); -Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, +void build_crs(PCIHostState *host, CrsRangeSet *range_set, uint32_t io_offset, uint32_t mmio32_offset, uint64_t mmio64_offset, - uint16_t bus_nr_offset); + uint16_t bus_nr_offset, Aml *crs); void build_srat_memory(GArray *table_data, uint64_t base, uint64_t len, int node, MemoryAffinityFlags flags); From patchwork Fri Mar 17 16:54:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 13179300 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1B219C74A5B for ; Fri, 17 Mar 2023 16:56:02 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pdDMp-0003o7-JC; Fri, 17 Mar 2023 12:55:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pdDMi-0003ig-VO for qemu-devel@nongnu.org; Fri, 17 Mar 2023 12:55:40 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pdDMg-0001lu-PT for qemu-devel@nongnu.org; Fri, 17 Mar 2023 12:55:40 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.226]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PdVY83B0vz67M1h; Sat, 18 Mar 2023 00:52:28 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 17 Mar 2023 16:55:36 +0000 To: Michael Tsirkin , Igor Mammedov , CC: , , , Fan Ni , Dave Jiang Subject: [RFC PATCH 2/4] tests/acpi: Allow changes to DSDT.cxl/viot and SSDT.cxl/viot Date: Fri, 17 Mar 2023 16:54:38 +0000 Message-ID: <20230317165440.24846-3-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317165440.24846-1-Jonathan.Cameron@huawei.com> References: <20230317165440.24846-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml100006.china.huawei.com (7.191.160.224) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron X-Patchwork-Original-From: Jonathan Cameron via From: Jonathan Cameron Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Splitting the PXB parts out of DSDT will change these files. Signed-off-by: Jonathan Cameron --- tests/data/acpi/q35/SSDT.cxl | 0 tests/data/acpi/q35/SSDT.viot | 0 tests/qtest/bios-tables-test-allowed-diff.h | 4 ++++ 3 files changed, 4 insertions(+) diff --git a/tests/data/acpi/q35/SSDT.cxl b/tests/data/acpi/q35/SSDT.cxl new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/data/acpi/q35/SSDT.viot b/tests/data/acpi/q35/SSDT.viot new file mode 100644 index 0000000000..e69de29bb2 diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios-tables-test-allowed-diff.h index dfb8523c8b..0307b25f93 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,5 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/q35/DSDT.cxl", +"tests/data/acpi/q35/DSDT.viot", +"tests/data/acpi/q35/SSDT.cxl", +"tests/data/acpi/q35/SSDT.viot", From patchwork Fri Mar 17 16:54:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 13179301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8EA0C6FD1D for ; Fri, 17 Mar 2023 16:56:23 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pdDNH-0005kJ-BZ; Fri, 17 Mar 2023 12:56:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pdDNG-0005j2-1A for qemu-devel@nongnu.org; Fri, 17 Mar 2023 12:56:14 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pdDNC-0001vK-PU for qemu-devel@nongnu.org; Fri, 17 Mar 2023 12:56:13 -0400 Received: from lhrpeml500005.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4PdVcz2X6Dz67xNS; Sat, 18 Mar 2023 00:55:47 +0800 (CST) Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhrpeml500005.china.huawei.com (7.191.163.240) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Fri, 17 Mar 2023 16:56:07 +0000 To: Michael Tsirkin , Igor Mammedov , CC: , , , Fan Ni , Dave Jiang Subject: [RFC PATCH 3/4] hw/i386/acpi: Separate PXB related parts of DSDT into an SSDT table. Date: Fri, 17 Mar 2023 16:54:39 +0000 Message-ID: <20230317165440.24846-4-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317165440.24846-1-Jonathan.Cameron@huawei.com> References: <20230317165440.24846-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml100005.china.huawei.com (7.191.160.25) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron X-Patchwork-Original-From: Jonathan Cameron via From: Jonathan Cameron Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The dependencies between the CRS entries and bus numbers due to PCI eXpander Bridges taking resources from the primary bus make this a slightly complex dance. The rules we have to fit into are: 1) FACP is first table in RSDT and points to the DSDT. 2) Thus DSDT is created before FACP 3) SSDT must be pointed to by a later entry in RSDT so must be created after DSDT. 4) The main PCI bus in DSDT contains entries that are dependent on bus walks done to establish the entries for the PXB buses which are now in SSDT. Solution is to precompute what will go in SSDT (CRS ranges and bus numbers) then to create the DSDT + FACTP as normal. After that create the SSDT, including rerunning some of the earlier bus walking code (which will give the same answers). Signed-off-by: Jonathan Cameron --- RFC because: - There are lots of ways this could be done and I'm not sure people will like this one. - Is it a good idea in general? - Should we just move all the PCI stuff including the main bus to an SSDT table? - That feels like overkill to me. --- hw/i386/acpi-build.c | 250 +++++++++++++++++++++++++++---------------- 1 file changed, 160 insertions(+), 90 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index d79d1d6f13..f0c4959455 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1423,28 +1423,158 @@ static void build_acpi0017(Aml *table) aml_append(table, scope); } +/* + * Precompute the crs ranges and bus numbers that will be used in PXB entries + * in PXB SSDT. + */ +static void get_pxb_info(MachineState *machine, CrsRangeSet *crs_range_set, + int *root_bus_limit) +{ + PCMachineState *pcms = PC_MACHINE(machine); + PCIBus *bus = PC_MACHINE(machine)->bus; + + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num = pci_bus_num(bus); + + /* look only for expander root buses */ + if (!pci_bus_is_root(bus)) { + continue; + } + + if (bus_num < *root_bus_limit) { + *root_bus_limit = bus_num - 1; + } + + build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), crs_range_set, + 0, 0, 0, 0, NULL); + + /* Handle the ranges for the PXB expanders */ + if (pci_bus_is_cxl(bus)) { + MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; + uint64_t base = mr->addr; + + crs_range_insert(crs_range_set->mem_ranges, base, + base + memory_region_size(mr) - 1); + } + } +} + +static void build_pxb_ssdt(GArray *table_offsets, GArray *table_data, BIOSLinker *linker, + MachineState *machine) +{ + X86MachineState *x86ms = X86_MACHINE(machine); + AcpiTable table = { .sig = "SSDT", .rev = 1, + .oem_id = x86ms->oem_id, .oem_table_id = "PXB" }; + Aml *ssdt, *scope, *dev, *crs; + bool cxl_present = false; + PCIBus *bus; + + /* + * Check if there are any PXB instances so as to avoid the aml setup + * if there won't be a PXB SSDT + */ + bus = PC_MACHINE(machine)->bus; + if (!bus) { + return; + } + + QLIST_FOREACH(bus, &bus->child, sibling) { + if (pci_bus_is_root(bus)) { + break; + } + } + if (!bus) { + return; + } + + /* SSDT will exist so add a pointer that will end up RSDT/XSDT */ + acpi_add_table(table_offsets, table_data); + acpi_table_begin(&table, table_data); + ssdt = init_aml_allocator(); + + bus = PC_MACHINE(machine)->bus; + + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num = pci_bus_num(bus); + uint8_t numa_node = pci_bus_numa_node(bus); + + /* look only for expander root buses */ + if (!pci_bus_is_root(bus)) { + continue; + } + + scope = aml_scope("\\_SB"); + + if (pci_bus_is_cxl(bus)) { + dev = aml_device("CL%.02X", bus_num); + } else { + dev = aml_device("PI%.02X", bus_num); + } + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + if (pci_bus_is_cxl(bus)) { + struct Aml *pkg = aml_package(2); + + aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); + aml_append(pkg, aml_eisaid("PNP0A08")); + aml_append(pkg, aml_eisaid("PNP0A03")); + aml_append(dev, aml_name_decl("_CID", pkg)); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + build_cxl_osc_method(dev); + } else if (pci_bus_is_express(bus)) { + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); + + /* Expander bridges do not have ACPI PCI Hot-plug enabled */ + aml_append(dev, build_q35_osc_method(true)); + } else { + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); + } + + if (numa_node != NUMA_NODE_UNASSIGNED) { + aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); + } + + aml_append(dev, build_prt(false)); + crs = aml_resource_template(); + build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), NULL, + 0, 0, 0, 0, crs); + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(scope, dev); + aml_append(ssdt, scope); + + if (pci_bus_is_cxl(bus)) { + cxl_present = true; + } + } + + if (cxl_present) { + build_acpi0017(ssdt); + } + g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); + acpi_table_end(linker, &table); + free_aml_allocator(); +} + static void build_dsdt(GArray *table_data, BIOSLinker *linker, AcpiPmInfo *pm, AcpiMiscInfo *misc, - Range *pci_hole, Range *pci_hole64, MachineState *machine) + Range *pci_hole, Range *pci_hole64, MachineState *machine, + CrsRangeSet *crs_range_set, int root_bus_limit) { Object *i440fx = object_resolve_type_unambiguous(TYPE_I440FX_PCI_HOST_BRIDGE); Object *q35 = object_resolve_type_unambiguous(TYPE_Q35_HOST_DEVICE); CrsRangeEntry *entry; Aml *dsdt, *sb_scope, *scope, *dev, *method, *field, *pkg, *crs; - CrsRangeSet crs_range_set; PCMachineState *pcms = PC_MACHINE(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); X86MachineState *x86ms = X86_MACHINE(machine); AcpiMcfgInfo mcfg; bool mcfg_valid = !!acpi_get_mcfg(&mcfg); uint32_t nr_mem = machine->ram_slots; - int root_bus_limit = 0xFF; - PCIBus *bus = NULL; #ifdef CONFIG_TPM TPMIf *tpm = tpm_find(); #endif - bool cxl_present = false; int i; VMBusBridge *vmbus_bridge = vmbus_bridge_find(); AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = x86ms->oem_id, @@ -1557,78 +1687,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, pcms->memhp_io_base); } - crs_range_set_init(&crs_range_set); - bus = PC_MACHINE(machine)->bus; - if (bus) { - QLIST_FOREACH(bus, &bus->child, sibling) { - uint8_t bus_num = pci_bus_num(bus); - uint8_t numa_node = pci_bus_numa_node(bus); - - /* look only for expander root buses */ - if (!pci_bus_is_root(bus)) { - continue; - } - - if (bus_num < root_bus_limit) { - root_bus_limit = bus_num - 1; - } - - scope = aml_scope("\\_SB"); - - if (pci_bus_is_cxl(bus)) { - dev = aml_device("CL%.02X", bus_num); - } else { - dev = aml_device("PC%.02X", bus_num); - } - aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); - aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); - if (pci_bus_is_cxl(bus)) { - struct Aml *pkg = aml_package(2); - - aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); - aml_append(pkg, aml_eisaid("PNP0A08")); - aml_append(pkg, aml_eisaid("PNP0A03")); - aml_append(dev, aml_name_decl("_CID", pkg)); - aml_append(dev, aml_name_decl("_ADR", aml_int(0))); - build_cxl_osc_method(dev); - } else if (pci_bus_is_express(bus)) { - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A08"))); - aml_append(dev, aml_name_decl("_CID", aml_eisaid("PNP0A03"))); - - /* Expander bridges do not have ACPI PCI Hot-plug enabled */ - aml_append(dev, build_q35_osc_method(true)); - } else { - aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A03"))); - } - - if (numa_node != NUMA_NODE_UNASSIGNED) { - aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); - } - - aml_append(dev, build_prt(false)); - crs = aml_resource_template(); - build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, - 0, 0, 0, 0, crs); - aml_append(dev, aml_name_decl("_CRS", crs)); - aml_append(scope, dev); - aml_append(dsdt, scope); - - /* Handle the ranges for the PXB expanders */ - if (pci_bus_is_cxl(bus)) { - MemoryRegion *mr = &pcms->cxl_devices_state.host_mr; - uint64_t base = mr->addr; - - cxl_present = true; - crs_range_insert(crs_range_set.mem_ranges, base, - base + memory_region_size(mr) - 1); - } - } - } - - if (cxl_present) { - build_acpi0017(dsdt); - } - /* * At this point crs_range_set has all the ranges used by pci * busses *other* than PCI0. These ranges will be excluded from @@ -1636,7 +1694,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, * too. */ if (mcfg_valid) { - crs_range_insert(crs_range_set.mem_ranges, + crs_range_insert(crs_range_set->mem_ranges, mcfg.base, mcfg.base + mcfg.size - 1); } @@ -1654,9 +1712,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, AML_POS_DECODE, AML_ENTIRE_RANGE, 0x0000, 0x0000, 0x0CF7, 0x0000, 0x0CF8)); - crs_replace_with_free_ranges(crs_range_set.io_ranges, 0x0D00, 0xFFFF); - for (i = 0; i < crs_range_set.io_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.io_ranges, i); + crs_replace_with_free_ranges(crs_range_set->io_ranges, 0x0D00, 0xFFFF); + for (i = 0; i < crs_range_set->io_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set->io_ranges, i); aml_append(crs, aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, AML_ENTIRE_RANGE, @@ -1669,11 +1727,11 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, AML_CACHEABLE, AML_READ_WRITE, 0, 0x000A0000, 0x000BFFFF, 0, 0x00020000)); - crs_replace_with_free_ranges(crs_range_set.mem_ranges, + crs_replace_with_free_ranges(crs_range_set->mem_ranges, range_lob(pci_hole), range_upb(pci_hole)); - for (i = 0; i < crs_range_set.mem_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.mem_ranges, i); + for (i = 0; i < crs_range_set->mem_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set->mem_ranges, i); aml_append(crs, aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, AML_NON_CACHEABLE, AML_READ_WRITE, @@ -1682,11 +1740,11 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, } if (!range_is_empty(pci_hole64)) { - crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, + crs_replace_with_free_ranges(crs_range_set->mem_64bit_ranges, range_lob(pci_hole64), range_upb(pci_hole64)); - for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { - entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); + for (i = 0; i < crs_range_set->mem_64bit_ranges->len; i++) { + entry = g_ptr_array_index(crs_range_set->mem_64bit_ranges, i); aml_append(crs, aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, @@ -1722,8 +1780,6 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_CRS", crs)); aml_append(scope, dev); - crs_range_set_free(&crs_range_set); - /* reserve PCIHP resources */ if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { dev = aml_device("PHPR"); @@ -2485,6 +2541,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) AcpiMiscInfo misc; AcpiMcfgInfo mcfg; Range pci_hole = {}, pci_hole64 = {}; + int root_bus_limit = 0xFF; + CrsRangeSet crs_range_set; uint8_t *u; size_t aml_len = 0; GArray *tables_blob = tables->table_data; @@ -2527,10 +2585,20 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) facs = tables_blob->len; build_facs(tables_blob); + crs_range_set_init(&crs_range_set); + + /* + * Before creating the entries for the main PCI bus, establish + * if space needs to be made for any PXB instances. + */ + get_pxb_info(machine, &crs_range_set, &root_bus_limit); /* DSDT is pointed to by FADT */ dsdt = tables_blob->len; build_dsdt(tables_blob, tables->linker, &pm, &misc, - &pci_hole, &pci_hole64, machine); + &pci_hole, &pci_hole64, machine, &crs_range_set, + root_bus_limit); + + crs_range_set_free(&crs_range_set); /* Count the size of the DSDT and SSDT, we will need it for legacy * sizing of ACPI tables. @@ -2546,6 +2614,8 @@ void acpi_build(AcpiBuildTables *tables, MachineState *machine) build_fadt(tables_blob, tables->linker, &pm.fadt, oem_id, oem_table_id); aml_len += tables_blob->len - fadt; + build_pxb_ssdt(table_offsets, tables_blob, tables->linker, machine); + acpi_add_table(table_offsets, tables_blob); acpi_build_madt(tables_blob, tables->linker, x86ms, ACPI_DEVICE_IF(x86ms->acpi_dev), x86ms->oem_id, From patchwork Fri Mar 17 16:54:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Cameron X-Patchwork-Id: 13179302 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BB9A3C6FD1D for ; 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Fri, 17 Mar 2023 16:56:37 +0000 To: Michael Tsirkin , Igor Mammedov , CC: , , , Fan Ni , Dave Jiang Subject: [RFC PATCH 4/4] tests/acpi: Updated DSDT and SSDT due to move of PXB info to SSDT Date: Fri, 17 Mar 2023 16:54:40 +0000 Message-ID: <20230317165440.24846-5-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230317165440.24846-1-Jonathan.Cameron@huawei.com> References: <20230317165440.24846-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhrpeml100005.china.huawei.com (7.191.160.25) To lhrpeml500005.china.huawei.com (7.191.163.240) X-CFilter-Loop: Reflected Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-to: Jonathan Cameron X-Patchwork-Original-From: Jonathan Cameron via From: Jonathan Cameron Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Signed-off-by: Jonathan Cameron --- tests/data/acpi/q35/DSDT.cxl | Bin 9673 -> 8474 bytes tests/data/acpi/q35/DSDT.viot | Bin 9470 -> 8429 bytes tests/data/acpi/q35/SSDT.cxl | Bin 0 -> 1235 bytes tests/data/acpi/q35/SSDT.viot | Bin 0 -> 1077 bytes tests/qtest/bios-tables-test-allowed-diff.h | 4 ---- 5 files changed, 4 deletions(-) diff --git a/tests/data/acpi/q35/DSDT.cxl b/tests/data/acpi/q35/DSDT.cxl index f049f414f0e789324e82916cfd0aa955211408c4..88783c368d3afeea2fd20e9e72e4807436aeb78d 100644 GIT binary patch delta 24 gcmX@=Dl*K|~C{g8# zg(yr>fPsayct?mCv9NSQLQF`7zkvk?TJz3sBM@Qhh==#yec!uxmhPu}Ztj)|vsq*J z5`gshH93i@-Bm5Cd z{d1az4NEvp$Gj}|E#Uwvie(%?H$@?d5O%iHVpWKLpb&Pl#c5uvH^85hw;UhbooaC6 zsY|x}2QHDJ<#+G7Eg%ZCNBXdhUDGK5t6FB@2|*eQ1`3&Bo5*9uJXDmiLc#MlH(Er8 znJ9vu2jF*IoZa&z@V%bn!hJV%0=$a4onceNd2|{;lOXx_qiAJ6DU0yCbN(QT_`xLS zB|71uBSUW%WDVQ);44N2HbDP_kUWhEX%a0#1k-UNGI(|BKN4+nOh^+XZh;5U delta 717 zcmaFs_|KEeCDWK+4I<4@7x* zy6`w&;NswjcZRT-C(dY~IX1}j3yN|Hb?`DU@h~tj7yu#A zqYRY{0w~@zf_hT{;!Pkmq`j%Ypn%nzhEQ(`K)ea02Cp}D2*;)Xg8(X@hL^Cdj;)WjOT0 z(mNOR)@guy_CqKiq?b@fsud_EQ zFSqvew<{m-rRd~`FFU*M2DLXU&#!B%r{4x$mc_aS^a}dLfQ;L7*{mCBN8zq?KwXDi zDVjM7hjfZ*#8CbMtu`#A?E;r_B9Z;;Kot{~a3D1(Q{56a;1rax0jKU|iA>x*&ZVqP00n!N2 z5y*!fCXW!~63L7Z4t{X3-)0(2CJFR?fS~7L@4hcV;P+h*9(b{f*J{{#afP{0uK}oZ zZF=WPvU;9|75JH%yGRn}VjS}tnfQ{Cp+5z(ifL!?8Eppke-lxWry^2Q5uy7pqJK<8 u6%^5yXl5A-ieoo*h^6n_kVX&y literal 0 HcmV?d00001 diff --git a/tests/data/acpi/q35/SSDT.viot b/tests/data/acpi/q35/SSDT.viot index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..6a746d34b01b87bc054093cd38801fddadb2daad 100644 GIT binary patch literal 1077 zcmeH@KWoB37>D0Pi}7mV{I?a%M=(mEOTk<+Xlr9I76l7QG?W&XqqKt!f^-UwhIUSi zAEY0lTZev-j`q$3htkE}JMMnR^S*a*k7en-lQe*EN;+E8lFb1DJ_NSNz|?r+^YXQA z5qtQomd#eZD%n>p9kC$9;L&X9IrS4slC8z3RH>b@JC>GSOhD87N@N^_xA`K%!^`jb zPvyAr+J8_#&c1FI6O?8RHI@>~I^~<=JE-DBcp2UaGk$$jQ=;NB+>~R6d4)QhyyarV zpHfznQX^}d-5$__ICm(x??&duMRWS(A`wQ^zjsG~QZSBiIA%>*_WQPRp@YYPumvgu z`EZQHEg=a>ZHWdRolQpw!{K@jfd@c+m%SZ$0#Gk-TzGU>4)fBr@?}&AjzG*Yp;b1y m;^`l?wM4BPt7WlQyQ5ke