From patchwork Sun Mar 19 13:21:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13180378 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F2F11C7618A for ; Sun, 19 Mar 2023 13:21:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbjCSNVh (ORCPT ); Sun, 19 Mar 2023 09:21:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230289AbjCSNVe (ORCPT ); Sun, 19 Mar 2023 09:21:34 -0400 Received: from mail-il1-x12a.google.com (mail-il1-x12a.google.com [IPv6:2607:f8b0:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0AE1F222CE; Sun, 19 Mar 2023 06:21:34 -0700 (PDT) Received: by mail-il1-x12a.google.com with SMTP id h5so5247731ile.13; Sun, 19 Mar 2023 06:21:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679232093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/8K00mhrFcQs9Z7odhdrKSasE5j1cIS7BmQWAR2zLjA=; b=N3LiLEhbiW97PwGOJH/Wbl7pLxJaNt0oR2gwkupf8el4rgsLamm/hKm/UGWfsnnYxA P84TQXwzCNOpJ1xGBy5zzyI1Fx2nWdJOkgLhTQy0fEgkGlj8EfPBdZRR2UqDVtV8tFuk ewv8kPrR6PD49urM9a9UCDAAIizBrmzEscmHHMRJo+oezAZnXto2hWhGaryW6iEt2Q/P ipCRf/CFYw5/9whB9Yi9lL0lyxAmaNDrCEIls8SvZm9EBoJmOg/Sii2DKKssMyoB0b1b uTIYE0VsISwmDXAbXVNyfMUuoKr8Kq7FOZpGtgyaLcEblvT0jU7JVEl4H/QHVJlxpaPQ 2uMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679232093; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/8K00mhrFcQs9Z7odhdrKSasE5j1cIS7BmQWAR2zLjA=; b=OimvPLOM7RrhIHvyuTL5jQ9U5VyKpm3SFRv7E5LaFVhTrSfP5xFhAtOVTd/eGacN1S gJPwWIYyB8K8gVlGzVYuuRp6s8JM0HzQ5wSY+v3aun8r5BeBlI5IIxcJH5ktWLtDuozo iKD7/QfoTl5H9gFzh+qmo/7CZIvJTmMtmmDolwQLLH5JGRq6cwUKZFuWZiHZMPjoyZt2 hstLauQd2xQjYIW18tAkJAk69PN7bwHIvEKSao5Tc76qV8L1oGG00ydkbMobEJ3XkMtO Y8TeVDrHfpbzDsEI0fuebKcNFUXjvfLiPjn+wwQqm9hix7yC1fP1BEtxbPXLwDCxaQIS pqkA== X-Gm-Message-State: AO0yUKV9SPZekqKG/rE4iasnF8LihL3m1tDTTl2dVgTp4kvKcN3mc9v2 Tx69l5l6mCcmpzgphcXestWGzQU/YVs= X-Google-Smtp-Source: AK7set8u5TAbtClNj4mHrUK2nLeJif8QArEGoDDl2cMxGZGRibszXccwl7TqKPfruuxZlaWvflMUuw== X-Received: by 2002:a92:ce85:0:b0:323:338:cc36 with SMTP id r5-20020a92ce85000000b003230338cc36mr3355844ilo.8.1679232093044; Sun, 19 Mar 2023 06:21:33 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id a23-20020a027357000000b00406227162fesm2363460jae.32.2023.03.19.06.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Mar 2023 06:21:32 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] clk: imx: composite-8m: Add support to determine_rate Date: Sun, 19 Mar 2023 08:21:18 -0500 Message-Id: <20230319132120.6347-2-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230319132120.6347-1-aford173@gmail.com> References: <20230319132120.6347-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Similar to imx/clk-composite-93 and imx/clk-divider-gate, the imx8m_clk_composite_divider_ops can support determine_rate. Without this the parent clocks are set to a fixed value, and if a consumer needs a slower reate, the clock is divided, but the division is only as good as the parent clock rate. With this added, the system can attempt to adjust the parent rate if the proper flags are set which can lead to a more precise clock value. Signed-off-by: Adam Ford Reviewed-by: Peng Fan diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..3b63e47f088f 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -119,10 +119,17 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, return ret; } +static int clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return clk_divider_ops.determine_rate(hw, req); +} + static const struct clk_ops imx8m_clk_composite_divider_ops = { .recalc_rate = imx8m_clk_composite_divider_recalc_rate, .round_rate = imx8m_clk_composite_divider_round_rate, .set_rate = imx8m_clk_composite_divider_set_rate, + .determine_rate = clk_divider_determine_rate, }; static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) From patchwork Sun Mar 19 13:21:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13180379 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D7AAC7619A for ; Sun, 19 Mar 2023 13:21:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230377AbjCSNVj (ORCPT ); Sun, 19 Mar 2023 09:21:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230359AbjCSNVh (ORCPT ); Sun, 19 Mar 2023 09:21:37 -0400 Received: from mail-io1-xd32.google.com (mail-io1-xd32.google.com [IPv6:2607:f8b0:4864:20::d32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 14F87222D4; Sun, 19 Mar 2023 06:21:36 -0700 (PDT) Received: by mail-io1-xd32.google.com with SMTP id p17so2605281ioj.10; Sun, 19 Mar 2023 06:21:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679232095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ICE/28jdiWQEExDCz4xlI7/MltQ5deN6UZpAbZEvh1g=; b=dwsNCcZCAaA8Y95qfxLCA6gLC/K5wYt/9k7ZquFa43Fw5t8CDxySvGP93vagrin9h+ 9Ruyraig8kgFcB0eLmEIqwN+zpo7ETEMJirizprUeyBchxaZuPMKtZyaTxLisJ3bguUB QGxU1SvqDYURdkUbw0Rz6XckvfoHZLXHET+/XgqvDof5lfZPQSLcrUy/0Ks6U5PCV4m+ vXGBp88/pm8M3QZJHiTjOncseRwaPYIXMdvk2mG7chqijMJ93WZzDSC4DQrr+hjWrvnr gl7/TZkD2DoHfrXGtL3WWdygPKaXpO0A+CmbmVAytN8uHj9Z+ykVkKl0pysyIlWSZL5r kkmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679232095; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ICE/28jdiWQEExDCz4xlI7/MltQ5deN6UZpAbZEvh1g=; b=NR+ZQGHqwOcbpkFe8zCe9so6UK+LhkdGIjt0q5J+msOyWf55VTgWYD2pqWZjy2cnNs JhcWs41Abc3altgemP4ojRnTw77Q7+Q/WO+AOQDHVWWnFxd7I1hoIXf5Ldk094X1Q0rd 5YUQdgrzW9LV64jt6n9vu2a1ZweYbgau8aEjfFgJvCRlVwyCoZQAOBS+SDnSUE02LJgB a0WKVeO9R+drm2A+3SkEr/jafeDWL+DoNDyx+zKDLzFv4NJyKUuM3+QFaV+k9GGuHnqI 5gGcRUPcjBQu9pY0VMUyQg1sI9t9gFJS5Xa5QD7fDuD70laDvQ1WVF9v4o1C0m0O99AI TsqQ== X-Gm-Message-State: AO0yUKUd1uSEzuO8SMYPaC38vlqIBFUylexc9SaPdvrgJz5+vy9hJtoT RVMv7ByBYQM7FOJ1JPnNdpr4RvSP7iA= X-Google-Smtp-Source: AK7set9jE3Qxtj29KL2vNJruxgw0I0I8Rgfvxf+OhLddCuPylzgqtHa2ahdOmGXz8gVXWjtyP7qaMw== X-Received: by 2002:a5d:8254:0:b0:750:6c44:3454 with SMTP id n20-20020a5d8254000000b007506c443454mr3247920ioo.12.1679232095050; Sun, 19 Mar 2023 06:21:35 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id a23-20020a027357000000b00406227162fesm2363460jae.32.2023.03.19.06.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Mar 2023 06:21:34 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate Date: Sun, 19 Mar 2023 08:21:19 -0500 Message-Id: <20230319132120.6347-3-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230319132120.6347-1-aford173@gmail.com> References: <20230319132120.6347-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org By default the display pixel clock needs to be evenly divide down from 594MHz which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll1 594000000 video_pll1_bypass 594000000 video_pll1_out 594000000 lcdif_pixel 148500000 Now that composite-8m supports determine_rate, we can allow lcdif_pixel to set the parent rate which then switches every clock in the chain to a new frequency when lcdif_pixel cannot evenly divide from video_pll1_out. Signed-off-by: Adam Ford diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index b618892170f2..075f643e3f35 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -468,7 +468,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_hw_composite("pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380); hws[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_hw_composite("pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400); hws[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_hw_composite("dc_pixel", imx8mm_dc_pixel_sels, base + 0xa480); - hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500); + hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite_flags("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); hws[IMX8MM_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mm_sai1_sels, base + 0xa580); hws[IMX8MM_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mm_sai2_sels, base + 0xa600); hws[IMX8MM_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mm_sai3_sels, base + 0xa680); From patchwork Sun Mar 19 13:21:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13180380 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC7CBC6FD1F for ; Sun, 19 Mar 2023 13:21:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230370AbjCSNVl (ORCPT ); Sun, 19 Mar 2023 09:21:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229622AbjCSNVj (ORCPT ); Sun, 19 Mar 2023 09:21:39 -0400 Received: from mail-il1-x12d.google.com (mail-il1-x12d.google.com [IPv6:2607:f8b0:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D91D822794; Sun, 19 Mar 2023 06:21:37 -0700 (PDT) Received: by mail-il1-x12d.google.com with SMTP id h11so5253901ild.11; Sun, 19 Mar 2023 06:21:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679232097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9jRLas+X66DwX3DvgENKtWbw6Tk9kAguCjzndTr3/Fs=; b=J9DyP+7/MlVewq+owGn+geALUpv3MYnFqyNPqqv5xtvFRYzsxIAUC1RKIvEqAubk93 rTfJBEv0/IHksl3L9dZ8MSkyuHdPgkmBuK5rmTe80SnBIsEmGdc4T1iOwohN9J01GLIW 56VlyFvZrmDiRNuOqgZlEL9midprlFaCt8JpZJlVYxs4S+90wcKY5XcJ9jf63stCyU+v fznUYlOJQCbtzfOObWyRK40qDfCYef8jWOJmKsCFr0phBiMiOSJQ9XN+lKqb8dP9RrZL lvwgAfdCOHivA1K9vcDxj6amxv6St5eZJzCAoW9pgK4jqs1MkyH8EGwtc1rZWCaiJ9uS O0HA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679232097; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9jRLas+X66DwX3DvgENKtWbw6Tk9kAguCjzndTr3/Fs=; b=PgBhLnMtfnun+A7kZWz+4VGvjllOrBZB6Qw+9emoFT4mflgnEXu8/JxVbk+uNe4HrB 13dfweNzhuJFoi5pqWy/m+0X4wsbcrcbe/BYq1j8dTMoXPDQXiE7ZSOELgBZ5U6rw80Z GctdhV7rLMrKJ2pLbQzDvofD/0sNbGFmuhiwqLshFKz2Y/vnP47wsRx4tdyqMk+DKYR0 U24Iofr3C5+0UVl+3m5fnWeTTJxkUsgx9bTWQB9kJZtGzIGdZvgTCjQDWIqtX3cZ2Dre KFH3UvSCB5C10lMsw3aQJi0idVVBLzNwIFTp/3rQGUL0MdXIE2lwwn/ay7fLWu25xCzm QVDw== X-Gm-Message-State: AO0yUKVZ8R+i7HCJX2hgtREEOSfsWuiUERfZKSy4UxAv6bOMkJk2dxMr yRuznsohiUV9HM7/sGceYW4ckaR8fSU= X-Google-Smtp-Source: AK7set9E8JPLYVAomIXIP7dJobm+AJ5GJXDPiDKsreSdMdMszzhI8MANxoCTEXwrxH+EYLP4mq/BIA== X-Received: by 2002:a05:6e02:686:b0:318:aa8a:6453 with SMTP id o6-20020a056e02068600b00318aa8a6453mr3334106ils.7.1679232096852; Sun, 19 Mar 2023 06:21:36 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan (c-75-72-166-104.hsd1.mn.comcast.net. [75.72.166.104]) by smtp.gmail.com with ESMTPSA id a23-20020a027357000000b00406227162fesm2363460jae.32.2023.03.19.06.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Mar 2023 06:21:36 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate Date: Sun, 19 Mar 2023 08:21:20 -0500 Message-Id: <20230319132120.6347-4-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230319132120.6347-1-aford173@gmail.com> References: <20230319132120.6347-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 148500000 disp_pixel_clk 148500000 Now that composite-8m supports determine_rate, we can allow disp_pixel to set the parent rate which then switches every clock in the chain to a new frequency when disp_pixel cannot evenly divide from video_pll_out. Signed-off-by: Adam Ford diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index a042ed3a9d6c..4b23a4648600 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -470,7 +470,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000); hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080); - hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500); + hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite_flags("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600); hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mn_sai3_sels, base + 0xa680); hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mn_sai5_sels, base + 0xa780); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 3d94722bbf99..621b0e84ef27 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -417,6 +417,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, _imx8m_clk_hw_composite(name, parent_names, reg, \ 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) +#define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \ + _imx8m_clk_hw_composite(name, parent_names, reg, \ + 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags) + #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ _imx8m_clk_hw_composite(name, parent_names, reg, \ 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL)