From patchwork Tue Mar 21 02:31:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13182174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB919C6FD1D for ; Tue, 21 Mar 2023 02:32:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229912AbjCUCcN (ORCPT ); Mon, 20 Mar 2023 22:32:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49238 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229900AbjCUCcL (ORCPT ); Mon, 20 Mar 2023 22:32:11 -0400 Received: from mail-io1-xd2e.google.com (mail-io1-xd2e.google.com [IPv6:2607:f8b0:4864:20::d2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB92A36FE2; Mon, 20 Mar 2023 19:31:49 -0700 (PDT) Received: by mail-io1-xd2e.google.com with SMTP id f14so6361614iow.5; Mon, 20 Mar 2023 19:31:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679365909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sTo3F/m/SxPHAqEXuebTGyXW2LKYPQRkLUm8e3SciVw=; b=jtWm45HrEd24L4clToDHgC5saIGxP00MYJ3iEBnl+HmrGuNeaWFNY0Y2ArHLweqAAy Xuspfga6nrYvqO1IUmUGeUeolYCixybPy7ejgqDex647tY9G6Ys1q41Uvbjcr4c37yGv WxiZld+rhzzulzvvPFOQwqyiOmQzEt1TCQSo26UTMk7G4SwpU1Ds2iH9FKJU4L9FUFu2 EsHlNqd++9PdTtCKOp0Jw9WI5hdVvQ26NKHKRmCwnEugnoZ/KdzdQXQqxKH813DH2vgI VE4qUcT4HUVoS/ifDGZ5ZLoss+RCVWrONgBPipOJOT6PQwGoeb7y2cIYoTYBTIhiczSM WFQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679365909; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sTo3F/m/SxPHAqEXuebTGyXW2LKYPQRkLUm8e3SciVw=; b=Nf4X6MFCD8ZkiWotau4qrop44lNkN1vvfA3t20zVI9lkz/NRKG56aLfSW2Nh7yg/f3 O8WQR/zps0+tY+DVugiOXfEIpelCJ74Un/kmjxmYNDZDYVKPIrwND5o6H+AuK/kprIqQ 3XNpYeFI6nSGkD6VkPMrxQQMc8RAl4P/5YeXGUVHa2yi++dr2uyV9a3eQLKUYazDkFnw EhaXij6HDHjjtlD3Z2n6fiYxqHYKNmK89wGD3HASBG5iwH66hiJzhuUicUcFcyczqZ8h nSCw0dUThapssUdGNGjp1+4C8KN3sSVCJjFLHmk/vJIUbRha+UlKoHTjoLbQc8d36FJp 0dEg== X-Gm-Message-State: AO0yUKVehGuSlKVtKPzgGGvBBKQ6ZNDA8Svmrc35WoKgV/VvwekOIBgt s00KVBYqM+7UvDC4FRhJlGWoOOw/sh0= X-Google-Smtp-Source: AK7set+Ibe5aCthxCU51+MZKk4ghN93jB6Jsfgn9wVamJsAh+oHNdRypAPnQ3pM47QAflwju4EDD1Q== X-Received: by 2002:a5d:895a:0:b0:74c:e456:629d with SMTP id b26-20020a5d895a000000b0074ce456629dmr699641iot.7.1679365908946; Mon, 20 Mar 2023 19:31:48 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:1387:3268:b209:f4ec]) by smtp.gmail.com with ESMTPSA id a28-20020a027a1c000000b004065ad317fdsm2241200jac.151.2023.03.20.19.31.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 19:31:48 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 1/4] clk: imx: composite-8m: Add support to determine_rate Date: Mon, 20 Mar 2023 21:31:33 -0500 Message-Id: <20230321023136.57986-2-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230321023136.57986-1-aford173@gmail.com> References: <20230321023136.57986-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Similar to imx/clk-composite-93 and imx/clk-divider-gate, the imx8m_clk_composite_divider_ops can support determine_rate. Without this the parent clocks are set to a fixed value, and if a consumer needs a slower reate, the clock is divided, but the division is only as good as the parent clock rate. With this added, the system can attempt to adjust the parent rate if the proper flags are set which can lead to a more precise clock value. Signed-off-by: Adam Ford --- V2: No Change diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..3b63e47f088f 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -119,10 +119,17 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, return ret; } +static int clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return clk_divider_ops.determine_rate(hw, req); +} + static const struct clk_ops imx8m_clk_composite_divider_ops = { .recalc_rate = imx8m_clk_composite_divider_recalc_rate, .round_rate = imx8m_clk_composite_divider_round_rate, .set_rate = imx8m_clk_composite_divider_set_rate, + .determine_rate = clk_divider_determine_rate, }; static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) From patchwork Tue Mar 21 02:31:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13182175 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCBFFC76195 for ; Tue, 21 Mar 2023 02:32:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229473AbjCUCcN (ORCPT ); Mon, 20 Mar 2023 22:32:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49250 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229898AbjCUCcL (ORCPT ); Mon, 20 Mar 2023 22:32:11 -0400 Received: from mail-il1-x133.google.com (mail-il1-x133.google.com [IPv6:2607:f8b0:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80B4539296; Mon, 20 Mar 2023 19:31:51 -0700 (PDT) Received: by mail-il1-x133.google.com with SMTP id h11so7481081ild.11; Mon, 20 Mar 2023 19:31:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679365910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YBy7Uhw8n9XJJSSN0OA/4i8xS/Flp3zKZhGIeWwusVM=; b=iQatrVrSpMzWM30D/QDBzwK1QzX3H9/6UAnHFb1yBrZ6JUUw82BPT4EPusvdKi6pjl VuNXhHXYsPY0VGRKIy+IFLw9Rd2Zrad/wTtin7ziRywR5F3PfHy6TzJbdW0QD9TtFRPs FUSrOocS0aBhsv4wedUXG3LohtmMEzWfFfwLAHBDAA8Fi4ZmCz4sbxjcNlqrT49HgIkv mKIOPPmNS/VYSkKTIRvR+9qZ/cTa3lKow3n2Uh04LLP31Yt+y+r+Y6pYvshtyyGcWEQ7 xAzRfovnLhDkFlLpPMaXkyG0Te9DdSXthpmauHL38b82JH0BbNKSBYf33V+sLcDaPwiT lPCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679365910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBy7Uhw8n9XJJSSN0OA/4i8xS/Flp3zKZhGIeWwusVM=; b=yA3snMwm6qpI1yZXWRNF8V1q7xk+5Tp+hmEswu+C03a2Yo5PRx+j7R8vCCTBzGM6Fp TyNZFYE8nGzHzxU/NNUeZtTVVYde6WacxegIQDcetdB75HWQlaSdDeYUhpE/H03U/gwY YVaEddzDulOYpyLx59G0yy4jdHEDjpZ9ZjNknj2T2rOj1MCHWmTwLqqzghYiie4qGxh8 Nt+6T0++VXrdYMQmFZyRD37L5T2TxdiLvOw6FsQHi8yntFNPxh1H7AY9aZ3USRCBnx1P voUb8o+4s1y9+fsBL6q9keKJoKoQztHiHvL0reWyUB5YDlsjfGMzqSK9q5TuwLQR1ILp LncA== X-Gm-Message-State: AO0yUKULXSZ0XSbLUsOx+7PcNcmWwY+/f5Hh7h/O049Qs7PVHSf2umCc uhxMA8BPimPoxtMbroQEHRac/1uiNqI= X-Google-Smtp-Source: AK7set9vcTeQrv+uY9TyXI19wR3n5BkdxkTtvMfVMUNnyt8RgvFbS0D7h3ZFNj2n45e0XVTDmmeRyQ== X-Received: by 2002:a92:d312:0:b0:318:aac7:d7aa with SMTP id x18-20020a92d312000000b00318aac7d7aamr517200ila.29.1679365910474; Mon, 20 Mar 2023 19:31:50 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:1387:3268:b209:f4ec]) by smtp.gmail.com with ESMTPSA id a28-20020a027a1c000000b004065ad317fdsm2241200jac.151.2023.03.20.19.31.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 19:31:50 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 2/4] clk: imx: Add imx8m_clk_hw_composite_flags macro Date: Mon, 20 Mar 2023 21:31:34 -0500 Message-Id: <20230321023136.57986-3-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230321023136.57986-1-aford173@gmail.com> References: <20230321023136.57986-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags. Signed-off-by: Adam Ford --- V2: Split into its own patch and re-order to fix build error diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 3d94722bbf99..621b0e84ef27 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -417,6 +417,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, _imx8m_clk_hw_composite(name, parent_names, reg, \ 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) +#define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \ + _imx8m_clk_hw_composite(name, parent_names, reg, \ + 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags) + #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ _imx8m_clk_hw_composite(name, parent_names, reg, \ 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) From patchwork Tue Mar 21 02:31:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13182176 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90D1BC77B60 for ; Tue, 21 Mar 2023 02:32:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229920AbjCUCcO (ORCPT ); Mon, 20 Mar 2023 22:32:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229901AbjCUCcM (ORCPT ); Mon, 20 Mar 2023 22:32:12 -0400 Received: from mail-il1-x12f.google.com (mail-il1-x12f.google.com [IPv6:2607:f8b0:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65FB3399D3; Mon, 20 Mar 2023 19:31:53 -0700 (PDT) Received: by mail-il1-x12f.google.com with SMTP id r4so7490550ilt.8; Mon, 20 Mar 2023 19:31:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679365912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=n/mm5G0PkOndQQapwu4nkn1W5qAmcqtIfUJayOecLk0=; b=njQQ2EZ6+w4LBgLXRCDOA1u/7yBrAiap9M56rD9qLhp8bs3ohxOy5MjiVFuMarc+PJ 5ifchgcAVvsBA0HIYA90NPsQau9ZJgJ/qGCV6HN5EINCiiIlTxhXUR3XOyvEPQVdHsPA wVAhNWso3D8bz+51lpszZqRXycM+P/1iiJN2DrYsP8qcv5XW0HVew+5IfCT3Kc65xenM Sa7cu0z4L5h9CLJPUM/ndxB7u421CfqPkUBXh8oGkkCx425O22GJEiuA1BuxDMmEsjsy 0rSGTSgWh6uqZEow46y6hGw+FxlxAJ9MeeL6dtSnLlkkrivn0u6RSGmO1YipG8O5f2BE 5z1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679365912; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n/mm5G0PkOndQQapwu4nkn1W5qAmcqtIfUJayOecLk0=; b=frNiWb9f0pHIbIAbnTJafmXBvEKtoob6DZ/vAxBUYPpI9PYlXEf+MtPKOnC3qpYw0D 5ObWXEjxMtNE+YEWkvQt6Kkc5IJanBrRszhnMTpWbC3aHBRiyZcNLwxfZofxXSzv3eNz fC3Ib5E74bUIRnGQU/azWZAHbpDMR7Md6KuC+YICW6qOvC/I4x3YOsrMd9Dt9L/2S0KX y1sBsXUnj+wBopc7Ky0AcEMMlZ/bZED8nQ8aai9NB1jPKqavOgAIrPn3IPVTYtU6dyRN 08+RE64Bs0WSsl+tjR0A4DYLIhySXZqzkk9ZWnr1w2GadUQF7vHG1w15MMpHsgz1BZsg M81g== X-Gm-Message-State: AO0yUKXDjEXXhirBybsSpgYAKpz7NkJ2SujF2J5GOSEIDtQuZrCiYNxJ C5HSlKxXrilGsrIMmC0J54/uWzFl/84= X-Google-Smtp-Source: AK7set/xGd4TZlxrqYJ02heVW2VbJ5R2Z1EZ24Lg2WVPoEgarTmsm6XiI/xSD+9eq4JwVthB9RTdvA== X-Received: by 2002:a92:4b0a:0:b0:317:93dc:10f5 with SMTP id m10-20020a924b0a000000b0031793dc10f5mr524195ilg.19.1679365912239; Mon, 20 Mar 2023 19:31:52 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:1387:3268:b209:f4ec]) by smtp.gmail.com with ESMTPSA id a28-20020a027a1c000000b004065ad317fdsm2241200jac.151.2023.03.20.19.31.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 19:31:51 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 3/4] clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate Date: Mon, 20 Mar 2023 21:31:35 -0500 Message-Id: <20230321023136.57986-4-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230321023136.57986-1-aford173@gmail.com> References: <20230321023136.57986-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org By default the display pixel clock needs to be evenly divide down from 594MHz which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll1 594000000 video_pll1_bypass 594000000 video_pll1_out 594000000 lcdif_pixel 148500000 Now that composite-8m supports determine_rate, we can allow lcdif_pixel to set the parent rate which then switches every clock in the chain to a new frequency when lcdif_pixel cannot evenly divide from video_pll1_out. Signed-off-by: Adam Ford --- V2: No Change diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index b618892170f2..075f643e3f35 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -468,7 +468,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_hw_composite("pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380); hws[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_hw_composite("pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400); hws[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_hw_composite("dc_pixel", imx8mm_dc_pixel_sels, base + 0xa480); - hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500); + hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite_flags("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); hws[IMX8MM_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mm_sai1_sels, base + 0xa580); hws[IMX8MM_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mm_sai2_sels, base + 0xa600); hws[IMX8MM_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mm_sai3_sels, base + 0xa680); From patchwork Tue Mar 21 02:31:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13182177 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82D57C761A6 for ; Tue, 21 Mar 2023 02:32:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229931AbjCUCcP (ORCPT ); Mon, 20 Mar 2023 22:32:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229916AbjCUCcO (ORCPT ); Mon, 20 Mar 2023 22:32:14 -0400 Received: from mail-il1-x129.google.com (mail-il1-x129.google.com [IPv6:2607:f8b0:4864:20::129]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B977A39283; 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Mon, 20 Mar 2023 19:31:53 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V2 4/4] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate Date: Mon, 20 Mar 2023 21:31:36 -0500 Message-Id: <20230321023136.57986-5-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230321023136.57986-1-aford173@gmail.com> References: <20230321023136.57986-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 148500000 disp_pixel_clk 148500000 Now that composite-8m supports determine_rate, we can allow disp_pixel to set the parent rate which then switches every clock in the chain to a new frequency when disp_pixel cannot evenly divide from video_pll_out. Signed-off-by: Adam Ford --- V2: Move imx8m_clk_hw_composite_flags macro into its own patch diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index a042ed3a9d6c..4b23a4648600 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -470,7 +470,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000); hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080); - hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500); + hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite_flags("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600); hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mn_sai3_sels, base + 0xa680); hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mn_sai5_sels, base + 0xa780);