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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 01/11] xen/arm: Use the correct format specifier Date: Tue, 21 Mar 2023 14:03:47 +0000 Message-ID: <20230321140357.24094-2-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E652:EE_|MW4PR12MB7381:EE_ X-MS-Office365-Filtering-Correlation-Id: 0cd21dab-a0d9-4a55-3ed1-08db2a1527a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 16Bam4HOJdKdD2t+DXbG6+5Qv+pSPmM0DnY4bjy+daVlzR0Z7u7S2Xf4VKvIrqQMXWtl9teTrqvR0z4xihLHm6jfl/cYUZS6WEXPG/UiiN2ifrV66rJVzEh08/V4BzKvA7AqvWAdnJFBql66favQweXHKG/874WQAXy//CIx1FVfUdNSIt7ro0xFbPetfGQrKC1U2chNt+65abmPsRVS3zeFxMNGe0q8LmXHNBBqs+IvMUC6tjpr2P3y0vGRmdlO+pGrojAgaDN1+LgXXqLUSYuo/CZqn0LshyiaNYJpM1oqDoGRNFj0k3kPysjaOQGumtfaXAXYvdlQj9rAF4HHGhg/7Smvc7pCt2wbmaP27H4VASm83mCr/IUM1nHJ9pgE5aEKmlAPKcprwzHlXG0RQHpomRt3n25iKHvHXHUyS8ayNFRMuPLSUUoMpGMHKF8c9zyFfhJ8Or8iIuty81/YP4QSLCRAJ6NAoWBECvVkADIZelgCyDweTIm7pt6LfunX1lrN7hYMjM6Z0ujLBUCBaioqvfx8oVtaR/VML0AsuQC2LGkEwpNfvOWEz3rEvz5f6sJoka0bB2zrpN3I/YfhB6uQrC2DyfiH0Wqi7DLTt8gRy2skX6LO8ygR5gM5443ibFUm+xtDstRKH8x8VLdSVD/ZN6a5fCLmzsBmbS/bYSG1qsvxkf2iRP0dBfLw5tTWPWzVDFzBKn5MoukDVxnXRYWPvOUcuPlofpcPqHeFYI8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(346002)(376002)(39860400002)(396003)(451199018)(46966006)(40470700004)(36840700001)(86362001)(82310400005)(40460700003)(36756003)(40480700001)(103116003)(4326008)(83380400001)(8676002)(6916009)(478600001)(70206006)(316002)(70586007)(54906003)(1076003)(336012)(2616005)(966005)(6666004)(47076005)(426003)(186003)(26005)(356005)(82740400003)(8936002)(5660300002)(7416002)(36860700001)(41300700001)(81166007)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:04:15.0162 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0cd21dab-a0d9-4a55-3ed1-08db2a1527a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E652.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7381 1. One should use 'PRIpaddr' to display 'paddr_t' variables. However, while creating nodes in fdt, the address (if present in the node name) should be represented using 'PRIx64'. This is to be in conformance with the following rule present in https://elinux.org/Device_Tree_Linux . node names "unit-address does not have leading zeros" As 'PRIpaddr' introduces leading zeros, we cannot use it. So, we have introduced a wrapper ie domain_fdt_begin_node() which will represent physical address using 'PRIx64'. 2. One should use 'PRIx64' to display 'u64' in hex format. The current use of 'PRIpaddr' for printing PTE is buggy as this is not a physical address. Signed-off-by: Ayan Kumar Halder Reviewed-by: Stefano Stabellini Acked-by: Julien Grall --- Changes from - v3 - 1. Extracted the patch from https://lists.xenproject.org/archives/html/xen-devel/2023-02/msg00655.html and added to this series. 2. No changes done. xen/arch/arm/domain_build.c | 64 +++++++++++++++++++++++-------------- xen/arch/arm/gic-v2.c | 6 ++-- xen/arch/arm/mm.c | 2 +- 3 files changed, 44 insertions(+), 28 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 9707eb7b1b..15fa88e977 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1288,6 +1288,39 @@ static int __init fdt_property_interrupts(const struct kernel_info *kinfo, return res; } +/* + * Wrapper to convert physical address from paddr_t to uint64_t and + * invoke fdt_begin_node(). This is required as the physical address + * provided as part of node name should not contain any leading + * zeroes. Thus, one should use PRIx64 (instead of PRIpaddr) to append + * unit (which contains the physical address) with name to generate a + * node name. + */ +static int __init domain_fdt_begin_node(void *fdt, const char *name, + uint64_t unit) +{ + /* + * The size of the buffer to hold the longest possible string (i.e. + * interrupt-controller@ + a 64-bit number + \0). + */ + char buf[38]; + int ret; + + /* ePAPR 3.4 */ + ret = snprintf(buf, sizeof(buf), "%s@%"PRIx64, name, unit); + + if ( ret >= sizeof(buf) ) + { + printk(XENLOG_ERR + "Insufficient buffer. Minimum size required is %d\n", + (ret + 1)); + + return -FDT_ERR_TRUNCATED; + } + + return fdt_begin_node(fdt, buf); +} + static int __init make_memory_node(const struct domain *d, void *fdt, int addrcells, int sizecells, @@ -1296,8 +1329,6 @@ static int __init make_memory_node(const struct domain *d, unsigned int i; int res, reg_size = addrcells + sizecells; int nr_cells = 0; - /* Placeholder for memory@ + a 64-bit number + \0 */ - char buf[24]; __be32 reg[NR_MEM_BANKS * 4 /* Worst case addrcells + sizecells */]; __be32 *cells; @@ -1314,9 +1345,7 @@ static int __init make_memory_node(const struct domain *d, dt_dprintk("Create memory node\n"); - /* ePAPR 3.4 */ - snprintf(buf, sizeof(buf), "memory@%"PRIx64, mem->bank[i].start); - res = fdt_begin_node(fdt, buf); + res = domain_fdt_begin_node(fdt, "memory", mem->bank[i].start); if ( res ) return res; @@ -1375,16 +1404,13 @@ static int __init make_shm_memory_node(const struct domain *d, { uint64_t start = mem->bank[i].start; uint64_t size = mem->bank[i].size; - /* Placeholder for xen-shmem@ + a 64-bit number + \0 */ - char buf[27]; const char compat[] = "xen,shared-memory-v1"; /* Worst case addrcells + sizecells */ __be32 reg[GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS]; __be32 *cells; unsigned int len = (addrcells + sizecells) * sizeof(__be32); - snprintf(buf, sizeof(buf), "xen-shmem@%"PRIx64, mem->bank[i].start); - res = fdt_begin_node(fdt, buf); + res = domain_fdt_begin_node(fdt, "xen-shmem", mem->bank[i].start); if ( res ) return res; @@ -2716,12 +2742,9 @@ static int __init make_gicv2_domU_node(struct kernel_info *kinfo) __be32 reg[(GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS) * 2]; __be32 *cells; const struct domain *d = kinfo->d; - /* Placeholder for interrupt-controller@ + a 64-bit number + \0 */ - char buf[38]; - snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIx64, - vgic_dist_base(&d->arch.vgic)); - res = fdt_begin_node(fdt, buf); + res = domain_fdt_begin_node(fdt, "interrupt-controller", + vgic_dist_base(&d->arch.vgic)); if ( res ) return res; @@ -2771,14 +2794,10 @@ static int __init make_gicv3_domU_node(struct kernel_info *kinfo) int res = 0; __be32 *reg, *cells; const struct domain *d = kinfo->d; - /* Placeholder for interrupt-controller@ + a 64-bit number + \0 */ - char buf[38]; unsigned int i, len = 0; - snprintf(buf, sizeof(buf), "interrupt-controller@%"PRIx64, - vgic_dist_base(&d->arch.vgic)); - - res = fdt_begin_node(fdt, buf); + res = domain_fdt_begin_node(fdt, "interrupt-controller", + vgic_dist_base(&d->arch.vgic)); if ( res ) return res; @@ -2858,11 +2877,8 @@ static int __init make_vpl011_uart_node(struct kernel_info *kinfo) __be32 reg[GUEST_ROOT_ADDRESS_CELLS + GUEST_ROOT_SIZE_CELLS]; __be32 *cells; struct domain *d = kinfo->d; - /* Placeholder for sbsa-uart@ + a 64-bit number + \0 */ - char buf[27]; - snprintf(buf, sizeof(buf), "sbsa-uart@%"PRIx64, d->arch.vpl011.base_addr); - res = fdt_begin_node(fdt, buf); + res = domain_fdt_begin_node(fdt, "sbsa-uart", d->arch.vpl011.base_addr); if ( res ) return res; diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 61802839cb..5d4d298b86 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -1049,7 +1049,7 @@ static void __init gicv2_dt_init(void) if ( csize < SZ_8K ) { printk(XENLOG_WARNING "GICv2: WARNING: " - "The GICC size is too small: %#"PRIx64" expected %#x\n", + "The GICC size is too small: %#"PRIpaddr" expected %#x\n", csize, SZ_8K); if ( platform_has_quirk(PLATFORM_QUIRK_GIC_64K_STRIDE) ) { @@ -1280,11 +1280,11 @@ static int __init gicv2_init(void) gicv2.map_cbase += aliased_offset; printk(XENLOG_WARNING - "GICv2: Adjusting CPU interface base to %#"PRIx64"\n", + "GICv2: Adjusting CPU interface base to %#"PRIpaddr"\n", cbase + aliased_offset); } else if ( csize == SZ_128K ) printk(XENLOG_WARNING - "GICv2: GICC size=%#"PRIx64" but not aliased\n", + "GICv2: GICC size=%#"PRIpaddr" but not aliased\n", csize); gicv2.map_hbase = ioremap_nocache(hbase, PAGE_SIZE); diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index f758cad545..b99806af99 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -263,7 +263,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, pte = mapping[offsets[level]]; - printk("%s[0x%03x] = 0x%"PRIpaddr"\n", + printk("%s[0x%03x] = 0x%"PRIx64"\n", level_strs[level], offsets[level], pte.bits); if ( level == 3 || !pte.walk.valid || !pte.walk.table ) From patchwork Tue Mar 21 14:03:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13182810 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 22F0CC761A6 for ; Tue, 21 Mar 2023 14:04:53 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.512667.792748 (Exim 4.92) (envelope-from ) id 1pecbS-0005IG-W4; Tue, 21 Mar 2023 14:04:42 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 512667.792748; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:04:35.8159 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e1394ce-77dd-4191-09aa-08db2a15340c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B077.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5965 rangeset_{xxx}_range() functions are invoked with 'start' and 'size' as arguments which are either 'uint64_t' or 'paddr_t'. However, the function accepts 'unsigned long' for 'start' and 'size'. 'unsigned long' is 32 bits for ARM_32. Thus, there is an implicit downcasting from 'uint64_t'/'paddr_t' to 'unsigned long' when invoking rangeset_{xxx}_range(). So, it may seem there is a possibility of lose of data due to truncation. In reality, 'start' and 'size' are always page aligned. And ARM_32 currently supports 40 bits as the width of physical address. So if the addresses are page aligned, the last 12 bits contain zeroes. Thus, we could instead pass page frame number which will contain 28 bits (40-12 on Arm_32) and this can be represented using 'unsigned long'. On Arm_64, this change will not induce any adverse side effect as the width of physical address is 48 bits. Thus, the width of 'mfn' (ie 48 - 12 = 36) can be represented using 'unsigned long' (which is 64 bits wide). Signed-off-by: Ayan Kumar Halder --- Changes from - v3 - 1. Extracted the patch from https://lists.xenproject.org/archives/html/xen-devel/2023-02/msg00657.html and added it to this series. 2. Modified add_ext_regions(). This accepts a frame number instead of physical address. xen/arch/arm/domain_build.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 15fa88e977..24b12b7512 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1500,10 +1500,13 @@ static int __init make_resv_memory_node(const struct domain *d, return res; } -static int __init add_ext_regions(unsigned long s, unsigned long e, void *data) +static int __init add_ext_regions(unsigned long s_pfn, unsigned long e_pfn, + void *data) { struct meminfo *ext_regions = data; paddr_t start, size; + paddr_t s = PFN_UP(s_pfn); + paddr_t e = PFN_UP(e_pfn); if ( ext_regions->nr_banks >= ARRAY_SIZE(ext_regions->bank) ) return 0; @@ -1566,7 +1569,8 @@ static int __init find_unallocated_memory(const struct kernel_info *kinfo, { start = bootinfo.mem.bank[i].start; end = bootinfo.mem.bank[i].start + bootinfo.mem.bank[i].size; - res = rangeset_add_range(unalloc_mem, start, end - 1); + res = rangeset_add_range(unalloc_mem, PFN_DOWN(start), + PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to add: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1580,7 +1584,8 @@ static int __init find_unallocated_memory(const struct kernel_info *kinfo, { start = assign_mem->bank[i].start; end = assign_mem->bank[i].start + assign_mem->bank[i].size; - res = rangeset_remove_range(unalloc_mem, start, end - 1); + res = rangeset_remove_range(unalloc_mem, PFN_DOWN(start), + PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1595,7 +1600,8 @@ static int __init find_unallocated_memory(const struct kernel_info *kinfo, start = bootinfo.reserved_mem.bank[i].start; end = bootinfo.reserved_mem.bank[i].start + bootinfo.reserved_mem.bank[i].size; - res = rangeset_remove_range(unalloc_mem, start, end - 1); + res = rangeset_remove_range(unalloc_mem, PFN_DOWN(start), + PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1607,7 +1613,7 @@ static int __init find_unallocated_memory(const struct kernel_info *kinfo, /* Remove grant table region */ start = kinfo->gnttab_start; end = kinfo->gnttab_start + kinfo->gnttab_size; - res = rangeset_remove_range(unalloc_mem, start, end - 1); + res = rangeset_remove_range(unalloc_mem, PFN_DOWN(start), PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1617,7 +1623,7 @@ static int __init find_unallocated_memory(const struct kernel_info *kinfo, start = 0; end = (1ULL << p2m_ipa_bits) - 1; - res = rangeset_report_ranges(unalloc_mem, start, end, + res = rangeset_report_ranges(unalloc_mem, PFN_DOWN(start), PFN_DOWN(end), add_ext_regions, ext_regions); if ( res ) ext_regions->nr_banks = 0; @@ -1639,7 +1645,7 @@ static int __init handle_pci_range(const struct dt_device_node *dev, start = addr & PAGE_MASK; end = PAGE_ALIGN(addr + len); - res = rangeset_remove_range(mem_holes, start, end - 1); + res = rangeset_remove_range(mem_holes, PFN_DOWN(start), PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1677,7 +1683,7 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, /* Start with maximum possible addressable physical memory range */ start = 0; end = (1ULL << p2m_ipa_bits) - 1; - res = rangeset_add_range(mem_holes, start, end); + res = rangeset_add_range(mem_holes, PFN_DOWN(start), PFN_DOWN(end)); if ( res ) { printk(XENLOG_ERR "Failed to add: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1708,7 +1714,8 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, start = addr & PAGE_MASK; end = PAGE_ALIGN(addr + size); - res = rangeset_remove_range(mem_holes, start, end - 1); + res = rangeset_remove_range(mem_holes, PFN_DOWN(start), + PFN_DOWN(end - 1)); if ( res ) { printk(XENLOG_ERR "Failed to remove: %#"PRIpaddr"->%#"PRIpaddr"\n", @@ -1735,7 +1742,7 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, start = 0; end = (1ULL << p2m_ipa_bits) - 1; - res = rangeset_report_ranges(mem_holes, start, end, + res = rangeset_report_ranges(mem_holes, PFN_DOWN(start), PFN_DOWN(end), add_ext_regions, ext_regions); if ( res ) ext_regions->nr_banks = 0; From patchwork Tue Mar 21 14:03:49 2023 Content-Type: text/plain; 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pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 03/11] xen/arm: Typecast the DT values into paddr_t Date: Tue, 21 Mar 2023 14:03:49 +0000 Message-ID: <20230321140357.24094-4-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E653:EE_|DM4PR12MB8570:EE_ X-MS-Office365-Filtering-Correlation-Id: ad916c65-605f-4a92-8d18-08db2a153826 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Qu7nSqp7DQl1GBXTapTs2grj2MNKqrYBQMWuQ22DeYp2El4SEsxnc4OcG99FizanYYtbuPfHJdXPXrbrMXsiTk+JIHpcC94ehk1EpVpLQ5RSgIs/UNPtYHfyqLxl80/Yc0z/B9vLVu4pchVKqgSSPt/bHf+RB6ZKxxbth8gi/HN/gpV4PaGJQ+eBT8GxjaSCFFktdSPZWIDWml5PKIY9+4LagmvuFk2dBusTkmKOeunmfuy4QB2Dly/dPmmG1e6EFm1oPDXN6jwEmFy9HdU3HFNVUweykAQ7t+FYytVsen3i4E4k8sVn/Yfu4v+VxZ9HTb3blvLHnab/drF/DUGVW1XgwKhtht/TqsWIzaphR/x0EnEsKX7vCR2VlJJpTQo5fqX8EsCpSj6rtAWmIcwI57OMwst6bzjGRCasqVWD0HFRr2zeX4gLbHev2uJye7SINQOFGhFFvyJXRGBZMp4eOXNC7LJg3ZWWtwHBj3X3ySq0Pe8/XM5eZiP4SiTP0uvoicTiSrbjDBxf9T/CDzWB1TTEsgk8AF2J9iO8uzl0GNW8dPxoh33ly7h9AxM97AyAGWXDrbd02JleE+ySI4UtFw3VRUDQIFwmBBiKNV+He3kci7R0lQ5+VQtspKQgEZAPK4fKgbp+OXFfJuuD4deDGWv4FJP/syFeWyI9bqaJKDliLHvlW7VdT0NdfREuUICndz8z22dFfK0U155xWfcOKFdQwVWePUPNfwb2ZFMj9XM= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(396003)(376002)(346002)(39860400002)(136003)(451199018)(36840700001)(40470700004)(46966006)(316002)(86362001)(83380400001)(36756003)(336012)(8936002)(40480700001)(41300700001)(47076005)(26005)(1076003)(186003)(2906002)(82310400005)(6916009)(4326008)(70586007)(70206006)(8676002)(40460700003)(426003)(6666004)(2616005)(30864003)(5660300002)(82740400003)(81166007)(54906003)(36860700001)(103116003)(356005)(7416002)(478600001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:04:42.7006 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ad916c65-605f-4a92-8d18-08db2a153826 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E653.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8570 In future, we wish to support 32 bit physical address. However, the current dt and fdt functions can only read u64 values. We wish to make the DT functions read 32bit as well 64bit values (depending on the width of physical address). Also, we wish to detect if any truncation has occurred (ie while reading 32bit physical addresses from 64bit values read from DT). device_tree_get_reg() should now be able to return paddr_t. This is invoked by various callers to get DT address and size. For fdt_get_mem_rsv(), we have introduced wrapper ie fdt_get_mem_rsv_paddr() while will invoke fdt_get_mem_rsv() and translate uint64_t to paddr_t. The reason being we cannot modify fdt_get_mem_rsv() as it has been imported from external source. For dt_read_number(), we have also introduced a wrapper ie dt_read_paddr() to read physical addresses. We chose not to modify the original function as it been used in places where it needs to specifically 64bit values from dt (For eg dt_property_read_u64()). Xen prints an error when it detects a truncation (during typecast between uint64_t and paddr_t). It is not possible to return an error in all scenarios. So, it is user's responsibility to check the error logs. Also, replaced u32/u64 with uint32_t/uint64_t in the functions touched by the code changes. Signed-off-by: Ayan Kumar Halder --- Changes from v1 - 1. Dropped "[XEN v1 2/9] xen/arm: Define translate_dt_address_size() for the translation between u64 and paddr_t" and "[XEN v1 4/9] xen/arm: Use translate_dt_address_size() to translate between device tree addr/size and paddr_t", instead this approach achieves the same purpose. 2. No need to check for truncation while converting values from u64 to paddr_t. v2 - 1. Use "( (dt_start >> (PADDR_SHIFT - 1)) > 1 )" to detect truncation. 2. Introduced libfdt_xen.h to implement fdt_get_mem_rsv_paddr 3. Logged error messages in case truncation is detected. v3 - 1. Renamed libfdt_xen.h to libfdt-xen.h. 2. Replaced u32/u64 with uint32_t/uint64_t 3. Use "(paddr_t)val != val" to check for truncation. 4. Removed the alias "#define PADDR_SHIFT PADDR_BITS". xen/arch/arm/bootfdt.c | 41 ++++++++++++++++++----- xen/arch/arm/domain_build.c | 2 +- xen/arch/arm/include/asm/setup.h | 4 +-- xen/arch/arm/setup.c | 14 ++++---- xen/arch/arm/smpboot.c | 2 +- xen/include/xen/device_tree.h | 21 ++++++++++++ xen/include/xen/libfdt/libfdt-xen.h | 52 +++++++++++++++++++++++++++++ 7 files changed, 116 insertions(+), 20 deletions(-) create mode 100644 xen/include/xen/libfdt/libfdt-xen.h diff --git a/xen/arch/arm/bootfdt.c b/xen/arch/arm/bootfdt.c index 0085c28d74..33bef1c15e 100644 --- a/xen/arch/arm/bootfdt.c +++ b/xen/arch/arm/bootfdt.c @@ -11,7 +11,7 @@ #include #include #include -#include +#include #include #include #include @@ -52,11 +52,32 @@ static bool __init device_tree_node_compatible(const void *fdt, int node, return false; } -void __init device_tree_get_reg(const __be32 **cell, u32 address_cells, - u32 size_cells, u64 *start, u64 *size) +void __init device_tree_get_reg(const __be32 **cell, uint32_t address_cells, + uint32_t size_cells, paddr_t *start, + paddr_t *size) { - *start = dt_next_cell(address_cells, cell); - *size = dt_next_cell(size_cells, cell); + uint64_t dt_start, dt_size; + + /* + * dt_next_cell will return u64 whereas paddr_t may be u64 or u32. Thus, + * there is an implicit cast from u64 to paddr_t. + */ + dt_start = dt_next_cell(address_cells, cell); + dt_size = dt_next_cell(size_cells, cell); + + if ( dt_start != (paddr_t)dt_start ) + printk("Error: Physical address greater than max width supported\n"); + + if ( dt_size != (paddr_t)dt_size ) + printk("Error: Physical size greater than max width supported\n"); + + /* + * Note: It is user's responsibility to check for the error messages. + * Xen will sliently truncate in case if the address/size is greater than + * the max supported width. + */ + *start = dt_start; + *size = dt_size; } static int __init device_tree_get_meminfo(const void *fdt, int node, @@ -326,7 +347,7 @@ static int __init process_chosen_node(const void *fdt, int node, printk("linux,initrd-start property has invalid length %d\n", len); return -EINVAL; } - start = dt_read_number((void *)&prop->data, dt_size_to_cells(len)); + start = dt_read_paddr((void *)&prop->data, dt_size_to_cells(len)); prop = fdt_get_property(fdt, node, "linux,initrd-end", &len); if ( !prop ) @@ -339,7 +360,7 @@ static int __init process_chosen_node(const void *fdt, int node, printk("linux,initrd-end property has invalid length %d\n", len); return -EINVAL; } - end = dt_read_number((void *)&prop->data, dt_size_to_cells(len)); + end = dt_read_paddr((void *)&prop->data, dt_size_to_cells(len)); if ( start >= end ) { @@ -594,9 +615,11 @@ static void __init early_print_info(void) for ( i = 0; i < nr_rsvd; i++ ) { paddr_t s, e; - if ( fdt_get_mem_rsv(device_tree_flattened, i, &s, &e) < 0 ) + + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, i, &s, &e) < 0 ) continue; - /* fdt_get_mem_rsv returns length */ + + /* fdt_get_mem_rsv_paddr returns length */ e += s; printk(" RESVD[%u]: %"PRIpaddr" - %"PRIpaddr"\n", i, s, e); } diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 24b12b7512..6573d15302 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -949,7 +949,7 @@ static int __init process_shm(struct domain *d, struct kernel_info *kinfo, BUG_ON(!prop); cells = (const __be32 *)prop->value; device_tree_get_reg(&cells, addr_cells, addr_cells, &pbase, &gbase); - psize = dt_read_number(cells, size_cells); + psize = dt_read_paddr(cells, size_cells); if ( !IS_ALIGNED(pbase, PAGE_SIZE) || !IS_ALIGNED(gbase, PAGE_SIZE) ) { printk("%pd: physical address 0x%"PRIpaddr", or guest address 0x%"PRIpaddr" is not suitably aligned.\n", diff --git a/xen/arch/arm/include/asm/setup.h b/xen/arch/arm/include/asm/setup.h index a926f30a2b..7b697d879e 100644 --- a/xen/arch/arm/include/asm/setup.h +++ b/xen/arch/arm/include/asm/setup.h @@ -157,8 +157,8 @@ const char *boot_module_kind_as_string(bootmodule_kind kind); extern uint32_t hyp_traps_vector[]; void init_traps(void); -void device_tree_get_reg(const __be32 **cell, u32 address_cells, - u32 size_cells, u64 *start, u64 *size); +void device_tree_get_reg(const __be32 **cell, uint32_t address_cells, + uint32_t size_cells, paddr_t *start, paddr_t *size); u32 device_tree_get_u32(const void *fdt, int node, const char *prop_name, u32 dflt); diff --git a/xen/arch/arm/setup.c b/xen/arch/arm/setup.c index 1f26f67b90..755173e5a3 100644 --- a/xen/arch/arm/setup.c +++ b/xen/arch/arm/setup.c @@ -29,7 +29,7 @@ #include #include #include -#include +#include #include #include #include @@ -222,11 +222,11 @@ static void __init dt_unreserved_regions(paddr_t s, paddr_t e, { paddr_t r_s, r_e; - if ( fdt_get_mem_rsv(device_tree_flattened, i, &r_s, &r_e ) < 0 ) + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, i, &r_s, &r_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; - r_e += r_s; /* fdt_get_mem_rsv returns length */ + r_e += r_s; /* fdt_get_mem_rsv_paddr returns length */ if ( s < r_e && r_s < e ) { @@ -502,13 +502,13 @@ static paddr_t __init consider_modules(paddr_t s, paddr_t e, { paddr_t mod_s, mod_e; - if ( fdt_get_mem_rsv(device_tree_flattened, - i - mi->nr_mods, - &mod_s, &mod_e ) < 0 ) + if ( fdt_get_mem_rsv_paddr(device_tree_flattened, + i - mi->nr_mods, + &mod_s, &mod_e ) < 0 ) /* If we can't read it, pretend it doesn't exist... */ continue; - /* fdt_get_mem_rsv returns length */ + /* fdt_get_mem_rsv_paddr returns length */ mod_e += mod_s; if ( s < mod_e && mod_s < e ) diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index 412ae22869..c15c177487 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -159,7 +159,7 @@ static void __init dt_smp_init_cpus(void) continue; } - addr = dt_read_number(prop, dt_n_addr_cells(cpu)); + addr = dt_read_paddr(prop, dt_n_addr_cells(cpu)); hwid = addr; if ( hwid != addr ) diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index 19a74909ce..bbc7d7377a 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -241,6 +241,27 @@ static inline u64 dt_read_number(const __be32 *cell, int size) return r; } +/* Wrapper for dt_read_number() to return paddr_t (instead of u64) */ +static inline paddr_t dt_read_paddr(const __be32 *cell, int size) +{ + uint64_t dt_r = 0; + paddr_t r; + + dt_r = dt_read_number(cell, size); + + if ( dt_r != (paddr_t)dt_r ) + printk("Error: Physical address greater than max width supported\n"); + + /* + * Note: It is user's responsibility to check for the error messages. + * Xen will sliently truncate in case if the address/size is greater than + * the max supported width. + */ + r = dt_r; + + return r; +} + /* Helper to convert a number of cells to bytes */ static inline int dt_cells_to_size(int size) { diff --git a/xen/include/xen/libfdt/libfdt-xen.h b/xen/include/xen/libfdt/libfdt-xen.h new file mode 100644 index 0000000000..648bf41be6 --- /dev/null +++ b/xen/include/xen/libfdt/libfdt-xen.h @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * xen/include/xen/libfdt/libfdt-xen.h + * + * Wrapper functions for device tree. This helps to convert dt values + * between u64 and paddr_t. + * + * Copyright (C) 2023, Advanced Micro Devices, Inc. All Rights Reserved. + */ + +#ifndef LIBFDT_XEN_H +#define LIBFDT_XEN_H + +#include + +inline int fdt_get_mem_rsv_paddr(const void *fdt, int n, + paddr_t *address, + paddr_t *size) +{ + uint64_t dt_addr; + uint64_t dt_size; + int ret = 0; + + ret = fdt_get_mem_rsv(fdt, n, &dt_addr, &dt_size); + + if ( dt_addr != (paddr_t)dt_addr ) + { + printk("Error: Physical address greater than max width supported\n"); + return -1; + } + + if ( dt_size != (paddr_t)dt_size ) + { + printk("Error: Physical size greater than max width supported\n"); + return -1; + } + + *address = dt_addr; + *size = dt_size; + + return ret; +} + +#endif /* LIBFDT_XEN_H */ +/* + * Local variables: + * mode: C + * c-file-style: "BSD" + * c-basic-offset: 4 + * indent-tabs-mode: nil + * End: + */ From patchwork Tue Mar 21 14:03:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13182812 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AD9D8C74A5B for ; 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bh=wdACvSYIwIHbjiq6l1EcIfjcW/2ojwnGS2SvBnGV5RE=; b=k4xPp/rRgWWRo4gg1BIqmoYxP8R9q2JENzfgvuLIATwbtMDR7bTWst6cAeDk+iozTtZxuleDJeUiCMMvblA+nFBwze9MNuAOcj4Wh9jVmqc2JTyOYkYD3CkYX6U3EqPQQPJiirexY7rkIBMz155MoLfvoKJ+HRPMhrKpZqQA1BE= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 04/11] xen/drivers: ns16550: Use paddr_t for io_base/io_size Date: Tue, 21 Mar 2023 14:03:50 +0000 Message-ID: <20230321140357.24094-5-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B079:EE_|DM4PR12MB6109:EE_ X-MS-Office365-Filtering-Correlation-Id: 949069a3-f7ed-4abb-0902-08db2a153f3b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:04:54.5789 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 949069a3-f7ed-4abb-0902-08db2a153f3b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B079.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6109 io_base and io_size represent physical addresses. So they should use paddr_t (instead of u64). However in future, paddr_t may be defined as u32. So when typecasting values from u64 to paddr_t, one should always check for any possible truncation. If any truncation is discovered, Xen needs to return an appropriate an error message for this. Also moved the definition of PARSE_ERR_RET before its first usage. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - NA v2 - 1. Extracted the patch from "[XEN v2 05/11] xen/arm: Use paddr_t instead of u64 for address/size" into a separate patch of its own. v3 - 1. Reduced the scope of pci_uart_io_base and uart_io_base definitions. 2. Instead of crashing, invoke PARSE_ERR_RET(). 3. Moved PARSE_ERR_RET() so that it is defined before its first use. xen/drivers/char/ns16550.c | 41 ++++++++++++++++++++++++++------------ 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 092f6b9c4b..2e8a9cfb24 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -42,8 +42,8 @@ static struct ns16550 { int baud, clock_hz, data_bits, parity, stop_bits, fifo_size, irq; - u64 io_base; /* I/O port or memory-mapped I/O address. */ - u64 io_size; + paddr_t io_base; /* I/O port or memory-mapped I/O address. */ + paddr_t io_size; int reg_shift; /* Bits to shift register offset by */ int reg_width; /* Size of access to use, the registers * themselves are still bytes */ @@ -1163,10 +1163,16 @@ static const struct ns16550_config __initconst uart_config[] = }, }; +#define PARSE_ERR_RET(_f, _a...) \ + do { \ + printk( "ERROR: " _f "\n" , ## _a ); \ + return false; \ + } while ( 0 ) + static int __init pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) { - u64 orig_base = uart->io_base; + paddr_t orig_base = uart->io_base; unsigned int b, d, f, nextf, i; /* NB. Start at bus 1 to avoid AMT: a plug-in card cannot be on bus 0. */ @@ -1235,6 +1241,8 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) /* MMIO based */ if ( param->mmio && !(bar & PCI_BASE_ADDRESS_SPACE_IO) ) { + uint64_t pci_uart_io_base; + pci_conf_write32(PCI_SBDF(0, b, d, f), PCI_BASE_ADDRESS_0 + bar_idx*4, ~0u); len = pci_conf_read32(PCI_SBDF(0, b, d, f), @@ -1259,8 +1267,14 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx) else size = len & PCI_BASE_ADDRESS_MEM_MASK; - uart->io_base = ((u64)bar_64 << 32) | - (bar & PCI_BASE_ADDRESS_MEM_MASK); + pci_uart_io_base = ((u64)bar_64 << 32) | + (bar & PCI_BASE_ADDRESS_MEM_MASK); + + /* Truncation detected while converting to paddr_t */ + if ( (pci_uart_io_base >> (PADDR_BITS - 1)) > 1 ) + PARSE_ERR_RET("Truncation detected for io_base address"); + + uart->io_base = pci_uart_io_base; } /* IO based */ else if ( !param->mmio && (bar & PCI_BASE_ADDRESS_SPACE_IO) ) @@ -1456,13 +1470,6 @@ static enum __init serial_param_type get_token(char *token, char **value) return; \ } while ( 0 ) -#define PARSE_ERR_RET(_f, _a...) \ - do { \ - printk( "ERROR: " _f "\n" , ## _a ); \ - return false; \ - } while ( 0 ) - - static bool __init parse_positional(struct ns16550 *uart, char **str) { int baud; @@ -1532,7 +1539,15 @@ static bool __init parse_positional(struct ns16550 *uart, char **str) else #endif { - uart->io_base = simple_strtoull(conf, &conf, 0); + uint64_t uart_io_base; + + uart_io_base = simple_strtoull(conf, &conf, 0); + + /* Truncation detected while converting to paddr_t */ + if ( (uart_io_base >> (PADDR_BITS - 1)) > 1 ) + PARSE_ERR_RET("Truncation detected for uart_io_base address"); + + uart->io_base = uart_io_base; } } From patchwork Tue Mar 21 14:03:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13182816 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0863CC7619A for ; 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bh=P4RP/khVYxFpfabYrxxnK0TXYG+4GHlNXLJPkm8V9rs=; b=er98oIPrUwDBQnj13JChgRWz5fb4TZlfwVeCYFTZj2paxon9V6QbBsXn1dEv6LfvXntzXGog4HRKjIKVMb5o9x0XwRUjUgUNhRnWdxrac3T8U3wfUWYlZ7RFcY9bLdKbyky2a+TQDwTBmHlQlhGOohNdYnB78gopoglKxvE3ZI4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 05/11] xen/arm: Introduce a wrapper for dt_device_get_address() to handle paddr_t Date: Tue, 21 Mar 2023 14:03:51 +0000 Message-ID: <20230321140357.24094-6-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E651:EE_|BL3PR12MB6450:EE_ X-MS-Office365-Filtering-Correlation-Id: c502188b-93bd-4bc2-f470-08db2a154d93 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:18.6497 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c502188b-93bd-4bc2-f470-08db2a154d93 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E651.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6450 dt_device_get_address() can accept uint64_t only for address and size. However, the address/size denotes physical addresses. Thus, they should be represented by 'paddr_t'. Consequently, we introduce a wrapper for dt_device_get_address() ie dt_device_get_paddr() which accepts address/size as paddr_t and inturn invokes dt_device_get_address() after converting address/size to uint64_t. The reason for introducing doing this is that in future 'paddr_t' may be defined as uint32_t. Thus, we need an explicit wrapper to do the type conversion and return an error in case of truncation. With this, callers now invoke dt_device_get_paddr(). dt_device_get_address() is invoked by dt_device_get_paddr() only. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. New patch. v2 - 1. Extracted part of "[XEN v2 05/11] xen/arm: Use paddr_t instead of u64 for address/size" into this patch. 2. dt_device_get_address() callers now invoke dt_device_get_paddr() instead. 3. Logged error in case of truncation. v3 - 1. Modified the truncation checks as "dt_addr != (paddr_t)dt_addr". 2. Some sanity fixes. xen/arch/arm/domain_build.c | 10 +++--- xen/arch/arm/gic-v2.c | 10 +++--- xen/arch/arm/gic-v3-its.c | 4 +-- xen/arch/arm/gic-v3.c | 10 +++--- xen/arch/arm/pci/pci-host-common.c | 6 ++-- xen/arch/arm/platforms/brcm-raspberry-pi.c | 2 +- xen/arch/arm/platforms/brcm.c | 4 +-- xen/arch/arm/platforms/exynos5.c | 32 ++++++++--------- xen/arch/arm/platforms/sunxi.c | 2 +- xen/arch/arm/platforms/xgene-storm.c | 2 +- xen/common/device_tree.c | 40 ++++++++++++++++++++-- xen/drivers/char/cadence-uart.c | 4 +-- xen/drivers/char/exynos4210-uart.c | 4 +-- xen/drivers/char/imx-lpuart.c | 4 +-- xen/drivers/char/meson-uart.c | 4 +-- xen/drivers/char/mvebu-uart.c | 4 +-- xen/drivers/char/ns16550.c | 2 +- xen/drivers/char/omap-uart.c | 4 +-- xen/drivers/char/pl011.c | 6 ++-- xen/drivers/char/scif-uart.c | 4 +-- xen/drivers/passthrough/arm/ipmmu-vmsa.c | 8 ++--- xen/drivers/passthrough/arm/smmu-v3.c | 2 +- xen/drivers/passthrough/arm/smmu.c | 8 ++--- xen/include/xen/device_tree.h | 6 ++-- 24 files changed, 109 insertions(+), 73 deletions(-) diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c index 6573d15302..b4ae6a2548 100644 --- a/xen/arch/arm/domain_build.c +++ b/xen/arch/arm/domain_build.c @@ -1698,13 +1698,13 @@ static int __init find_memory_holes(const struct kernel_info *kinfo, dt_for_each_device_node( dt_host, np ) { unsigned int naddr; - u64 addr, size; + paddr_t addr, size; naddr = dt_number_of_address(np); for ( i = 0; i < naddr; i++ ) { - res = dt_device_get_address(np, i, &addr, &size); + res = dt_device_get_paddr(np, i, &addr, &size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -2478,7 +2478,7 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, unsigned int naddr; unsigned int i; int res; - u64 addr, size; + paddr_t addr, size; bool own_device = !dt_device_for_passthrough(dev); /* * We want to avoid mapping the MMIO in dom0 for the following cases: @@ -2533,7 +2533,7 @@ static int __init handle_device(struct domain *d, struct dt_device_node *dev, /* Give permission and map MMIOs */ for ( i = 0; i < naddr; i++ ) { - res = dt_device_get_address(dev, i, &addr, &size); + res = dt_device_get_paddr(dev, i, &addr, &size); if ( res ) { printk(XENLOG_ERR "Unable to retrieve address %u for %s\n", @@ -2964,7 +2964,7 @@ static int __init handle_passthrough_prop(struct kernel_info *kinfo, if ( res ) { printk(XENLOG_ERR "Unable to permit to dom%d access to" - " 0x%"PRIx64" - 0x%"PRIx64"\n", + " 0x%"PRIpaddr" - 0x%"PRIpaddr"\n", kinfo->d->domain_id, mstart & PAGE_MASK, PAGE_ALIGN(mstart + size) - 1); return res; diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 5d4d298b86..6476ff4230 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -993,7 +993,7 @@ static void gicv2_extension_dt_init(const struct dt_device_node *node) continue; /* Get register frame resource from DT. */ - if ( dt_device_get_address(v2m, 0, &addr, &size) ) + if ( dt_device_get_paddr(v2m, 0, &addr, &size) ) panic("GICv2: Cannot find a valid v2m frame address\n"); /* @@ -1018,19 +1018,19 @@ static void __init gicv2_dt_init(void) paddr_t vsize; const struct dt_device_node *node = gicv2_info.node; - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the distributor\n"); - res = dt_device_get_address(node, 1, &cbase, &csize); + res = dt_device_get_paddr(node, 1, &cbase, &csize); if ( res ) panic("GICv2: Cannot find a valid address for the CPU\n"); - res = dt_device_get_address(node, 2, &hbase, NULL); + res = dt_device_get_paddr(node, 2, &hbase, NULL); if ( res ) panic("GICv2: Cannot find a valid address for the hypervisor\n"); - res = dt_device_get_address(node, 3, &vbase, &vsize); + res = dt_device_get_paddr(node, 3, &vbase, &vsize); if ( res ) panic("GICv2: Cannot find a valid address for the virtual CPU\n"); diff --git a/xen/arch/arm/gic-v3-its.c b/xen/arch/arm/gic-v3-its.c index 1ec9934191..3aa4edda10 100644 --- a/xen/arch/arm/gic-v3-its.c +++ b/xen/arch/arm/gic-v3-its.c @@ -1004,12 +1004,12 @@ static void gicv3_its_dt_init(const struct dt_device_node *node) */ dt_for_each_child_node(node, its) { - uint64_t addr, size; + paddr_t addr, size; if ( !dt_device_is_compatible(its, "arm,gic-v3-its") ) continue; - if ( dt_device_get_address(its, 0, &addr, &size) ) + if ( dt_device_get_paddr(its, 0, &addr, &size) ) panic("GICv3: Cannot find a valid ITS frame address\n"); add_to_host_its_list(addr, size, its); diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index bb59ea94cd..4e6c98bada 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -1377,7 +1377,7 @@ static void __init gicv3_dt_init(void) int res, i; const struct dt_device_node *node = gicv3_info.node; - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("GICv3: Cannot find a valid distributor address\n"); @@ -1393,9 +1393,9 @@ static void __init gicv3_dt_init(void) for ( i = 0; i < gicv3.rdist_count; i++ ) { - uint64_t rdist_base, rdist_size; + paddr_t rdist_base, rdist_size; - res = dt_device_get_address(node, 1 + i, &rdist_base, &rdist_size); + res = dt_device_get_paddr(node, 1 + i, &rdist_base, &rdist_size); if ( res ) panic("GICv3: No rdist base found for region %d\n", i); @@ -1417,10 +1417,10 @@ static void __init gicv3_dt_init(void) * For GICv3 supporting GICv2, GICC and GICV base address will be * provided. */ - res = dt_device_get_address(node, 1 + gicv3.rdist_count, + res = dt_device_get_paddr(node, 1 + gicv3.rdist_count, &cbase, &csize); if ( !res ) - dt_device_get_address(node, 1 + gicv3.rdist_count + 2, + dt_device_get_paddr(node, 1 + gicv3.rdist_count + 2, &vbase, &vsize); } diff --git a/xen/arch/arm/pci/pci-host-common.c b/xen/arch/arm/pci/pci-host-common.c index a8ece94303..5550f9478d 100644 --- a/xen/arch/arm/pci/pci-host-common.c +++ b/xen/arch/arm/pci/pci-host-common.c @@ -93,7 +93,7 @@ gen_pci_init(struct dt_device_node *dev, const struct pci_ecam_ops *ops) cfg_reg_idx = 0; /* Parse our PCI ecam register address */ - err = dt_device_get_address(dev, cfg_reg_idx, &addr, &size); + err = dt_device_get_paddr(dev, cfg_reg_idx, &addr, &size); if ( err ) goto err_exit; @@ -349,10 +349,10 @@ int __init pci_host_bridge_mappings(struct domain *d) for ( i = 0; i < dt_number_of_address(dev); i++ ) { - uint64_t addr, size; + paddr_t addr, size; int err; - err = dt_device_get_address(dev, i, &addr, &size); + err = dt_device_get_paddr(dev, i, &addr, &size); if ( err ) { printk(XENLOG_ERR diff --git a/xen/arch/arm/platforms/brcm-raspberry-pi.c b/xen/arch/arm/platforms/brcm-raspberry-pi.c index 811b40b1a6..407ec07f63 100644 --- a/xen/arch/arm/platforms/brcm-raspberry-pi.c +++ b/xen/arch/arm/platforms/brcm-raspberry-pi.c @@ -64,7 +64,7 @@ static void __iomem *rpi4_map_watchdog(void) if ( !node ) return NULL; - ret = dt_device_get_address(node, 0, &start, &len); + ret = dt_device_get_paddr(node, 0, &start, &len); if ( ret ) { printk("Cannot read watchdog register address\n"); diff --git a/xen/arch/arm/platforms/brcm.c b/xen/arch/arm/platforms/brcm.c index d481b2c60f..4310feee73 100644 --- a/xen/arch/arm/platforms/brcm.c +++ b/xen/arch/arm/platforms/brcm.c @@ -40,7 +40,7 @@ static __init int brcm_get_dt_node(char *compat_str, u32 *reg_base) { const struct dt_device_node *node; - u64 reg_base_64; + paddr_t reg_base_64; int rc; node = dt_find_compatible_node(NULL, NULL, compat_str); @@ -50,7 +50,7 @@ static __init int brcm_get_dt_node(char *compat_str, return -ENOENT; } - rc = dt_device_get_address(node, 0, ®_base_64, NULL); + rc = dt_device_get_paddr(node, 0, ®_base_64, NULL); if ( rc ) { dprintk(XENLOG_ERR, "%s: missing \"reg\" prop\n", __func__); diff --git a/xen/arch/arm/platforms/exynos5.c b/xen/arch/arm/platforms/exynos5.c index 6560507092..c48093cd4f 100644 --- a/xen/arch/arm/platforms/exynos5.c +++ b/xen/arch/arm/platforms/exynos5.c @@ -42,8 +42,8 @@ static int exynos5_init_time(void) void __iomem *mct; int rc; struct dt_device_node *node; - u64 mct_base_addr; - u64 size; + paddr_t mct_base_addr; + paddr_t size; node = dt_find_compatible_node(NULL, NULL, "samsung,exynos4210-mct"); if ( !node ) @@ -52,14 +52,14 @@ static int exynos5_init_time(void) return -ENXIO; } - rc = dt_device_get_address(node, 0, &mct_base_addr, &size); + rc = dt_device_get_paddr(node, 0, &mct_base_addr, &size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos4210-mct\"\n"); return -ENXIO; } - dprintk(XENLOG_INFO, "mct_base_addr: %016llx size: %016llx\n", + dprintk(XENLOG_INFO, "mct_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"\n", mct_base_addr, size); mct = ioremap_nocache(mct_base_addr, size); @@ -97,9 +97,9 @@ static int __init exynos5_smp_init(void) struct dt_device_node *node; void __iomem *sysram; char *compatible; - u64 sysram_addr; - u64 size; - u64 sysram_offset; + paddr_t sysram_addr; + paddr_t size; + paddr_t sysram_offset; int rc; node = dt_find_compatible_node(NULL, NULL, "samsung,secure-firmware"); @@ -125,13 +125,13 @@ static int __init exynos5_smp_init(void) return -ENXIO; } - rc = dt_device_get_address(node, 0, &sysram_addr, &size); + rc = dt_device_get_paddr(node, 0, &sysram_addr, &size); if ( rc ) { dprintk(XENLOG_ERR, "Error in %s\n", compatible); return -ENXIO; } - dprintk(XENLOG_INFO, "sysram_addr: %016llx size: %016llx offset: %016llx\n", + dprintk(XENLOG_INFO,"sysram_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"offset: 0x%"PRIpaddr"\n", sysram_addr, size, sysram_offset); sysram = ioremap_nocache(sysram_addr, size); @@ -189,7 +189,7 @@ static int exynos5_cpu_power_up(void __iomem *power, int cpu) return 0; } -static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) +static int exynos5_get_pmu_baseandsize(paddr_t *power_base_addr, paddr_t *size) { struct dt_device_node *node; int rc; @@ -208,14 +208,14 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) return -ENXIO; } - rc = dt_device_get_address(node, 0, power_base_addr, size); + rc = dt_device_get_paddr(node, 0, power_base_addr, size); if ( rc ) { dprintk(XENLOG_ERR, "Error in \"samsung,exynos5XXX-pmu\"\n"); return -ENXIO; } - dprintk(XENLOG_DEBUG, "power_base_addr: %016llx size: %016llx\n", + dprintk(XENLOG_DEBUG, "power_base_addr: 0x%"PRIpaddr" size: 0x%"PRIpaddr"\n", *power_base_addr, *size); return 0; @@ -223,8 +223,8 @@ static int exynos5_get_pmu_baseandsize(u64 *power_base_addr, u64 *size) static int exynos5_cpu_up(int cpu) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *power; int rc; @@ -256,8 +256,8 @@ static int exynos5_cpu_up(int cpu) static void exynos5_reset(void) { - u64 power_base_addr; - u64 size; + paddr_t power_base_addr; + paddr_t size; void __iomem *pmu; int rc; diff --git a/xen/arch/arm/platforms/sunxi.c b/xen/arch/arm/platforms/sunxi.c index e8e4d88bef..2b2c215f20 100644 --- a/xen/arch/arm/platforms/sunxi.c +++ b/xen/arch/arm/platforms/sunxi.c @@ -50,7 +50,7 @@ static void __iomem *sunxi_map_watchdog(bool *new_wdt) return NULL; } - ret = dt_device_get_address(node, 0, &wdt_start, &wdt_len); + ret = dt_device_get_paddr(node, 0, &wdt_start, &wdt_len); if ( ret ) { dprintk(XENLOG_ERR, "Cannot read watchdog register address\n"); diff --git a/xen/arch/arm/platforms/xgene-storm.c b/xen/arch/arm/platforms/xgene-storm.c index befd0c3c2d..6fc2f9679e 100644 --- a/xen/arch/arm/platforms/xgene-storm.c +++ b/xen/arch/arm/platforms/xgene-storm.c @@ -50,7 +50,7 @@ static void __init xgene_check_pirq_eoi(void) if ( !node ) panic("%s: Can not find interrupt controller node\n", __func__); - res = dt_device_get_address(node, 0, &dbase, NULL); + res = dt_device_get_paddr(node, 0, &dbase, NULL); if ( res ) panic("%s: Cannot find a valid address for the distributor\n", __func__); diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c index 6c9712ab7b..0d2922ad85 100644 --- a/xen/common/device_tree.c +++ b/xen/common/device_tree.c @@ -934,8 +934,9 @@ bail: } /* dt_device_address - Translate device tree address and return it */ -int dt_device_get_address(const struct dt_device_node *dev, unsigned int index, - u64 *addr, u64 *size) +static int dt_device_get_address(const struct dt_device_node *dev, + unsigned int index, + u64 *addr, u64 *size) { const __be32 *addrp; unsigned int flags; @@ -955,6 +956,41 @@ int dt_device_get_address(const struct dt_device_node *dev, unsigned int index, return 0; } +int dt_device_get_paddr(const struct dt_device_node *dev, unsigned int index, + paddr_t *addr, paddr_t *size) +{ + uint64_t dt_addr = 0, dt_size = 0; + int ret; + + ret = dt_device_get_address(dev, index, &dt_addr, &dt_size); + if ( ret ) + return ret; + + if ( addr ) + { + if ( dt_addr != (paddr_t)dt_addr ) + { + printk("Error: Physical address 0x%"PRIx64" for node=%s is greater than max width (%zu bytes) supported\n", + dt_addr, dev->name, sizeof(paddr_t)); + return -ERANGE; + } + + *addr = dt_addr; + } + + if ( size ) + { + if ( dt_size != (paddr_t)dt_size ) + { + printk("Error: Physical size 0x%"PRIx64" for node=%s is greater than max width (%zu bytes) supported\n", + dt_size, dev->name, sizeof(paddr_t)); + return -ERANGE; + } + *size = dt_size; + } + + return ret; +} int dt_for_each_range(const struct dt_device_node *dev, int (*cb)(const struct dt_device_node *, diff --git a/xen/drivers/char/cadence-uart.c b/xen/drivers/char/cadence-uart.c index 22905ba66c..c38d7ed143 100644 --- a/xen/drivers/char/cadence-uart.c +++ b/xen/drivers/char/cadence-uart.c @@ -158,14 +158,14 @@ static int __init cuart_init(struct dt_device_node *dev, const void *data) const char *config = data; struct cuart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &cuart_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("cadence: Unable to retrieve the base" diff --git a/xen/drivers/char/exynos4210-uart.c b/xen/drivers/char/exynos4210-uart.c index 43aaf02e18..2503392ccd 100644 --- a/xen/drivers/char/exynos4210-uart.c +++ b/xen/drivers/char/exynos4210-uart.c @@ -303,7 +303,7 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, const char *config = data; struct exynos4210_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -316,7 +316,7 @@ static int __init exynos4210_uart_init(struct dt_device_node *dev, uart->parity = PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("exynos4210: Unable to retrieve the base" diff --git a/xen/drivers/char/imx-lpuart.c b/xen/drivers/char/imx-lpuart.c index 9c1f3b71a3..77f70c2719 100644 --- a/xen/drivers/char/imx-lpuart.c +++ b/xen/drivers/char/imx-lpuart.c @@ -204,7 +204,7 @@ static int __init imx_lpuart_init(struct dt_device_node *dev, const char *config = data; struct imx_lpuart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -216,7 +216,7 @@ static int __init imx_lpuart_init(struct dt_device_node *dev, uart->parity = 0; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("imx8-lpuart: Unable to retrieve the base" diff --git a/xen/drivers/char/meson-uart.c b/xen/drivers/char/meson-uart.c index b1e25e0468..c627328122 100644 --- a/xen/drivers/char/meson-uart.c +++ b/xen/drivers/char/meson-uart.c @@ -209,14 +209,14 @@ static int __init meson_uart_init(struct dt_device_node *dev, const void *data) const char *config = data; struct meson_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &meson_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("meson: Unable to retrieve the base address of the UART\n"); diff --git a/xen/drivers/char/mvebu-uart.c b/xen/drivers/char/mvebu-uart.c index a00618b96f..cc55173513 100644 --- a/xen/drivers/char/mvebu-uart.c +++ b/xen/drivers/char/mvebu-uart.c @@ -231,14 +231,14 @@ static int __init mvebu_uart_init(struct dt_device_node *dev, const void *data) const char *config = data; struct mvebu3700_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &mvebu3700_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("mvebu3700: Unable to retrieve the base address of the UART\n"); diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c index 2e8a9cfb24..732c1e5c71 100644 --- a/xen/drivers/char/ns16550.c +++ b/xen/drivers/char/ns16550.c @@ -1772,7 +1772,7 @@ static int __init ns16550_uart_dt_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &uart->io_base, &uart->io_size); + res = dt_device_get_paddr(dev, 0, &uart->io_base, &uart->io_size); if ( res ) return res; diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c index d6a5d59aa2..8e643cb039 100644 --- a/xen/drivers/char/omap-uart.c +++ b/xen/drivers/char/omap-uart.c @@ -324,7 +324,7 @@ static int __init omap_uart_init(struct dt_device_node *dev, struct omap_uart *uart; u32 clkspec; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); @@ -344,7 +344,7 @@ static int __init omap_uart_init(struct dt_device_node *dev, uart->parity = UART_PARITY_NONE; uart->stop_bits = 1; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("omap-uart: Unable to retrieve the base" diff --git a/xen/drivers/char/pl011.c b/xen/drivers/char/pl011.c index be67242bc0..052a651251 100644 --- a/xen/drivers/char/pl011.c +++ b/xen/drivers/char/pl011.c @@ -222,7 +222,7 @@ static struct uart_driver __read_mostly pl011_driver = { .vuart_info = pl011_vuart, }; -static int __init pl011_uart_init(int irq, u64 addr, u64 size, bool sbsa) +static int __init pl011_uart_init(int irq, paddr_t addr, paddr_t size, bool sbsa) { struct pl011 *uart; @@ -258,14 +258,14 @@ static int __init pl011_dt_uart_init(struct dt_device_node *dev, { const char *config = data; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) { printk("WARNING: UART configuration is not supported\n"); } - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("pl011: Unable to retrieve the base" diff --git a/xen/drivers/char/scif-uart.c b/xen/drivers/char/scif-uart.c index 2fccafe340..1b28ba90e9 100644 --- a/xen/drivers/char/scif-uart.c +++ b/xen/drivers/char/scif-uart.c @@ -311,14 +311,14 @@ static int __init scif_uart_init(struct dt_device_node *dev, const char *config = data; struct scif_uart *uart; int res; - u64 addr, size; + paddr_t addr, size; if ( strcmp(config, "") ) printk("WARNING: UART configuration is not supported\n"); uart = &scif_com; - res = dt_device_get_address(dev, 0, &addr, &size); + res = dt_device_get_paddr(dev, 0, &addr, &size); if ( res ) { printk("scif-uart: Unable to retrieve the base" diff --git a/xen/drivers/passthrough/arm/ipmmu-vmsa.c b/xen/drivers/passthrough/arm/ipmmu-vmsa.c index 091f09b217..611d9eeba5 100644 --- a/xen/drivers/passthrough/arm/ipmmu-vmsa.c +++ b/xen/drivers/passthrough/arm/ipmmu-vmsa.c @@ -794,7 +794,7 @@ static void ipmmu_device_reset(struct ipmmu_vmsa_device *mmu) static __init bool ipmmu_stage2_supported(void) { struct dt_device_node *np; - uint64_t addr, size; + paddr_t addr, size; void __iomem *base; uint32_t product, cut; bool stage2_supported = false; @@ -806,7 +806,7 @@ static __init bool ipmmu_stage2_supported(void) return false; } - if ( dt_device_get_address(np, 0, &addr, &size) ) + if ( dt_device_get_paddr(np, 0, &addr, &size) ) { printk(XENLOG_ERR "ipmmu: Failed to get PRR MMIO\n"); return false; @@ -884,7 +884,7 @@ static int ipmmu_probe(struct dt_device_node *node) { const struct dt_device_match *match; struct ipmmu_vmsa_device *mmu; - uint64_t addr, size; + paddr_t addr, size; uint32_t reg; int irq, ret; @@ -905,7 +905,7 @@ static int ipmmu_probe(struct dt_device_node *node) bitmap_zero(mmu->ctx, IPMMU_CTX_MAX); /* Map I/O memory and request IRQ. */ - ret = dt_device_get_address(node, 0, &addr, &size); + ret = dt_device_get_paddr(node, 0, &addr, &size); if ( ret ) { dev_err(&node->dev, "Failed to get MMIO\n"); diff --git a/xen/drivers/passthrough/arm/smmu-v3.c b/xen/drivers/passthrough/arm/smmu-v3.c index bfdb62b395..b7fa2e90f7 100644 --- a/xen/drivers/passthrough/arm/smmu-v3.c +++ b/xen/drivers/passthrough/arm/smmu-v3.c @@ -2428,7 +2428,7 @@ static int arm_smmu_device_probe(struct platform_device *pdev) } /* Base address */ - ret = dt_device_get_address(np, 0, &ioaddr, &iosize); + ret = dt_device_get_paddr(np, 0, &ioaddr, &iosize); if (ret) goto out_free_smmu; diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 0a514821b3..79281075ba 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -73,8 +73,8 @@ /* Xen: Helpers to get device MMIO and IRQs */ struct resource { - u64 addr; - u64 size; + paddr_t addr; + paddr_t size; unsigned int type; }; @@ -101,7 +101,7 @@ static struct resource *platform_get_resource(struct platform_device *pdev, switch (type) { case IORESOURCE_MEM: - ret = dt_device_get_address(pdev, num, &res.addr, &res.size); + ret = dt_device_get_paddr(pdev, num, &res.addr, &res.size); return ((ret) ? NULL : &res); @@ -169,7 +169,7 @@ static void __iomem *devm_ioremap_resource(struct device *dev, ptr = ioremap_nocache(res->addr, res->size); if (!ptr) { dev_err(dev, - "ioremap failed (addr 0x%"PRIx64" size 0x%"PRIx64")\n", + "ioremap failed (addr 0x%"PRIpaddr" size 0x%"PRIpaddr")\n", res->addr, res->size); return ERR_PTR(-ENOMEM); } diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h index bbc7d7377a..d72dc7c788 100644 --- a/xen/include/xen/device_tree.h +++ b/xen/include/xen/device_tree.h @@ -580,7 +580,7 @@ int dt_find_node_by_gpath(XEN_GUEST_HANDLE(char) u_path, uint32_t u_plen, const struct dt_device_node *dt_get_parent(const struct dt_device_node *node); /** - * dt_device_get_address - Resolve an address for a device + * dt_device_get_paddr - Resolve an address for a device * @device: the device whose address is to be resolved * @index: index of the address to resolve * @addr: address filled by this function @@ -589,8 +589,8 @@ const struct dt_device_node *dt_get_parent(const struct dt_device_node *node); * This function resolves an address, walking the tree, for a give * device-tree node. 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bh=MyaKuKEF+X/1Kr4Tl9QPLAvUvFva7QxbH99CVqus0xY=; b=ReoJnGhJpRrTwTUGAOIN2plpdNSMUgqBLHz/wclSUQ7nybq9povoBYQOTWk7Y5QWOa6X0eamfVlkHrfpJZQD1S6Gr+ukc6PayDsyKf/xjLYhH3bScywAEF/fz74NE/uHEQu8WC/IbQmQFyOSH0lf6cKoBkR7cp1BhRa7wzIUVgw= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 06/11] xen/arm: smmu: Use writeq_relaxed_non_atomic() for writing to SMMU_CBn_TTBR0 Date: Tue, 21 Mar 2023 14:03:52 +0000 Message-ID: <20230321140357.24094-7-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B079:EE_|DS0PR12MB6415:EE_ X-MS-Office365-Filtering-Correlation-Id: 8f74f5e1-0f78-44d8-bd2f-08db2a154fc7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: DkQet4KD9tM/vlmph+nkGnsmiH9mWPc4NxUcqsJbMNmkEd4ZT3jjs932in0GNf4f//xGdlqGYgoZmWC11y06m7EIL5agmypUJ7bn8k6GYE8oMVOj622nmH86jKZmM+B4Brod+Pu8ArS5+b9b+V4GA5eua+x1XwGB/7fNKCKHWMUYNkXkqUvdYA1cntAOsUTlIVO87E+VFZDK3a5D0y+ErAr6/g52gwwKpX0DNthaGYkeTDcYCT7d+IVY2sZPbFs0ll1CWXRL8crFMDVuDkVqTXZzCBNncChESLom+06w4zVuTe+/HEn/nT1bC8yNBZCUPgYsMhexPW8miDDMglMaeoI0YWPk5sFva4/kvtF8EmfErRysKl83d8O7TGDE8TxQtPND7++WXMsn5DMDRC+Opo091LpPaQ2CJsKVoHnmhTxAPL7MbzRbyiYCbiXOxTRwL/IHNp6UPs+QS+9ujzxo9YCLaf8woPuI2nkGu08cLMLzAd3KSxd5mdkA7kofYMK6JxfSb1XOLcuEPKeGSeaqB23HkI/3CLAaxH/QqKQZCVvwfQyg4MXNhYu9L2WJpCyAvw0JAKza7ZZdhApeN8PAIzyAiG1StWhxQsK74UWvD4ogSOr5259LQ5iWT0ACssSJFFavoZj5q8I9nUEd1UjiKNN26BU85MC15V796o8LQN7ad6Hw3E+sojFnPuv1UiMg8Gopd4Nz1gihg1ctqqgylnZ3mX14srpfJYr8nwUsbpo= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB03.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(136003)(39860400002)(376002)(346002)(396003)(451199018)(46966006)(36840700001)(40470700004)(41300700001)(7416002)(8936002)(5660300002)(4326008)(36860700001)(40480700001)(82310400005)(356005)(103116003)(86362001)(36756003)(40460700003)(81166007)(82740400003)(2906002)(6666004)(336012)(83380400001)(426003)(47076005)(478600001)(2616005)(26005)(186003)(1076003)(54906003)(316002)(70586007)(6916009)(70206006)(8676002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:22.3289 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8f74f5e1-0f78-44d8-bd2f-08db2a154fc7 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B079.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB6415 Refer ARM IHI 0062D.c ID070116 (SMMU 2.0 spec), 17-360, 17.3.9, SMMU_CBn_TTBR0 is a 64 bit register. Thus, one can use writeq_relaxed_non_atomic() to write to it instead of invoking writel_relaxed() twice for lower half and upper half of the register. This also helps us as p2maddr is 'paddr_t' (which may be u32 in future). Thus, one can assign p2maddr to a 64 bit register and do the bit manipulations on it, to generate the value for SMMU_CBn_TTBR0. Reviewed-by: Stefano Stabellini Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Extracted the patch from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". Use writeq_relaxed_non_atomic() to write u64 register in a non-atomic fashion. v2 - 1. Added R-b. v3 - 1. No changes. xen/drivers/passthrough/arm/smmu.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/xen/drivers/passthrough/arm/smmu.c b/xen/drivers/passthrough/arm/smmu.c index 79281075ba..c8ef2a925f 100644 --- a/xen/drivers/passthrough/arm/smmu.c +++ b/xen/drivers/passthrough/arm/smmu.c @@ -499,8 +499,7 @@ enum arm_smmu_s2cr_privcfg { #define ARM_SMMU_CB_SCTLR 0x0 #define ARM_SMMU_CB_RESUME 0x8 #define ARM_SMMU_CB_TTBCR2 0x10 -#define ARM_SMMU_CB_TTBR0_LO 0x20 -#define ARM_SMMU_CB_TTBR0_HI 0x24 +#define ARM_SMMU_CB_TTBR0 0x20 #define ARM_SMMU_CB_TTBCR 0x30 #define ARM_SMMU_CB_S1_MAIR0 0x38 #define ARM_SMMU_CB_FSR 0x58 @@ -1083,6 +1082,7 @@ static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr, static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) { u32 reg; + u64 reg64; bool stage1; struct arm_smmu_cfg *cfg = &smmu_domain->cfg; struct arm_smmu_device *smmu = smmu_domain->smmu; @@ -1177,12 +1177,13 @@ static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain) dev_notice(smmu->dev, "d%u: p2maddr 0x%"PRIpaddr"\n", smmu_domain->cfg.domain->domain_id, p2maddr); - reg = (p2maddr & ((1ULL << 32) - 1)); - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO); - reg = (p2maddr >> 32); + reg64 = p2maddr; + if (stage1) - reg |= ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT; - writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI); + reg64 |= (((uint64_t) (ARM_SMMU_CB_ASID(cfg) << TTBRn_HI_ASID_SHIFT)) + << 32); + + writeq_relaxed_non_atomic(reg64, cb_base + ARM_SMMU_CB_TTBR0); /* * TTBCR From patchwork Tue Mar 21 14:03:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13182814 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BE8C0C74A5B for ; Tue, 21 Mar 2023 14:05:38 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.512683.792808 (Exim 4.92) (envelope-from ) id 1peccE-0007xD-V8; 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bh=YVw45C8rVy7+9H7135cJVOJglF13yYQFx7MyOjqge1Y=; b=zslQaGiXD+CDP4M8Oi7oAE821Zttq5lhxLGn42H05pZb2hUT+GlNoEH25AcDT+OeisUR6I4W3Lf5u4JoZD7SXWJC0YPzsXWgfDASwl0kdcTwkRHGEI9IAZd5hg8p+6UxpX6pdQPDCrinMd1oIp8k88csfpfztGW1iJ2T+gJMHl8= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 07/11] xen/arm: Introduce choice to enable 64/32 bit physical addressing Date: Tue, 21 Mar 2023 14:03:53 +0000 Message-ID: <20230321140357.24094-8-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000B07A:EE_|BL3PR12MB6380:EE_ X-MS-Office365-Filtering-Correlation-Id: cb5c4778-6cdd-495e-c86d-08db2a155175 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:25.1629 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cb5c4778-6cdd-495e-c86d-08db2a155175 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000B07A.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6380 Some Arm based hardware platforms which does not support LPAE (eg Cortex-R52), uses 32 bit physical addresses. Also, users may choose to use 32 bits to represent physical addresses for optimization. To support the above use cases, we have introduced arch independent configs to choose if the physical address can be represented using 32 bits (PHYS_ADDR_T_32) or 64 bits (PHYS_ADDR_T_64). For now only ARM_32 provides support to enable 32 bit physical addressing. When PHYS_ADDR_T_32 is defined, PADDR_BITS is set to 32. When PHYS_ADDR_T_64 is defined with ARM_32, PADDR_BITS is set to 40. When PHYS_ADDR_T_64 is defined with ARM_64, PADDR_BITS is set to 48. The last two are same as the current configuration used today on Xen. PADDR_BITS is also set to 48 when ARM_64 is defined. The reason being the choice to select ARM_PA_BITS_32/ARM_PA_BITS_40/ARM_PA_BITS_48 is currently allowed when ARM_32 is defined. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". v2 - 1. Introduced Kconfig choice. ARM_64 can select PHYS_ADDR_64 only whereas ARM_32 can select PHYS_ADDR_32 or PHYS_ADDR_64. 2. For CONFIG_ARM_PA_32, paddr_t is defined as 'unsigned long'. v3 - 1. Allow user to define PADDR_BITS by selecting different config options ARM_PA_BITS_32, ARM_PA_BITS_40 and ARM_PA_BITS_48. 2. Add the choice under "Architecture Features". xen/arch/Kconfig | 6 +++++ xen/arch/arm/Kconfig | 40 ++++++++++++++++++++++++++-- xen/arch/arm/include/asm/page-bits.h | 6 +---- xen/arch/arm/include/asm/types.h | 6 +++++ xen/arch/arm/mm.c | 1 + 5 files changed, 52 insertions(+), 7 deletions(-) diff --git a/xen/arch/Kconfig b/xen/arch/Kconfig index 7028f7b74f..89096c77a4 100644 --- a/xen/arch/Kconfig +++ b/xen/arch/Kconfig @@ -1,6 +1,12 @@ config 64BIT bool +config PHYS_ADDR_T_32 + bool + +config PHYS_ADDR_T_64 + bool + config NR_CPUS int "Maximum number of CPUs" range 1 4095 diff --git a/xen/arch/arm/Kconfig b/xen/arch/arm/Kconfig index 239d3aed3c..13e3a23911 100644 --- a/xen/arch/arm/Kconfig +++ b/xen/arch/arm/Kconfig @@ -9,6 +9,7 @@ config ARM_64 select 64BIT select ARM_EFI select HAS_FAST_MULTIPLY + select PHYS_ADDR_T_64 config ARM def_bool y @@ -19,13 +20,48 @@ config ARM select HAS_PMAP select IOMMU_FORCE_PT_SHARE +menu "Architecture Features" + +choice + prompt "Physical address space size" if ARM_32 + default ARM_PA_BITS_48 if ARM_64 + default ARM_PA_BITS_40 if ARM_32 + help + User can choose to represent the width of physical address. This can + sometimes help in optimizing the size of image when user chooses a + smaller size to represent physical address. + +config ARM_PA_BITS_32 + bool "32-bit" + help + On platforms where any physical address can be represented within 32 bits + , user should choose this option. This will help is reduced size of the + binary. + select PHYS_ADDR_T_32 + depends on ARM_32 + +config ARM_PA_BITS_40 + bool "40-bit" + select PHYS_ADDR_T_64 + depends on ARM_32 + +config ARM_PA_BITS_48 + bool "40-bit" + select PHYS_ADDR_T_64 + depends on ARM_48 +endchoice + +config PADDR_BITS + int + default 32 if ARM_PA_BITS_32 + default 40 if ARM_PA_BITS_40 + default 48 if ARM_PA_BITS_48 || ARM_64 + config ARCH_DEFCONFIG string default "arch/arm/configs/arm32_defconfig" if ARM_32 default "arch/arm/configs/arm64_defconfig" if ARM_64 -menu "Architecture Features" - source "arch/Kconfig" config ACPI diff --git a/xen/arch/arm/include/asm/page-bits.h b/xen/arch/arm/include/asm/page-bits.h index 5d6477e599..deb381ceeb 100644 --- a/xen/arch/arm/include/asm/page-bits.h +++ b/xen/arch/arm/include/asm/page-bits.h @@ -3,10 +3,6 @@ #define PAGE_SHIFT 12 -#ifdef CONFIG_ARM_64 -#define PADDR_BITS 48 -#else -#define PADDR_BITS 40 -#endif +#define PADDR_BITS CONFIG_PADDR_BITS #endif /* __ARM_PAGE_SHIFT_H__ */ diff --git a/xen/arch/arm/include/asm/types.h b/xen/arch/arm/include/asm/types.h index e218ed77bd..e3cfbbb060 100644 --- a/xen/arch/arm/include/asm/types.h +++ b/xen/arch/arm/include/asm/types.h @@ -34,9 +34,15 @@ typedef signed long long s64; typedef unsigned long long u64; typedef u32 vaddr_t; #define PRIvaddr PRIx32 +#if defined(CONFIG_PHYS_ADDR_T_32) +typedef unsigned long paddr_t; +#define INVALID_PADDR (~0UL) +#define PRIpaddr "08lx" +#else typedef u64 paddr_t; #define INVALID_PADDR (~0ULL) #define PRIpaddr "016llx" +#endif typedef u32 register_t; #define PRIregister "08x" #elif defined (CONFIG_ARM_64) diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index b99806af99..d8b43ef38c 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -690,6 +690,7 @@ void __init setup_frametable_mappings(paddr_t ps, paddr_t pe) const unsigned long mapping_size = frametable_size < MB(32) ? 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bh=Xotrsbhl/FLSUoI3qOBJKeSy4Rd9/LSb5Psg/+0wEqU=; b=UJegmBtONBMdn8jgImCM1TXmpzonBv6AAiueDvVkVWynJOKOXw0P557KDY2Gu/CBLaakrj7OtirbhexPNVMjsVosamGBdP1IrUC8AIiEchHwWFLfnRse/V54qQPrpnzIuTGt/ajBBNPvbrbj4K2Ccq7xYudA1Mi0FUpFr9SXn6U= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 08/11] xen/arm: guest_walk: LPAE specific bits should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32" Date: Tue, 21 Mar 2023 14:03:54 +0000 Message-ID: <20230321140357.24094-9-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E654:EE_|DM6PR12MB4418:EE_ X-MS-Office365-Filtering-Correlation-Id: c6eedad3-5752-4a2e-a25d-08db2a15535c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:28.3380 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c6eedad3-5752-4a2e-a25d-08db2a15535c X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E654.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4418 As the previous patch introduces CONFIG_PHYS_ADDR_T_32 to support 32 bit physical addresses, the code specific to "Large Physical Address Extension" (ie LPAE) should be enclosed within "ifndef CONFIG_PHYS_ADDR_T_32". Refer xen/arch/arm/include/asm/short-desc.h, "short_desc_l1_supersec_t" unsigned int extbase1:4; /* Extended base address, PA[35:32] */ unsigned int extbase2:4; /* Extended base address, PA[39:36] */ Thus, extbase1 and extbase2 are not valid when 32 bit physical addresses are supported. Signed-off-by: Ayan Kumar Halder Acked-by: Stefano Stabellini --- Changes from - v1 - 1. Extracted from "[XEN v1 8/9] xen/arm: Other adaptations required to support 32bit paddr". v2 - 1. Reordered this patch so that it appears after CONFIG_ARM_PA_32 is introduced (in 6/9). v3 - 1. Updated the commit message. 2. Added Ack. xen/arch/arm/guest_walk.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/xen/arch/arm/guest_walk.c b/xen/arch/arm/guest_walk.c index 43d3215304..c80a0ce55b 100644 --- a/xen/arch/arm/guest_walk.c +++ b/xen/arch/arm/guest_walk.c @@ -154,8 +154,10 @@ static bool guest_walk_sd(const struct vcpu *v, mask = (1ULL << L1DESC_SUPERSECTION_SHIFT) - 1; *ipa = gva & mask; *ipa |= (paddr_t)(pte.supersec.base) << L1DESC_SUPERSECTION_SHIFT; +#ifndef CONFIG_PHYS_ADDR_T_32 *ipa |= (paddr_t)(pte.supersec.extbase1) << L1DESC_SUPERSECTION_EXT_BASE1_SHIFT; *ipa |= (paddr_t)(pte.supersec.extbase2) << L1DESC_SUPERSECTION_EXT_BASE2_SHIFT; +#endif /* CONFIG_PHYS_ADDR_T_32 */ } /* Set permissions so that the caller can check the flags by herself. */ From patchwork Tue Mar 21 14:03:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13182829 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 098B8C74A5B for ; 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bh=iKVGGJrESWsLzoLGHnzYf6BFviRvh/CY/WThQ1yLYG8=; b=j2FtKS7BjLjLwRpWnzBUMVTQDXNP9vJGYCUv0p6JrsakkaQ/2EP6SFu+rYw7kMMoXBmC6fgKdLiVEuawbd4hPdfwBrTyOAJ+5+6eS/pxFoBsKtKXhjVKUap63JVavFi5pP2srBo0FNGNw4AhigCcj/Ly8A3dVmMXH7hn7R8CCkA= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 09/11] xen/arm: Restrict zeroeth_table_offset for ARM_64 Date: Tue, 21 Mar 2023 14:03:55 +0000 Message-ID: <20230321140357.24094-10-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF0000E653:EE_|PH8PR12MB7027:EE_ X-MS-Office365-Filtering-Correlation-Id: 1a272155-57fc-44ff-ffbe-08db2a155570 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:31.8268 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1a272155-57fc-44ff-ffbe-08db2a155570 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF0000E653.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7027 When 32 bit physical addresses are used (ie ARM_PA_32=y), "va >> ZEROETH_SHIFT" causes an overflow. Also, there is no zeroeth level page table on Arm 32-bit. Also took the opportunity to clean up dump_pt_walk(). One could use DECLARE_OFFSETS() macro instead of declaring the declaring an array of page table offsets. Acked-by: Julien Grall Reviewed-by: Stefano Stabellini Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - Removed the duplicate declaration for DECLARE_OFFSETS. v2 - 1. Reworded the commit message. 2. Use CONFIG_ARM_PA_32 to restrict zeroeth_table_offset. v3 - 1. Added R-b and Ack. xen/arch/arm/include/asm/lpae.h | 4 ++++ xen/arch/arm/mm.c | 7 +------ 2 files changed, 5 insertions(+), 6 deletions(-) diff --git a/xen/arch/arm/include/asm/lpae.h b/xen/arch/arm/include/asm/lpae.h index 3fdd5d0de2..0d40388f93 100644 --- a/xen/arch/arm/include/asm/lpae.h +++ b/xen/arch/arm/include/asm/lpae.h @@ -259,7 +259,11 @@ lpae_t mfn_to_xen_entry(mfn_t mfn, unsigned int attr); #define first_table_offset(va) TABLE_OFFSET(first_linear_offset(va)) #define second_table_offset(va) TABLE_OFFSET(second_linear_offset(va)) #define third_table_offset(va) TABLE_OFFSET(third_linear_offset(va)) +#ifdef CONFIG_ARM_PA_BITS_32 +#define zeroeth_table_offset(va) 0 +#else #define zeroeth_table_offset(va) TABLE_OFFSET(zeroeth_linear_offset(va)) +#endif /* * Macros to define page-tables: diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index d8b43ef38c..41e0896b0f 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -221,12 +221,7 @@ void dump_pt_walk(paddr_t ttbr, paddr_t addr, { static const char *level_strs[4] = { "0TH", "1ST", "2ND", "3RD" }; const mfn_t root_mfn = maddr_to_mfn(ttbr); - const unsigned int offsets[4] = { - zeroeth_table_offset(addr), - first_table_offset(addr), - second_table_offset(addr), - third_table_offset(addr) - }; + DECLARE_OFFSETS(offsets, addr); lpae_t pte, *mapping; unsigned int level, root_table; From patchwork Tue Mar 21 14:03:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13182830 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 01879C761A6 for ; Tue, 21 Mar 2023 14:14:14 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.512709.792858 (Exim 4.92) (envelope-from ) id 1pecka-0004Eu-6Z; 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bh=bcfEw0YmhpLuK5yfYdcOma+HR1pKGZ8HcIt8DLoLQyI=; b=qnS6WYbUuTw4AXb16ZtPssyvHsbcivqPAGQtQ8n68PFNRWMxy6AXZK7jYM16DinY6IaCTsNUQt5704a/YAA+7XZdcQirnfg5lW/Kun9ZCWP9pRzM/yAaay6c/U/5IU1PgoGsBcLXGW+Pf0QbNXAmnIJVG9mnCTkAziitc6Ez65c= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 10/11] xen/arm: p2m: Use the pa_range_info table to support Arm_32 and Arm_64 Date: Tue, 21 Mar 2023 14:03:56 +0000 Message-ID: <20230321140357.24094-11-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT013:EE_|IA1PR12MB6330:EE_ X-MS-Office365-Filtering-Correlation-Id: 79928000-796f-4c80-5b07-08db2a155dac X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:45.7001 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 79928000-796f-4c80-5b07-08db2a155dac X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT013.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6330 Restructure the code so that one can use pa_range_info[] table for both ARM_32 as well as ARM_64. Signed-off-by: Ayan Kumar Halder --- Changes from - v3 - 1. New patch introduced in v4. 2. Restructure the code such that pa_range_info[] is used both by ARM_32 as well as ARM_64. xen/arch/arm/p2m.c | 28 +++++++++++++++------------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index 948f199d84..f34b6e6f11 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2265,22 +2265,16 @@ void __init setup_virt_paging(void) /* Setup Stage 2 address translation */ register_t val = VTCR_RES1|VTCR_SH0_IS|VTCR_ORGN0_WBWA|VTCR_IRGN0_WBWA; -#ifdef CONFIG_ARM_32 - if ( p2m_ipa_bits < 40 ) - panic("P2M: Not able to support %u-bit IPA at the moment\n", - p2m_ipa_bits); - - printk("P2M: 40-bit IPA\n"); - p2m_ipa_bits = 40; - val |= VTCR_T0SZ(0x18); /* 40 bit IPA */ - val |= VTCR_SL0(0x1); /* P2M starts at first level */ -#else /* CONFIG_ARM_64 */ static const struct { unsigned int pabits; /* Physical Address Size */ unsigned int t0sz; /* Desired T0SZ, minimum in comment */ unsigned int root_order; /* Page order of the root of the p2m */ unsigned int sl0; /* Desired SL0, maximum in comment */ } pa_range_info[] __initconst = { +#ifdef CONFIG_ARM_32 + [0] = { 40, 24/*24*/, 1, 1 }, + [1] = { 0 } /* Invalid */ +#else /* T0SZ minimum and SL0 maximum from ARM DDI 0487H.a Table D5-6 */ /* PA size, t0sz(min), root-order, sl0(max) */ [0] = { 32, 32/*32*/, 0, 1 }, @@ -2291,11 +2285,13 @@ void __init setup_virt_paging(void) [5] = { 48, 16/*16*/, 0, 2 }, [6] = { 52, 12/*12*/, 4, 2 }, [7] = { 0 } /* Invalid */ +#endif }; unsigned int i; unsigned int pa_range = 0x10; /* Larger than any possible value */ +#ifdef CONFIG_ARM_64 /* * Restrict "p2m_ipa_bits" if needed. As P2M table is always configured * with IPA bits == PA bits, compare against "pabits". @@ -2309,6 +2305,9 @@ void __init setup_virt_paging(void) */ if ( system_cpuinfo.mm64.vmid_bits == MM64_VMID_16_BITS_SUPPORT ) max_vmid = MAX_VMID_16_BIT; +#else + p2m_ipa_bits = PADDR_BITS; +#endif /* Choose suitable "pa_range" according to the resulted "p2m_ipa_bits". */ for ( i = 0; i < ARRAY_SIZE(pa_range_info); i++ ) @@ -2324,14 +2323,13 @@ void __init setup_virt_paging(void) if ( pa_range >= ARRAY_SIZE(pa_range_info) || !pa_range_info[pa_range].pabits ) panic("Unknown encoding of ID_AA64MMFR0_EL1.PARange %x\n", pa_range); - val |= VTCR_PS(pa_range); +#ifdef CONFIG_ARM_64 val |= VTCR_TG0_4K; + val |= VTCR_PS(pa_range); /* Set the VS bit only if 16 bit VMID is supported. */ if ( MAX_VMID == MAX_VMID_16_BIT ) val |= VTCR_VS; - val |= VTCR_SL0(pa_range_info[pa_range].sl0); - val |= VTCR_T0SZ(pa_range_info[pa_range].t0sz); p2m_root_order = pa_range_info[pa_range].root_order; p2m_root_level = 2 - pa_range_info[pa_range].sl0; @@ -2342,6 +2340,10 @@ void __init setup_virt_paging(void) pa_range_info[pa_range].pabits, ( MAX_VMID == MAX_VMID_16_BIT ) ? 16 : 8); #endif + + val |= VTCR_SL0(pa_range_info[pa_range].sl0); + val |= VTCR_T0SZ(pa_range_info[pa_range].t0sz); + printk("P2M: %d levels with order-%d root, VTCR 0x%"PRIregister"\n", 4 - P2M_ROOT_LEVEL, P2M_ROOT_ORDER, val); From patchwork Tue Mar 21 14:03:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ayan Kumar Halder X-Patchwork-Id: 13182817 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5151C6FD1D for ; Tue, 21 Mar 2023 14:05:52 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.512686.792828 (Exim 4.92) (envelope-from ) id 1peccT-0000Yf-Mw; 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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB03.amd.com; pr=C From: Ayan Kumar Halder To: CC: , , , , , , , , , , Ayan Kumar Halder Subject: [XEN v4 11/11] xen/arm: p2m: Enable support for 32bit IPA for ARM_32 Date: Tue, 21 Mar 2023 14:03:57 +0000 Message-ID: <20230321140357.24094-12-ayan.kumar.halder@amd.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230321140357.24094-1-ayan.kumar.halder@amd.com> References: <20230321140357.24094-1-ayan.kumar.halder@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT076:EE_|DS7PR12MB6144:EE_ X-MS-Office365-Filtering-Correlation-Id: 6928ca25-aba4-4dda-565d-08db2a155954 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Mar 2023 14:05:38.4123 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6928ca25-aba4-4dda-565d-08db2a155954 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT076.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6144 The pabits, t0sz, root_order and sl0 values are the same as those for ARM_64. Signed-off-by: Ayan Kumar Halder --- Changes from - v1 - New patch. v2 - 1. Added Ack. v3 - 1. Dropped Ack. 2. Rebased the patch based on the previous change. xen/arch/arm/p2m.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/xen/arch/arm/p2m.c b/xen/arch/arm/p2m.c index f34b6e6f11..20beecc6e8 100644 --- a/xen/arch/arm/p2m.c +++ b/xen/arch/arm/p2m.c @@ -2272,8 +2272,9 @@ void __init setup_virt_paging(void) unsigned int sl0; /* Desired SL0, maximum in comment */ } pa_range_info[] __initconst = { #ifdef CONFIG_ARM_32 - [0] = { 40, 24/*24*/, 1, 1 }, - [1] = { 0 } /* Invalid */ + [0] = { 32, 32/*32*/, 0, 1 }, + [1] = { 40, 24/*24*/, 1, 1 }, + [2] = { 0 } /* Invalid */ #else /* T0SZ minimum and SL0 maximum from ARM DDI 0487H.a Table D5-6 */ /* PA size, t0sz(min), root-order, sl0(max) */