From patchwork Thu Mar 23 17:30:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185914 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C12AC6FD1C for ; Thu, 23 Mar 2023 17:31:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231486AbjCWRbR (ORCPT ); Thu, 23 Mar 2023 13:31:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231516AbjCWRbR (ORCPT ); Thu, 23 Mar 2023 13:31:17 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E405A241DA for ; Thu, 23 Mar 2023 10:31:10 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id p13-20020a17090a284d00b0023d2e945aebso4020343pjf.0 for ; Thu, 23 Mar 2023 10:31:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=km2gqXc7azHXISk3TRRkbz6777YLDRrwj5fuSfpq1q8=; b=KCgwX9Jxa6ZuTKmTith9SO5UOsRsmngKseZno4cqXEm7+jy1lVMNhTL1iOBxxM5TxK oYE8Dll9PNG+8RA0LbuHxpwQIZxHdl8kOBdP4qkOWRFfmZlXmgW7smhrcv73a8Vu18z4 0zVIqv9teDevEYUSrhbLRlUA2va7Vj4PC4tN8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592670; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=km2gqXc7azHXISk3TRRkbz6777YLDRrwj5fuSfpq1q8=; b=n3jx7f++y9iEJ1yVB7bh/wVMwbhXyDWFadoW2CUqMmb/ygkVEUPfITlXsPvOLABRha CMUKm7a/WlSo8XNOns+izChWDc5xujcK1D8lA7vhqRwuOO3UMbBgU+IqmDoYZOIDx0lR moAvkUp9gTXL7yGIVSx3mWpAVr8CSESvx495GFpAcghqOWIrz26vRm1wb0MnyRQ5iA4F zQOAYzHJz+Fzyg/LoJtSxT5fKKXe+IRlG5CdTLEn4CmY0JEkyRgTAKc8jxeeSDVI9pN9 vzqi3edzcdYqkbpyMxvVq3tdPIlQ8TsEEPP4kfzOwx9SId6OO8gqPGCNGnAdmY1+V4bX 3mWw== X-Gm-Message-State: AO0yUKUht2r2tPg6wPOgQyT57mRDGxdWlPZO63ifrqNE1YkOqi8JmJvH LmQr9AF4XtCJ10MGbvScp1GnBw== X-Google-Smtp-Source: AK7set/eq0TFdASOKnSDm1Sm/iWmOncE+NdY4v8Uy8PcDjyvmJd7KNfv2/GAbFmZOvVhygT3gxRmiQ== X-Received: by 2002:a05:6a20:8b9c:b0:da:d9e7:9a5d with SMTP id m28-20020a056a208b9c00b000dad9e79a5dmr400673pzh.4.1679592669751; Thu, 23 Mar 2023 10:31:09 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:09 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , Rajendra Nayak , Roja Rani Yarubandi , linux-kernel@vger.kernel.org Subject: [PATCH 01/14] arm64: dts: sc7180: Rename qspi data12 as data23 Date: Thu, 23 Mar 2023 10:30:05 -0700 Message-Id: <20230323102605.1.Ifc1b5be04653f4ab119698a5944bfecded2080d6@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: ba3fc6496366 ("arm64: dts: sc7180: Add qupv3_0 and qupv3_1") Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7180.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index ebfa21e9ed8a..fe62ce516c4e 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1540,7 +1540,7 @@ qspi_data01: qspi-data01-state { function = "qspi_data"; }; - qspi_data12: qspi-data12-state { + qspi_data23: qspi-data23-state { pins = "gpio66", "gpio67"; function = "qspi_data"; }; From patchwork Thu Mar 23 17:30:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185917 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2799C74A5B for ; Thu, 23 Mar 2023 17:31:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232214AbjCWRb1 (ORCPT ); Thu, 23 Mar 2023 13:31:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44020 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232216AbjCWRbW (ORCPT ); Thu, 23 Mar 2023 13:31:22 -0400 Received: from mail-pg1-x535.google.com (mail-pg1-x535.google.com [IPv6:2607:f8b0:4864:20::535]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E92A826CEF for ; Thu, 23 Mar 2023 10:31:12 -0700 (PDT) Received: by mail-pg1-x535.google.com with SMTP id x37so13018194pga.1 for ; Thu, 23 Mar 2023 10:31:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LHcHlbRFQY1a3JxFlrTE/SnrAnzBxSKk8fubRmial5c=; b=fa1AbAuC4lMywoWwSoxWcDq285CBpRd8wXgmJnExNcYHfkUP1ByNGsnGs2A+nRC58g IhBPVm84vP7b9SjRBDVPetgiMJK3hzuEBeEk/aTsLjmFl1GMxcmBJTPfNls0eXD6mO38 Ot9J34CJK0XUpgnnWoc0fCWj8B4ePd39cTIuY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592672; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LHcHlbRFQY1a3JxFlrTE/SnrAnzBxSKk8fubRmial5c=; b=0vK1W6BcxkG5p8SIAtX0Ibs8J5gFz11zc4JtL1wjmo8qUouq7TRdE2NEH1wI3ry3O7 X274jsIIeTwjoNN+GtJrpQKDUr00mvuRbI5xJCLPc29Xz/KurrQEFbkwQSS8zdKOAGIN bIvtdzzRsD3qvMU8zHI8aIY9KAp0aVnL2zsb5C51P8g8PO3X86t1uw6qBvTSUnLWhHkx CsuyOcz6oGGMhS4H6Q++u4G02X6z3zOVivZfJUHmdC6g3RwIFg3/7o3IoGWeHobtvxQk RBUM1T10PWX2GR17ulZ87rfBu9LG3T51oyJAXRVepUGYa6h1+cYYrSMcEBMRuxWwnD/V wLmw== X-Gm-Message-State: AAQBX9eanXpL6yE8y/Lj5G3hGD6i8gIjtAcrMFrc07z8VJm3e07Evoha 7UuXNTOiXe+rXMSZkDyhy9rYZg== X-Google-Smtp-Source: AKy350YRQbAsTlxP8jPotY6cwhOcbMsZEQmWDnFz9TlVTur3weEs/Ki80n/8ugba1vq19+wsolyKlQ== X-Received: by 2002:aa7:94ba:0:b0:627:f756:b206 with SMTP id a26-20020aa794ba000000b00627f756b206mr260563pfl.1.1679592671782; Thu, 23 Mar 2023 10:31:11 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:11 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , Rajesh Patil , Roja Rani Yarubandi , linux-kernel@vger.kernel.org Subject: [PATCH 02/14] arm64: dts: sc7280: Rename qspi data12 as data23 Date: Thu, 23 Mar 2023 10:30:06 -0700 Message-Id: <20230323102605.2.I4043491bb24b1e92267c5033d76cdb0fe60934da@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: 7720ea001b52 ("arm64: dts: qcom: sc7280: Add QSPI node") Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index bdcb74925313..71e2e51c7c7f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4342,7 +4342,7 @@ qspi_data01: qspi-data01-state { function = "qspi_data"; }; - qspi_data12: qspi-data12-state { + qspi_data23: qspi-data23-state { pins = "gpio16", "gpio17"; function = "qspi_data"; }; From patchwork Thu Mar 23 17:30:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63D09C77B6C for ; Thu, 23 Mar 2023 17:31:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232308AbjCWRb0 (ORCPT ); Thu, 23 Mar 2023 13:31:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43976 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231556AbjCWRbX (ORCPT ); Thu, 23 Mar 2023 13:31:23 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4F5C27D6A for ; Thu, 23 Mar 2023 10:31:14 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id j3-20020a17090adc8300b0023d09aea4a6so2643193pjv.5 for ; Thu, 23 Mar 2023 10:31:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Q/zeFLtT5svFzGSOkobW0E5oP7EbYRFgi9o291n1fds=; b=boK1pbwfD/kYb4hq6aRa2l1YdEoUbvsvhKq6ynUQNzmwi7Jv/PhGDBu5Bx1f6HvNmn +khbFlnkQMzS1vnj/PR7JEto7gmj8WiTli3UEBDkSnzmGBO4IjkpU4y2asHr8V/a7iDS 94iajP4/4tBFsAcYJKwUUfFsYUkBQkDxkA1Io= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Q/zeFLtT5svFzGSOkobW0E5oP7EbYRFgi9o291n1fds=; b=jskO2BpL9VFxVScYA556WhcvCYzsE+BvpOWBmSIF5n7p4gOZ6ty6RfbHCw99jYGIsb G4K89hdHIdIBEnHvu3/yquqWjk6wk8CVP9BMkbIsDRiSn5PkOHcFVcsemUd/dGRIFbik 6MHNfo6qXjOqaLnrwrAk1AZqVPwMnpiC4sZy+e+eMbBH5z9KTpAmgQHBG5oTWfg0cshb Xn5FRi5kaFuVJEsiFtXdJmA05OS4nan+XK4XswR6vewzRFYTaWPITaY2EIBoz7ok/sIG iahwgz8Vcvn6kdejLVAGnkxwI3aOGF/M1WeSTdaVuuL8FFqWoyYnpPwzrpR9F6Yl3Q1N xwPQ== X-Gm-Message-State: AO0yUKXpa7iQc+jn2wlkUOzOXo3SWe8HDUwzsnSfAjnaQZPHbUczDjFE DJsHuzHroWlSk25Lywy0xFN2OQ== X-Google-Smtp-Source: AK7set8xZYhtJRYs2MfbgIfoHpLj82VbbGDiATnaAmjPI0WzHRRjr0Glpcmwp9jUtedg4qA792B6KQ== X-Received: by 2002:a05:6a20:4d92:b0:da:aaec:9455 with SMTP id gj18-20020a056a204d9200b000daaaec9455mr304246pzb.43.1679592673682; Thu, 23 Mar 2023 10:31:13 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:13 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 03/14] arm64: dts: sdm845: Rename qspi data12 as data23 Date: Thu, 23 Mar 2023 10:30:07 -0700 Message-Id: <20230323102605.3.I88528d037b7fda4e53a40f661be5ac61628691cd@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org There are 4 qspi data pins: data0, data1, data2, and data3. Currently we have a shared pin state for data0 and data1 (2 lane config) and a pin state for data2 and data3 (you'd enable both this and the 2 lane state for 4 lanes). The second state is obviously misnamed. Fix it. Fixes: e1ce853932b7 ("arm64: dts: qcom: sdm845: Add qspi (quad SPI) node") Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index 479859bd8ab3..aafc7cc7edd8 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2763,7 +2763,7 @@ qspi_data01: qspi-data01-state { function = "qspi_data"; }; - qspi_data12: qspi-data12-state { + qspi_data23: qspi-data23-state { pins = "gpio93", "gpio94"; function = "qspi_data"; }; From patchwork Thu Mar 23 17:30:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185918 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADBD5C74A5B for ; Thu, 23 Mar 2023 17:31:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232384AbjCWRb3 (ORCPT ); Thu, 23 Mar 2023 13:31:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232250AbjCWRbX (ORCPT ); Thu, 23 Mar 2023 13:31:23 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6B37E28E7A for ; Thu, 23 Mar 2023 10:31:17 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id bt19so89161pfb.3 for ; Thu, 23 Mar 2023 10:31:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6kiM2lrh2kvgdALZI8OIkWyLB50SqdxAm52tOpr2esY=; b=HXiP72pym+YYw/orvrMjuH/G76artp0TTfq7fhSlUPoJldbPdKxo3MqETM7XoMrCX/ 5MljJsHVpAL1rPPYKJFros7D3ckXNFp7LvANq7FzWMN8EXqeau3FUOkkmfu430yNwGtk rNzLOsjj27FpxdgtXZE5PmSLTxs0yAK+PEzT4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592677; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6kiM2lrh2kvgdALZI8OIkWyLB50SqdxAm52tOpr2esY=; b=19EQj9Pa/ICrtROHHylSFZNdCotcFR5ptZyF5gwlpgXV7abydwyp8QunSaXV9IcdJ1 HBs2TN5dW1nKk72R9fsts7UX3RNBkRr+OjA9UWOT0dvZ7Kzysw55s6lZJ82hxB60S07c I4ntrUzR/s6shyLU73aeDd4iXjqFwlbHabJQc8FrGdU74Va6XMSfybFXxhxg9cqT7n69 Tkh6yKCaR9kph/neZJo+w0nkUg1iwXnp6hD9WJmHIhqRRXnQtngv9c2IwEL793WVxQl9 g2U9D3b5bQbHHV2Wfs3rdz0W0pzQb/kwSy8jO9qOwEQZ5ZZAcOQaCo41uu8yFQRPVbMw u0cw== X-Gm-Message-State: AAQBX9elvyR7R/i8FhwsdfgtesC/zDTmqiARXg2vEHKAb+TranhDHwxv qymph7Pp3nBsr3V07Q9B/bnmfQ== X-Google-Smtp-Source: AKy350buG3y4PZg93OsVSfDc5+NHl/qYArOkaLVdvFImYeKdyz7hN2Fv645vPTrSh6BE5heW32nH9g== X-Received: by 2002:a62:8413:0:b0:624:d72e:e629 with SMTP id k19-20020a628413000000b00624d72ee629mr251075pfd.8.1679592676912; Thu, 23 Mar 2023 10:31:16 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:15 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 04/14] arm64: dts: qcom: sc7180: Annotate l13a on trogdor to always-on Date: Thu, 23 Mar 2023 10:30:08 -0700 Message-Id: <20230323102605.4.I9f47a8a53eacff6229711a827993792ceeb36971@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The l13a rail on trogdor devices has always been intended to be always-on on both S0 and S3. Different trogdor variants use l13a in slightly different ways, but the overall theme is that it's a 1.8V rail that the board uses for things that it wants powered in on S0 and S3. On many boards this includes the boot SPI (AKA qspi). For all intents and purposes this patch is actually a no-op since something else in the system seems to already be keeping the rail on all the time (confirmed via multimeter). That "something else" was postulated to be the modem but the rail is on / stays on even without the modem/wifi coming up so it's likely the boot config. In any case, making the fact that this is always-on explicit seems like a good idea. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 423630c4d02c..1f2e1f701761 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -512,6 +512,8 @@ pp1800_l13a: ldo13 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; regulator-initial-mode = ; + regulator-always-on; + regulator-boot-on; }; pp1800_prox: From patchwork Thu Mar 23 17:30:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9116DC761AF for ; Thu, 23 Mar 2023 17:31:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231901AbjCWRba (ORCPT ); Thu, 23 Mar 2023 13:31:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232265AbjCWRbY (ORCPT ); Thu, 23 Mar 2023 13:31:24 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3BE9D2686C for ; Thu, 23 Mar 2023 10:31:20 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id k2so22980613pll.8 for ; Thu, 23 Mar 2023 10:31:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=axzKHWKEv5YVhGt7OnDPPiY6mPvXZ76IZmLOehTivRM=; b=Hr6ofu6oqBQij15HDorCxP6qJd/DFWqt6l/Ey7WIKytvKq0Hg1t6qCmeE664vXR+Z9 N59aPdWEExquxwyH812aZNz20iZjJTt5Bk3jJvB2U7kgSZVLQutKqiBNL36uDXjSqWfU jL5NAUAv3Uxd6DivSrdFnrub1l7TcPWrtBjyk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592680; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=axzKHWKEv5YVhGt7OnDPPiY6mPvXZ76IZmLOehTivRM=; b=E737PzL428FPLzRfe62aC0cK6xa4aiaP6M0yMFChXqjJrNhATjrbSQ2B93qKdJQjrY 4DcV3VOimefTkfqXgFmgRFHwttOrn4mhyIGHXNavsEq59OQdmf2yxOL+mS5IZIYNqDVM Blg1LjnQFlIamj6vgy49RUAOpYIjWCmRiacuo70jfMKPYPDXMGkSaLiDmCvZIkWq7CUr qSoLmKOcRvQJeplpHz+Al4LV326cLzr5J1jeKcm40cioAlAZVodknCwrRHILlTx+c9Ue 9YCn68M6Jfjw/41mlMFmsYA4R/W5UiXfKIJgIEnd8EQsz0o8L09vvs7aETJ74b6CqgUs hQvw== X-Gm-Message-State: AO0yUKW4Gj6Tlmzi8v+XKMVPAGM1pBU9Xf0SBEa1Hh4qGmK159Olqc4a HqNDdfpsNB1axaECgkNG8jvzEg== X-Google-Smtp-Source: AK7set98W2pL/pZaFCyJ1kV68FLpW0uLABrjIbr4GjXq3ykVerKMR6GAGJsUb4A7bHVMxCGlYMXUNg== X-Received: by 2002:a05:6a20:8b14:b0:d9:840f:79c2 with SMTP id l20-20020a056a208b1400b000d9840f79c2mr464959pzh.2.1679592679750; Thu, 23 Mar 2023 10:31:19 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:18 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 05/14] spi: spi-qcom-qspi: Support pinctrl sleep states Date: Thu, 23 Mar 2023 10:30:09 -0700 Message-Id: <20230323102605.5.I79544b9486033bd7b27f2be55adda6d36f62a366@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org It's fairly common practice for drivers to switch to a "sleep" pinctrl state at the end of its runtime_suspend function and then back to "default" at the beginning of runtime_resume. Let's do that for spi-qcom-qspi. Signed-off-by: Douglas Anderson --- drivers/spi/spi-qcom-qspi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spi/spi-qcom-qspi.c b/drivers/spi/spi-qcom-qspi.c index c334dfec4117..7851cf1986cc 100644 --- a/drivers/spi/spi-qcom-qspi.c +++ b/drivers/spi/spi-qcom-qspi.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -581,6 +582,8 @@ static int __maybe_unused qcom_qspi_runtime_suspend(struct device *dev) return ret; } + pinctrl_pm_select_sleep_state(dev); + return 0; } @@ -590,6 +593,8 @@ static int __maybe_unused qcom_qspi_runtime_resume(struct device *dev) struct qcom_qspi *ctrl = spi_master_get_devdata(master); int ret; + pinctrl_pm_select_default_state(dev); + ret = icc_enable(ctrl->icc_path_cpu_to_qspi); if (ret) { dev_err_ratelimited(ctrl->dev, "%s: ICC enable failed for cpu: %d\n", From patchwork Thu Mar 23 17:30:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 338BDC76196 for ; Thu, 23 Mar 2023 17:31:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232445AbjCWRbk (ORCPT ); Thu, 23 Mar 2023 13:31:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232213AbjCWRbZ (ORCPT ); Thu, 23 Mar 2023 13:31:25 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9D8BE2B9D8 for ; Thu, 23 Mar 2023 10:31:23 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id j3-20020a17090adc8300b0023d09aea4a6so2643629pjv.5 for ; Thu, 23 Mar 2023 10:31:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FoRlfx7CbmqnP3zURzbR63MNq645Q0jdEhms+74MeYc=; b=kAbV/I/7xnERMCRUryA9uRdH+3r0Gbql1oICa8dpLQkpw3nzC30aFv0O2WVZhad+Rg z/5TPz2pe2fz4w0QwV2aTcCxsSSCzZRWT4Rb7+IXKwSWE25W9HVRgq2ygsxETUMA6Yeu 1bfWQmuHyrMczCGKRaLFy9bXJTz805huHOKHY= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592683; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FoRlfx7CbmqnP3zURzbR63MNq645Q0jdEhms+74MeYc=; b=IY0gr76AsDJbdZpTb+V8+i0rPuXHNxF/Zq9QSo3k8eGxbIEhDwHQB4PLD1DaYlYLC8 Ku/mpGgNfew7hVWHxwpkALUJPEzxYtCfoZ641PZWoMuJKzNAhejnj69c82GASSE0jQw/ n/QsrPHPhd3tW0teB3g+XLPijnt7rQ1loH9IHH/pNa3jzzwcKDSw2UWEcs+ffyLnIsbA exRu7QC6FGJ21nzvsyI6K7lq1pQTRFnBoSamvTSXmAINHeBmy2bHWUYY6vMVz+iXdM4v 0uoF7Z/HfLKMsJyhqpeRqFa0TzO/jNMKnJZDw120rfwK8CPxQqKpaQF52s/nWeFKMUYJ Bgdg== X-Gm-Message-State: AO0yUKVUVDEXwbRt7O5+JpFU/JpCPZgqLSefiTH8ZXC1WLLG2h9SaH6e w8/YUVxuyNirnXKM99f3KsfgBQ== X-Google-Smtp-Source: AK7set+wKfX/T8HiiMPPsgLGNmM1PcdDUUn5hrO5kvSgLUVSymrEOe8m2EhrenDZ8jrFoHqrR+7FrA== X-Received: by 2002:a05:6a20:33a8:b0:d4:c605:4512 with SMTP id f40-20020a056a2033a800b000d4c6054512mr318424pzd.30.1679592683296; Thu, 23 Mar 2023 10:31:23 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:21 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 06/14] dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable Date: Thu, 23 Mar 2023 10:30:10 -0700 Message-Id: <20230323102605.6.I291ce0ba2c6ea80b341659c4f75a567a76dd7ca6@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org As evidenced by the Qualcomm TLMM Linux driver, the TLMM IP block in Qualcomm SoCs has a bit to enable/disable the output for a pin that's configured as a GPIO but _not_ a bit to enable/disable an input buffer. Current device trees that are specifying "input-enable" for pins managed by TLMM are either doing so needlessly or are using it to mean "output-disable". Presumably the current convention of using "input-enable" to mean "output-disable" stems from the fact that "output-disable" is a "new" property from 2017. It was introduced in commit 425562429d4f ("pinctrl: generic: Add output-enable property"). The "input-enable" handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property"). Given that there's no other use for "input-enable" for TLMM, we can still handle old device trees in code, but let's encourage people to move to the proper / documented property by updating the bindings. Signed-off-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pinctrl/qcom,tlmm-common.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index cb5ba1bd6f8d..5a815c199642 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -75,7 +75,8 @@ $defs: bias-pull-down: true bias-pull-up: true bias-disable: true - input-enable: true + input-enable: false + output-disable: true output-high: true output-low: true From patchwork Thu Mar 23 17:30:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8F4D6C74A5B for ; Thu, 23 Mar 2023 17:31:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232484AbjCWRbp (ORCPT ); Thu, 23 Mar 2023 13:31:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232366AbjCWRb3 (ORCPT ); Thu, 23 Mar 2023 13:31:29 -0400 Received: from mail-pf1-x42b.google.com (mail-pf1-x42b.google.com [IPv6:2607:f8b0:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CC102798D for ; Thu, 23 Mar 2023 10:31:26 -0700 (PDT) Received: by mail-pf1-x42b.google.com with SMTP id y2so9276420pfw.9 for ; Thu, 23 Mar 2023 10:31:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PrlHsI5Z/NNnOc1NjNfOu1jz21Q+M+e28AawYyOfx3M=; b=edHQ2+I5cm1iMvu/Yj4j6Xbo05S5NenSnnJ/8+XM+FqQ9x1iG7FiNzB4IqHhkdKkdy I7hNLoWg0LzzdN1YAC5hKBHtRdEq0ZUvRvp4YkxNHFhYoF36rHr7JoId7M/TCNQpSQj0 2YixmX4hf3itZ3gWw9KyqAqkg0eMTKQYXPTgU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592686; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PrlHsI5Z/NNnOc1NjNfOu1jz21Q+M+e28AawYyOfx3M=; b=gqZJYGii93Cf9XYZ2CGfQ0SWbtQMnlG4WTdMmdBMCDQaj6H5FNy5Ly3E1qMS67ohwA L0Ve7qpp/n1PDJN3D1kyPYbGdxh/hi2bhE/WaD57LfV5sfypFtbppuokpt34sudQiWpK KRRiM2YOzD8CeEQ03gKKj/7A1eImmtkOJNdYTXg55F1/svQFYDAeYX1udlAnc9SWSMMT 4IL4YUWROkoW0zzvR7B1OCBp2W/HVtZljygDtRIu2UQfQOtLKpKYGEl8zNI5tJNR7KI5 ZmIJ1RLGbmLgcptXiDEJGk0c7QXQy+qAPJeqnJcFZaTjEq8NO8K9cN6/1vxBk5WS0ey2 NrBg== X-Gm-Message-State: AO0yUKW8GgKqK2u1pzKgy7NW5hb9GQoE3K9MNbXLBBWhiHd8/AzH/M+V Um4/bfRIZdnX2EF5Gs/5v0bbRg== X-Google-Smtp-Source: AKy350aipydQzWbD4aLzbW5qWar+RQQyGCphddK1U85iT9QM7zEOrgHW0QB0QuHoYtR6mtAQbvOAAw== X-Received: by 2002:a62:1941:0:b0:5e2:434d:116b with SMTP id 62-20020a621941000000b005e2434d116bmr179799pfz.23.1679592685919; Thu, 23 Mar 2023 10:31:25 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:24 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 07/14] dt-bindings: pinctrl: qcom: Add output-enable Date: Thu, 23 Mar 2023 10:30:11 -0700 Message-Id: <20230323102605.7.I7874c00092115c45377c2a06f7f133356956686e@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org In the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable") we allowed setting "output-disable" for TLMM pinctrl states. Let's also add "output-enable". At first blush this seems a needless thing to do. Specifically: - In Linux (and presumably any other OSes using the same device trees) the GPIO/pinctrl driver knows to automatically enable the output when a GPIO is changed to an output. Thus in most cases specifying "output-enable" is superfluous and should be avoided. - If we need to set a pin's default state we already have "output-high" and "output-low" and these properties already imply "output-enabled" (at least on the Linux Qualcomm TLMM driver). However, there is one instance where "output-enable" seems like it could be useful: sleep states. It's not uncommon to want to configure pins as inputs (with appropriate pulls) when the driver controlling them is in a low power state. Then we want the pins back to outputs when the driver wants things running normally. To accomplish this we'd want to be able to use "output-enable". Then the "default" state could have "output-enable" and the "sleep" state could have "output-disable". NOTE: in all instances I'm aware of, we'd only want to use "output-enable" on pins that are configured as "gpio". The Qualcomm documentation that I have access to says that "output-enable" only does something useful when in GPIO mode. Signed-off-by: Douglas Anderson Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index 5a815c199642..90b7d75840c1 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -77,6 +77,7 @@ $defs: bias-disable: true input-enable: false output-disable: true + output-enable: true output-high: true output-low: true From patchwork Thu Mar 23 17:30:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1AE9C6FD1C for ; Thu, 23 Mar 2023 17:31:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232414AbjCWRbv (ORCPT ); Thu, 23 Mar 2023 13:31:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232438AbjCWRbj (ORCPT ); Thu, 23 Mar 2023 13:31:39 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6380A28E7A for ; Thu, 23 Mar 2023 10:31:28 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id k2so22981015pll.8 for ; Thu, 23 Mar 2023 10:31:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ItXOwha8h+SsgLUIpHMGhHvifqAv9ElkC8GCOIPwlBw=; b=dlcfhiyu360dY4oLMEki5fh68mVrzK1golDy+8Cl/tA1wIHUAz5UypP9RbEfsj/oPz Q192lYMSR1A2uPv9Q7Edridi1TOXxy/UISMuh1Q1qYdm+3okAQFuaxPQ4WJ3XTS9J1fj arFPfu9+Wy9gvejEE21dWL8FGSCl5kOrmFnEE= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592688; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ItXOwha8h+SsgLUIpHMGhHvifqAv9ElkC8GCOIPwlBw=; b=P3ItX+ta97Vj0JSvn2OqWP/1cnGsW3+aEHZDKyjboSMFfXiptxhJh+x83GQEN/V9MI IjTMHwY71/cYtm+qtHTnzVfly+4FYsy6p8zFazZodz/4zpgpei/bjwxASvshHxHHKJiT C2ZjJEN3TegYkq2gAoauThL9DzDGdJEjcsDUGYcIl9uV0HghBFLUsGlJIucYIBH8CvFB U9/vWttsCJnb+FK1Chts9vGn1nKVAglGGpcWFZHCKnqjZM6r9ZRV/jBybspSjAo8TSXN QBWcyJLodFAq3w21rlLnwRh1AI4CfrRNw44hbQt6Va2xUtaBEzW+BS7CP4bFbaaggtva Icrw== X-Gm-Message-State: AO0yUKWfY3iS0+FkoRPrUfgDfTkGHpxlPRoymKZ4n5hIuq5gE2c8fnBf OJeWt5QIPLq03Emarx5b9Js8yg== X-Google-Smtp-Source: AK7set9xgENCrOfo90ZpjRRQSLIrRXwbPcZgC3d88EUdy4NyQal6IFhJCQ1/Qsa1/qHZs38tljQAcQ== X-Received: by 2002:a05:6a20:8b82:b0:d9:7fcf:1076 with SMTP id m2-20020a056a208b8200b000d97fcf1076mr374864pzh.25.1679592687986; Thu, 23 Mar 2023 10:31:27 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:27 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 08/14] pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE Date: Thu, 23 Mar 2023 10:30:12 -0700 Message-Id: <20230323102605.8.Id740ae6a993f9313b58add6b10f6a92795d510d4@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The Qualcomm pinctrl driver has been violating the documented meaning of PIN_CONFIG_INPUT_ENABLE. That documentation says: Note that this does not affect the pin's ability to drive output. ...yet the Qualcomm driver's sole action when asked to "enable input" on a pin is to disable its output. The Qualcomm driver's implementation stems from the fact that "output-disable" is a "new" property from 2017. It was introduced in commit 425562429d4f ("pinctrl: generic: Add output-enable property"). The "input-enable" handling in Qualcomm drivers is from 2015 introduced in commit 407f5e392f9c ("pinctrl: qcom: handle input-enable pinconf property"). Let's change the Qualcomm driver to move us in the right direction. As part of this: 1. We'll now support PIN_CONFIG_OUTPUT_ENABLE 2. We'll still support using PIN_CONFIG_INPUT_ENABLE to disable a pin's output (in violation of the docs) with a big comment in the code. This is needed because old device trees have "input-enable" in them and, in some cases, people might need the old behavior. While we could programmatically change all old device trees, it doesn't really hurt to keep supporting the old behavior and we're _supposed_ to try to be compatible with old device trees anyway. It can also be noted that the PIN_CONFIG_INPUT_ENABLE handling code seems to have purposefully ignored its argument. That means that old boards that had _either_ "input-disable" or "input-enable" in them would have had the effect of disabling a pin's output. While we could change this behavior, since we're only leaving the PIN_CONFIG_INPUT_ENABLE there for backward compatibility we might as well be fully backward compatible. NOTE: despite the fact that we'll still support PIN_CONFIG_INPUT_ENABLE for _setting_ config, we take it away from msm_config_group_get(). This appears to be only used for populating debugfs and fixing debugfs to "output enabled" where relevant instead of "input enabled" makes more sense and has more truthiness. Signed-off-by: Douglas Anderson Reviewed-by: Bjorn Andersson --- drivers/pinctrl/qcom/pinctrl-msm.c | 36 +++++++++++++++++++++++++----- 1 file changed, 31 insertions(+), 5 deletions(-) diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c index daeb79a9a602..4515f375c5e8 100644 --- a/drivers/pinctrl/qcom/pinctrl-msm.c +++ b/drivers/pinctrl/qcom/pinctrl-msm.c @@ -323,6 +323,7 @@ static int msm_config_reg(struct msm_pinctrl *pctrl, break; case PIN_CONFIG_OUTPUT: case PIN_CONFIG_INPUT_ENABLE: + case PIN_CONFIG_OUTPUT_ENABLE: *bit = g->oe_bit; *mask = 1; break; @@ -414,11 +415,9 @@ static int msm_config_group_get(struct pinctrl_dev *pctldev, val = msm_readl_io(pctrl, g); arg = !!(val & BIT(g->in_bit)); break; - case PIN_CONFIG_INPUT_ENABLE: - /* Pin is output */ - if (arg) + case PIN_CONFIG_OUTPUT_ENABLE: + if (!arg) return -EINVAL; - arg = 1; break; default: return -ENOTSUPP; @@ -502,9 +501,36 @@ static int msm_config_group_set(struct pinctrl_dev *pctldev, arg = 1; break; case PIN_CONFIG_INPUT_ENABLE: - /* disable output */ + /* + * According to pinctrl documentation this should + * actually be a no-op. + * + * The docs are explicit that "this does not affect + * the pin's ability to drive output" but what we do + * here is to modify the output enable bit. Thus, to + * follow the docs we should remove that. + * + * The docs say that we should enable any relevant + * input buffer, but TLMM there is no input buffer that + * can be enabled/disabled. It's always on. + * + * The points above, explain why this _should_ be a + * no-op. However, for historical reasons and to + * support old device trees, we'll violate the docs + * still affect the output. + * + * It should further be noted that this old historical + * behavior actually overrides arg to 0. That means + * that "input-enable" and "input-disable" in a device + * tree would _both_ disable the output. We'll + * continue to preserve this behavior as well since + * we have no other use for this attribute. + */ arg = 0; break; + case PIN_CONFIG_OUTPUT_ENABLE: + arg = !!arg; + break; default: dev_err(pctrl->dev, "Unsupported config parameter: %x\n", param); From patchwork Thu Mar 23 17:30:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EB6A1C77B60 for ; Thu, 23 Mar 2023 17:32:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232457AbjCWRb6 (ORCPT ); Thu, 23 Mar 2023 13:31:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45456 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232461AbjCWRbl (ORCPT ); Thu, 23 Mar 2023 13:31:41 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92C082B630 for ; Thu, 23 Mar 2023 10:31:30 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id h12-20020a17090aea8c00b0023d1311fab3so2792861pjz.1 for ; Thu, 23 Mar 2023 10:31:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UzgVWFKkQG0YRgZ5w6TjXBTOfYthe0uzWRC1HMbAqOY=; b=X2o9knEsTKQQzx8gUX7pGP/FjrsVMIhOGp2uKJa+AGe9PxrgzMZdCJqPp5cq0yvbBt l4lRBlXZT14PG0qFzIEQO5xtDafKJHZhf9fTZfMAWHVFQJ932srFyL1blt+2uieb9QTl Nlq1T0lil2SQWsSAEJmaFlXjwl/k55JK9MK38= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592690; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UzgVWFKkQG0YRgZ5w6TjXBTOfYthe0uzWRC1HMbAqOY=; b=5kEci0keGY1EW2BRGwTIkEgyBvLUm6OzGbYjcNkmfQmi93x6qSFW1r9quS5eazUXdj 8IebymmKYdr4i6CUVtlK0REVW+HiMHaiiMA0A68b680eOj0j/4hJ7vsQt8jPD3cAhtIf lhqxKq8ZPdPdRT51eWmriu82PJiTxF5N9WuE25ybN9ong2uUiFfymgKrxZ+ridgiCp2K 4cUwRobUSNCfvB1Y7ObOuAGjJfuubLxmYBtLgnqw8K9xnceZWI4eGg/EaCQxCtT9Vg/1 sIS5roRuImq4fw1G6qr6H71y6969lHWMn+yzpmd2ZN5iAIdNSTRLrzpZNryjjS3o7E0X uiDQ== X-Gm-Message-State: AO0yUKUSi1lKKg1EOlE3Bp+pmfSUgBo2kramhsZvPgh3mSb/3S62j7se oO4HmLmVTPIp60k0FsyyLUp/9A== X-Google-Smtp-Source: AK7set9Kd6/5HOTo2T6ATRK/d1+qZFgR+pYMVOMlgSvhzz9Dwm5JQDFYMgGojvaIfO5hah7gVDlN9A== X-Received: by 2002:a05:6a20:2d99:b0:d5:b3d1:bff9 with SMTP id bf25-20020a056a202d9900b000d5b3d1bff9mr250734pzb.52.1679592689791; Thu, 23 Mar 2023 10:31:29 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:29 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 09/14] arm64: dts: qcom: sc7180: Remove superfluous "input-enable"s from trogdor Date: Thu, 23 Mar 2023 10:30:13 -0700 Message-Id: <20230323102605.9.I94dbc53176e8adb0d7673b7feb2368e85418f938@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at trogdor: * ap_ec_int_l, fp_to_ap_irq_l, h1_ap_int_odl, p_sensor_int_l: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). * bios_flash_wp_l: Superfluous. This pin is exposed to userspace through the kernel's GPIO API and will be configured automatically. That means that in none of the cases for trogdor did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 5 ----- 1 file changed, 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 1f2e1f701761..39100b0c1140 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -1206,7 +1206,6 @@ amp_en: amp-en-state { ap_ec_int_l: ap-ec-int-l-state { pins = "gpio94"; function = "gpio"; - input-enable; bias-pull-up; }; @@ -1229,7 +1228,6 @@ ap_suspend_l_neuter: ap-suspend-l-neuter-state { bios_flash_wp_l: bios-flash-wp-l-state { pins = "gpio66"; function = "gpio"; - input-enable; bias-disable; }; @@ -1271,7 +1269,6 @@ fp_rst_l: fp-rst-l-state { fp_to_ap_irq_l: fp-to-ap-irq-l-state { pins = "gpio4"; function = "gpio"; - input-enable; /* Has external pullup */ bias-disable; @@ -1286,7 +1283,6 @@ fpmcu_boot0: fpmcu-boot0-state { h1_ap_int_odl: h1-ap-int-odl-state { pins = "gpio42"; function = "gpio"; - input-enable; bias-pull-up; }; @@ -1335,7 +1331,6 @@ pen_rst_odl: pen-rst-odl-state { p_sensor_int_l: p-sensor-int-l-state { pins = "gpio24"; function = "gpio"; - input-enable; /* Has external pullup */ bias-disable; From patchwork Thu Mar 23 17:30:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185924 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4AD89C74A5B for ; Thu, 23 Mar 2023 17:32:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232477AbjCWRcH (ORCPT ); Thu, 23 Mar 2023 13:32:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232480AbjCWRbp (ORCPT ); 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Thu, 23 Mar 2023 10:31:31 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 10/14] arm64: dts: qcom: sc7280: Remove superfluous "input-enable"s from idp-ec-h1 Date: Thu, 23 Mar 2023 10:30:14 -0700 Message-Id: <20230323102605.10.I1343c20f4aaac8e2c1918b756f7ed66f6ceace9c@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at the sc7280-idp-ec-h1.dtsi file: * ap_ec_int_l, h1_ap_int_odl: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). That means that in none of the cases for sc7280-idp-ec-h1.dtsi did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi index 3cfeb118d379..ebae545c587c 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp-ec-h1.dtsi @@ -82,14 +82,12 @@ &tlmm { ap_ec_int_l: ap-ec-int-l-state { pins = "gpio18"; function = "gpio"; - input-enable; bias-pull-up; }; h1_ap_int_odl: h1-ap-int-odl-state { pins = "gpio104"; function = "gpio"; - input-enable; bias-pull-up; }; From patchwork Thu Mar 23 17:30:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CAE91C74A5B for ; Thu, 23 Mar 2023 17:32:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232403AbjCWRcS (ORCPT ); Thu, 23 Mar 2023 13:32:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232371AbjCWRbu (ORCPT ); Thu, 23 Mar 2023 13:31:50 -0400 Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B004C28E9F for ; Thu, 23 Mar 2023 10:31:34 -0700 (PDT) Received: by mail-pj1-x102a.google.com with SMTP id p13-20020a17090a284d00b0023d2e945aebso4020989pjf.0 for ; Thu, 23 Mar 2023 10:31:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592693; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=e0GSudvBlA2ChvW+1tK19vXmBXB0gm+MldtIhXHWk80=; b=f8MEMPhDfzoFegAhp/wfBqbHVIsGQ736bOmKQD+YQO8hYiVarK1C43+BZhyvyHDqb2 qygRDuX5MFaxcnB+jTX/PyrCbyk3gwQ0pCf4mCgXPd54jUhyzslyhuPnUX3NjxMNenuD Vf4bdDfS4YeAdxNX5bBueM8Yuj7TfCR5AR4zM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592693; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=e0GSudvBlA2ChvW+1tK19vXmBXB0gm+MldtIhXHWk80=; b=aJevUFPPXFtpBAhgJCdVsmuU59b6ycs1KizVLqhDAIA4afFjG1r6tJXUtNoQzTL1tm SjcRpBsOuOe6uaqy+BJKlIp78Kn9czBWuOjLdrwWdfJG/fSSjTj4Lzpz9xQKIfhHVAYC fh2KRvO8MVJAAy+OkXi22Xz3JgPIBK6XXisiIIc3GW+/zRogsOtCr0yMD4boaOjitOt5 di2YTakY0u/mdahXuLEsNNgZl/TZCnL/YkczKYWameWSEYlNJM1Fj+YhSki/lDjzqivr zypklSh4kUbw1kz4gyUoeK1o9Be+AkGiTvAua+ax23XzpXG8/RoQMwFujYxtCqx12/+F yJAg== X-Gm-Message-State: AO0yUKWqIamuh4yCh7tn7mooraMjoYjVOi3HzjQfGYI/shPikGrBtlcA 5bfQ6DorAEYBfkmL2/w4sr/ogQ== X-Google-Smtp-Source: AK7set97Q7ByztaZI4dKAUikIP7l4jBgCdFB7n6RsJvEpYOdNT3MUl2aWbhj4bw3DASCvj3xaFJ0tg== X-Received: by 2002:a05:6a20:718a:b0:d9:a792:8e3d with SMTP id s10-20020a056a20718a00b000d9a7928e3dmr349987pzb.30.1679592693514; Thu, 23 Mar 2023 10:31:33 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:32 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 11/14] arm64: dts: qcom: sdm845: Remove superfluous "input-enable"s from cheza Date: Thu, 23 Mar 2023 10:30:15 -0700 Message-Id: <20230323102605.11.Ia439c29517b1c0625325a54387b047f099d16425@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org As talked about in the patch ("dt-bindings: pinctrl: qcom: tlmm should use output-disable, not input-enable"), using "input-enable" in pinctrl states for Qualcomm TLMM pinctrl devices was either superfluous or there to disable a pin's output. Looking at cheza * ec_ap_int_l, h1_ap_int_odl: Superfluous. The pins will be configured as inputs automatically by the Linux GPIO subsystem (presumably the reference for other OSes using these device trees). * bios_flash_wp_l: Superfluous. This pin is exposed to userspace through the kernel's GPIO API and will be configured automatically. That means that in none of the cases for cheza did we need to change "input-enable" to "output-disable" and we can just remove these superfluous properties. Signed-off-by: Douglas Anderson --- arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 3 --- 1 file changed, 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index f2b48241d15c..588165ee74b3 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -1155,14 +1155,12 @@ ap_edp_bklten: ap-edp-bklten-state { bios_flash_wp_r_l: bios-flash-wp-r-l-state { pins = "gpio128"; function = "gpio"; - input-enable; bias-disable; }; ec_ap_int_l: ec-ap-int-l-state { pins = "gpio122"; function = "gpio"; - input-enable; bias-pull-up; }; @@ -1190,7 +1188,6 @@ en_pp3300_dx_edp: en-pp3300-dx-edp-state { h1_ap_int_odl: h1-ap-int-odl-state { pins = "gpio129"; function = "gpio"; - input-enable; bias-pull-up; }; From patchwork Thu Mar 23 17:30:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185926 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2AAF0C6FD1C for ; Thu, 23 Mar 2023 17:32:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232460AbjCWRcd (ORCPT ); Thu, 23 Mar 2023 13:32:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44000 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232320AbjCWRcD (ORCPT ); Thu, 23 Mar 2023 13:32:03 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A740D360AD for ; Thu, 23 Mar 2023 10:31:37 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id p13-20020a17090a284d00b0023d2e945aebso4021036pjf.0 for ; Thu, 23 Mar 2023 10:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592695; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=j6LXKCEb3/BINodw1aD0uX0Oh1YqBoNeM7/LB28/UeE=; b=NK9khFXdbhd8AKbccKVwlYyqpaZSoBXNzGIi3sVGUjFITXPQheAzihAZfIYb9p+oxb XUEpywwYq0mqN5UgRT4jN3CL+nDWq1ly1yWETTmghx9I7R6rh1PuH7RfMF66fg37AzoU FDVkOPpzOxlYJBbqQ9zCj6qxz0ADFmmhi3w5o= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592695; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=j6LXKCEb3/BINodw1aD0uX0Oh1YqBoNeM7/LB28/UeE=; b=cIYKM+mdxuLwKS8BDhUpYWpdFykPtjCMtHwJbMURaKu0erkowOvhSuuRAtPpO7LGhF vOoIAnDopFEcHAmSY6x2yZysw4PMbf7N0/Lk+PfQv12vv7SGwNq7PsQcUmGtgnwONyvc K0Duu84u66y1JZ4iDEDlSDhygvQZL1vfuNHdnoTJWVvX72X3WlwMB1ECDXEz3xcl3tUp Is+6oDLDwOjUO4rtFswV4EFiZK7dYgjnqomrWsEDRKy69+g99vCBfQOmQ8bltCKHCpG8 AVIVrDFqxiQZZP9koqpF4rVesDjIG4vTJgu9NDZFuVC1ImjspyACzkUFGmnDDI/XK11a t/VA== X-Gm-Message-State: AO0yUKXx0tIxMRCNt538sRYeE3I9g84KlCEE+56AMfz+5JRPhktMVGQq x/udclLuzn5+FXKJh/FDYB82gw== X-Google-Smtp-Source: AK7set8eHb9MWIbayLU4pYFk+mcrLE3Fp8YxxyVR5lvyiNfDfEC1S4tIYQcJryxp4TjSbPKIz4IrPA== X-Received: by 2002:a05:6a20:8b83:b0:da:5ab7:8ce9 with SMTP id m3-20020a056a208b8300b000da5ab78ce9mr271523pzh.22.1679592695237; Thu, 23 Mar 2023 10:31:35 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:34 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 12/14] arm64: dts: qcom: sc7180: Fix trogdor qspi pin config Date: Thu, 23 Mar 2023 10:30:16 -0700 Message-Id: <20230323102605.12.I6f03f86546e6ce9abb1d24fd9ece663c3a5b950c@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org In commit 7ec3e67307f8 ("arm64: dts: qcom: sc7180-trogdor: add initial trogdor and lazor dt") we specified the pull settings on the boot SPI (the qspi) data lines as pullups to "park" the lines. This seemed like the right thing to do, but I never really probed the lines to confirm. Since that time, I've done A LOT of research, experiements and poking of the lines with a voltmeter. A first batch of discoveries: - There is an external pullup on CS (clearly shown on schematics) - There are weak external pulldowns on CLK/MOSI (believed to be Cr50's internal pulldowns) - There is no pull on MISO. - When qspi isn't actively transferring it still drives CS, CLK, and MOSI. CS and MOSI are driven high and CLK is driven low. It does not drive MISO and (if no internal pulls are enabled) the line floats. The above means that it's good to have some sort of pull on MISO, at the very least. The pullup that we had before was actually fine (and my voltmeter confirms that it actually affected the state of the pin) but a pulldown would work equally well (and would match MOSI and CLK better). The above also means that we could save a tiny bit of power (not measurable by my setup) by setting up a sleep state for these pins. If nothing else this prevents us from driving high against Cr50's internal pulldown on MOSI. However, Qualcomm has also asserted in the past that it burns a little extra power to drive a pin, especially since these are configured with a slightly higher drive strength Let's fix all this. Since the external pulls are different for the two data lines, we'll split them into separate configs. Then we'll change the MISO pin to a pulldown and add a sleep state. On a slightly tangental (but not totally unrelated note), I also discovered some interesting things with these pins in suspend. First, I found that if we don't switch the pins to GPIO that the qspi peripheral continues to drive them in suspend. That'll be solved by what we're already doing above. Second, I found that something in the system suspend path (after Linux stops running) reconfigures these pins so that they don't have their normal pulls enabled but instead change to "keepers" (bias-bus-hold in DT speak). If a pin was floating before we entered suspend then it would stop floating. I found that I could manually pull a pin to a different level and then probe it and it would stay there. This is exactly keeper behavior. With the solution we have the switch to "keeper" doesn't matter too much but it's good to document. While talking about "keepers", it can also be noted that I found that the "keepers" on these pins were at least enough to win a fight against Cr50's internal pulls. That means it's best to make sure that the state of the pins are already correct before the mysterious transition to a keeper. Otherwise we'll burn (a small amount of) power in S3 via this fight. Luckily with the current solution we don't hit this case. NOTE: I've left "sc7180-idp" behavior totally alone in this patch. I didn't add a sleep state and I didn't change any pulls--I just adapted it to the fact that the data lines have separate configs. Qualcomm doesn't provide me with schematics for IDP and thus I don't actually know how the pulls are configured. Since this is just a development platform and worked well enough, it seems safer to leave it alone. Dependencies: - This patch has a hard dependency on ("pinctrl: qcom: Support OUTPUT_ENABLE; deprecate INPUT_ENABLE"). Something in the boot code seemed to have been confused and thought it needed to set the "OUTPUT ENABLE" bit for these pins even though it was using them as SPI. Thus if we don't honor the "output-disable" property we could end up driving the SPI pins while in sleep mode. - In general, it's probably best not to backport this to a kernel that doesn't have commit d21f4b7ffc22 ("pinctrl: qcom: Avoid glitching lines when we first mux to output"). That landed a while ago, but it's still good to be explicit in case someone was backporting. If we don't have that then there might be a glitch when we first switch over to GPIO before we disable the output. - This patch _doesn't_ really have any dependency on the qspi driver patch that supports setting the pinctrl sleep state--they can go in either order. If we define the sleep state and the driver never selects it that's fine. If the driver tries to select a sleep state that we don't define that's fine. Signed-off-by: Douglas Anderson --- v1 of this patch was ("arm64: dts: qcom: sc7180: Fix trogdor qspi pull direction") [1]. Since then, I've spent time running experiments where I tried lots of different combinations and then probed the GPIOs with a multimeter to figure out what's happening. As a result, it's now at the end of a somewhat larger series. I should note that I've removed the "Fixes" tag of this patch. While it still technically does "fix" the old behavior, the old behavior really wasn't terrible (a miniscule amount of extra power draw). It's probably not worth the risk that adding "Fixes" will cause it to get backported without the pinctrl support (see "Dependencies" in the patch description). [1] https://lore.kernel.org/r/20230213165743.1.I6f03f86546e6ce9abb1d24fd9ece663c3a5b950c@changeid arch/arm64/boot/dts/qcom/sc7180-idp.dts | 9 ++++-- arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi | 34 ++++++++++++++++---- arch/arm64/boot/dts/qcom/sc7180.dtsi | 9 ++++-- 3 files changed, 40 insertions(+), 12 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7180-idp.dts b/arch/arm64/boot/dts/qcom/sc7180-idp.dts index c3bdd3295c02..44c27b4eac45 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-idp.dts +++ b/arch/arm64/boot/dts/qcom/sc7180-idp.dts @@ -354,7 +354,7 @@ &qfprom { &qspi { status = "okay"; pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; flash@0 { compatible = "jedec,spi-nor"; @@ -512,8 +512,11 @@ &qspi_cs0 { bias-disable; }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ +&qspi_data0 { + bias-pull-up; +}; + +&qspi_data1 { bias-pull-up; }; diff --git a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi index 39100b0c1140..ca6920de7ea8 100644 --- a/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180-trogdor.dtsi @@ -424,8 +424,9 @@ &qfprom { &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; + pinctrl-1 = <&qspi_sleep>; flash@0 { compatible = "jedec,spi-nor"; @@ -1046,17 +1047,20 @@ &pri_mi2s_mclk_active { }; &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ }; &qspi_clk { drive-strength = <8>; - bias-disable; + bias-disable; /* Rely on Cr50 internal pulldown */ }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-disable; /* Rely on Cr50 internal pulldown */ +}; + +&qspi_data1 { + bias-pull-down; }; &qup_i2c2_default { @@ -1336,6 +1340,22 @@ p_sensor_int_l: p-sensor-int-l-state { bias-disable; }; + qspi_sleep: qspi-sleep-state { + pins = "gpio63", "gpio64", "gpio65", "gpio68"; + + /* + * When we're not actively transferring we want pins as GPIOs + * with output disabled so that the quad SPI IP block stops + * driving them. We rely on the normal pulls configured in + * the active state and don't redefine them here. Also note + * that we don't need the reverse (output-enable) in the + * normal mode since the "output-enable" only matters for + * GPIO function. + */ + function = "gpio"; + output-disable; + }; + qup_uart3_sleep: qup-uart3-sleep-state { cts-pins { /* diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi index fe62ce516c4e..b2fcf0b58722 100644 --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi @@ -1535,8 +1535,13 @@ qspi_cs1: qspi-cs1-state { function = "qspi_cs"; }; - qspi_data01: qspi-data01-state { - pins = "gpio64", "gpio65"; + qspi_data0: qspi-data0-state { + pins = "gpio64"; + function = "qspi_data"; + }; + + qspi_data1: qspi-data1-state { + pins = "gpio65"; function = "qspi_data"; }; From patchwork Thu Mar 23 17:30:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185927 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 241A4C761AF for ; Thu, 23 Mar 2023 17:32:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232598AbjCWRci (ORCPT ); Thu, 23 Mar 2023 13:32:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232480AbjCWRcJ (ORCPT ); Thu, 23 Mar 2023 13:32:09 -0400 Received: from mail-pg1-x52d.google.com (mail-pg1-x52d.google.com [IPv6:2607:f8b0:4864:20::52d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 529B238442 for ; Thu, 23 Mar 2023 10:31:39 -0700 (PDT) Received: by mail-pg1-x52d.google.com with SMTP id y35so11855236pgl.4 for ; Thu, 23 Mar 2023 10:31:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1679592698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wRxHjat8O8FYtA1vS1Ehqi9VaQ+n7ssLGElmobuUyNk=; b=U+4DEso+L/0m/PFXzT7CZpH9N8N0qk37EIGBUM9bYOrsWMIBtlO2tOyJBPL29QQwV4 GJhQjcoCRMUsexIHCQ/f996IhXXdiUupT4oHps+65XZzI28Yo9q9VrTbsycdovu6fpKs mujXI+2Hz+scgy06KyIdr+3MPES2iK719bDgk= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679592698; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wRxHjat8O8FYtA1vS1Ehqi9VaQ+n7ssLGElmobuUyNk=; b=I1qrTs9kKbtmEvKJXXr+F3tjn2WSSsTWB5tsOwifi/531DKLOJKi+CIu9jjWRB1zaq ocIGbk7fMtBGIG5wsK2MWYkAxdvFesq2W5zdIZfl1glFabi0n9zYHsRnEELHIjBdvbXD 5Uc1ZbQ5iceB/rXQC7FeFDDFWtaiUeb/Cs8zAUccyb91tcfKswlNnnbXhk24kTzvOQPg xDokyogOb6HhGT2wWKVv3G0kUIKFGEI7M4TOqDVN8monTD7u25LYlUKF3FG0rBHOTs48 qfuHdnHnXx7QImqfLqzL/VsrqhvOuiReRdLLiAkqflcgol/g0+Wjld5FD7atkKz7pwoR u+9A== X-Gm-Message-State: AAQBX9eVSJrRoDCJanqCTZFbHUL++AA2082COH2o+wL9yP06UUNysqTQ eDkiFkTxRWxJj8b0mggFX5Qa9g== X-Google-Smtp-Source: AKy350Y9uI++VGMZHk8Z3V/GCLI2m4BsnZwP4JxPB7sf6iJ3SVpjUx00AyoX5UWoTsvS+s5PYYvTWw== X-Received: by 2002:a62:18c4:0:b0:619:53de:8880 with SMTP id 187-20020a6218c4000000b0061953de8880mr187692pfy.16.1679592697823; Thu, 23 Mar 2023 10:31:37 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:36 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 13/14] arm64: dts: qcom: sc7280: Fix qspi pin config Date: Thu, 23 Mar 2023 10:30:17 -0700 Message-Id: <20230323102605.13.Ib44c3e417c414a4227db8def75ded37ad368212c@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Similar to sc7180 (see the patch ("arm64: dts: qcom: sc7180: Fix trogdor qspi pin config")), we should adjust the qspi pin config for sc7280. I won't re-describe all the research/arguments in the sc7180 patch here, but there are a few differences for sc7280 worth noting: 1. On herobrine the SPI flash (qspi) is wired up differently on the board. Rather than Cr50 and the AP being wired directly together, there's actually a mux that will _either_ connect the AP to the flash or Cr50 to the flash. This means that the internal pulls on Cr50 don't affect us and we should enable our own pulldowns. 2. On herobrine, EEs added an external pulldown on the MISO line. The argument in the schematic said that we added it (but not one on MOSI and CLK) because Cr50 already enabled pulldowns on MOSI and CLK. ...though, as per #1, those Cr50 pulldowns would only affect the line when the mux was swung to Cr50. The ironic result of #1 and #2 is that the external pulldowns on CLK/MISO/MOSI on herobrine are _exactly opposite_ of the ones on trogdor. 3. While I still don't have the actual exact schematics for all variants of IDP/CRD that were produced, I have some reference schematics that give me a belief of how the qspi is hooked up there. From this, I'm fairly certain that all of the older variants of IDP/CRD either have a pulldown on the CLK/MOSI/MISO lines (maybe through a direct connect to Cr50) or have no pull (in other words, they don't have a pullup). I'll go ahead and enable internal pulldowns on all the lines since that won't hurt to double-pull if there's an external pulldown and it's nice to have a pulldown if there's nothing external. Note that this only affects _older_ CRDs. Newer revs are considered "herobrine" (see the hoglin/zoglin device trees). 4. I didn't find the same strange "auto-switch-to-keeper" at suspend when probing on sc7280. Whatever pulls (or lack thereof) I left at suspend time seemed to persist into suspend. Signed-off-by: Douglas Anderson --- .../boot/dts/qcom/sc7280-chrome-common.dtsi | 25 +++++++++++++++++-- .../arm64/boot/dts/qcom/sc7280-herobrine.dtsi | 14 +++++++---- arch/arm64/boot/dts/qcom/sc7280-idp.dtsi | 13 ++++++---- arch/arm64/boot/dts/qcom/sc7280.dtsi | 9 +++++-- 4 files changed, 47 insertions(+), 14 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi index 16fb20369c01..f562e4d2b655 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-chrome-common.dtsi @@ -60,8 +60,9 @@ &pmk8350_pon { */ &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; + pinctrl-1 = <&qspi_sleep>; spi_flash: flash@0 { compatible = "jedec,spi-nor"; @@ -85,3 +86,23 @@ wifi-firmware { iommus = <&apps_smmu 0x1c02 0x1>; }; }; + +/* PINCTRL - chrome-common pinctrl */ + +&tlmm { + qspi_sleep: qspi-sleep-state { + pins = "gpio12", "gpio13", "gpio14", "gpio15"; + + /* + * When we're not actively transferring we want pins as GPIOs + * with output disabled so that the quad SPI IP block stops + * driving them. We rely on the normal pulls configured in + * the active state and don't redefine them here. Also note + * that we don't need the reverse (output-enable) in the + * normal mode since the "output-enable" only matters for + * GPIO function. + */ + function = "gpio"; + output-disable; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi index b6137816f2f3..e651f633341f 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-herobrine.dtsi @@ -692,18 +692,22 @@ &pcie1_clkreq_n { }; &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ drive-strength = <8>; }; &qspi_clk { - bias-disable; + bias-pull-down; /* No external pulls */ drive-strength = <8>; }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-pull-down; /* No external pulls */ + drive-strength = <8>; +}; + +&qspi_data1 { + bias-disable; /* External pulldown */ drive-strength = <8>; }; diff --git a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi index 8b5293e7fd2a..6aaa77abc00b 100644 --- a/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280-idp.dtsi @@ -636,16 +636,19 @@ &pcie1_clkreq_n { }; &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ }; &qspi_clk { - bias-disable; + bias-pull-down; /* No external pulls or external pulldown */ }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-pull-down; /* No external pulls or external pulldown */ +}; + +&qspi_data1 { + bias-pull-down; /* No external pulls or external pulldown */ }; &qup_uart5_tx { diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 71e2e51c7c7f..b98994cc8616 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4337,8 +4337,13 @@ qspi_cs1: qspi-cs1-state { function = "qspi_cs"; }; - qspi_data01: qspi-data01-state { - pins = "gpio12", "gpio13"; + qspi_data0: qspi-data0-state { + pins = "gpio12"; + function = "qspi_data"; + }; + + qspi_data1: qspi-data1-state { + pins = "gpio13"; function = "qspi_data"; }; From patchwork Thu Mar 23 17:30:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 13185928 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05E66C6FD1C for ; Thu, 23 Mar 2023 17:32:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232605AbjCWRcq (ORCPT ); Thu, 23 Mar 2023 13:32:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46018 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232402AbjCWRcR (ORCPT ); Thu, 23 Mar 2023 13:32:17 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 200D13844A for ; Thu, 23 Mar 2023 10:31:41 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id dw14so8335180pfb.6 for ; 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Thu, 23 Mar 2023 10:31:39 -0700 (PDT) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16d3:ef20:206a:6521]) by smtp.gmail.com with ESMTPSA id x13-20020a62fb0d000000b0061a6f4c1b2bsm12613546pfm.171.2023.03.23.10.31.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 10:31:39 -0700 (PDT) From: Douglas Anderson To: Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , Mark Brown , Linus Walleij Cc: Matthias Kaehlcke , Konrad Dybcio , linux-gpio@vger.kernel.org, Stephen Boyd , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, Douglas Anderson , Andy Gross , linux-kernel@vger.kernel.org Subject: [PATCH 14/14] arm64: dts: qcom: sdm845: Fix cheza qspi pin config Date: Thu, 23 Mar 2023 10:30:18 -0700 Message-Id: <20230323102605.14.I82951106ab8170f973a4c1c7d9b034655bbe2f60@changeid> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog In-Reply-To: <20230323173019.3706069-1-dianders@chromium.org> References: <20230323173019.3706069-1-dianders@chromium.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Cheza's SPI flash hookups (qspi) are exactly the same as trogdor's. Apply the same solution that's described in the patch ("arm64: dts: qcom: sc7180: Fix trogdor qspi pin config") Signed-off-by: Douglas Anderson --- I think cheza is only very lightly used today (it was never sold, but there are various people still using the dev boards) and I'm not personally setup to test this. It's fairly straightforward but has only been compile-tested. arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi | 34 +++++++++++++++++----- arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 ++++-- 2 files changed, 34 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi index 588165ee74b3..64ad8d1ed433 100644 --- a/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845-cheza.dtsi @@ -319,8 +319,9 @@ venus_mem: memory@96000000 { &qspi { status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&qspi_clk>, <&qspi_cs0>, <&qspi_data0>, <&qspi_data1>; + pinctrl-1 = <&qspi_sleep>; flash@0 { compatible = "jedec,spi-nor"; @@ -995,16 +996,19 @@ &wifi { /* PINCTRL - additions to nodes defined in sdm845.dtsi */ &qspi_cs0 { - bias-disable; + bias-disable; /* External pullup */ }; &qspi_clk { - bias-disable; + bias-disable; /* Rely on Cr50 internal pulldown */ }; -&qspi_data01 { - /* High-Z when no transfers; nice to park the lines */ - bias-pull-up; +&qspi_data0 { + bias-disable; /* Rely on Cr50 internal pulldown */ +}; + +&qspi_data1 { + bias-pull-down; }; &qup_i2c3_default { @@ -1233,6 +1237,22 @@ pen_rst_l: pen-rst-l-state { output-high; }; + qspi_sleep: qspi-sleep-state { + pins = "gpio90", "gpio91", "gpio92", "gpio95"; + + /* + * When we're not actively transferring we want pins as GPIOs + * with output disabled so that the quad SPI IP block stops + * driving them. We rely on the normal pulls configured in + * the active state and don't redefine them here. Also note + * that we don't need the reverse (output-enable) in the + * normal mode since the "output-enable" only matters for + * GPIO function. + */ + function = "gpio"; + output-disable; + }; + sdc2_clk: sdc2-clk-state { pins = "sdc2_clk"; bias-disable; diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index aafc7cc7edd8..dce2cb29347b 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -2758,8 +2758,13 @@ qspi_cs1: qspi-cs1-state { function = "qspi_cs"; }; - qspi_data01: qspi-data01-state { - pins = "gpio91", "gpio92"; + qspi_data0: qspi-data0-state { + pins = "gpio91"; + function = "qspi_data"; + }; + + qspi_data1: qspi-data1-state { + pins = "gpio92"; function = "qspi_data"; };