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Thu, 23 Mar 2023 21:38:26 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT054.mail.protection.outlook.com (10.13.173.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6222.22 via Frontend Transport; Thu, 23 Mar 2023 21:38:26 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 23 Mar 2023 16:38:25 -0500 From: Terry Bowman To: , , , , , , , , , CC: , Subject: [PATCH v2 1/5] cxl/pci: Add RCH downstream port AER and RAS register discovery Date: Thu, 23 Mar 2023 16:38:04 -0500 Message-ID: <20230323213808.398039-2-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323213808.398039-1-terry.bowman@amd.com> References: <20230323213808.398039-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT054:EE_|SJ0PR12MB5455:EE_ X-MS-Office365-Filtering-Correlation-Id: de8a8f64-3268-4509-aacf-08db2be6ef7d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 21:38:26.2738 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: de8a8f64-3268-4509-aacf-08db2be6ef7d X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT054.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5455 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org Restricted CXL host (RCH) downstream port AER information is not currently logged while in the error state. One problem preventing existing PCIe AER functions from logging errors is the AER registers are not accessible. The CXL driver requires changes to find RCH downstream port AER registers for purpose of error logging. RCH downstream ports are not enumerated during a PCI bus scan and are instead discovered using system firmware, ACPI in this case.[1] The downstream port is implemented as a Root Complex Register Block (RCRB). The RCRB is a 4k memory block containing PCIe registers based on the PCIe root port.[2] The RCRB includes AER extended capability registers used for reporting errors. Note, the RCH's AER Capability is located in the RCRB memory space instead of PCI configuration space, thus its register access is different. Existing kernel PCIe AER functions can not be used to manage the downstream port AER capabilities because the port was not enumerated during PCI scan and the registers are not PCI config accessible. Discover RCH downstream port AER extended capability registers. This requires using MMIO accesses to search for extended AER capability in RCRB register space. [1] CXL 3.0 Spec, 9.11.2 - System Firmware View of CXL 1.1 Hierarchy [2] CXL 3.0 Spec, 8.2.1.1 - RCH Downstream Port RCRB Co-developed-by: Robert Richter Signed-off-by: Robert Richter Signed-off-by: Terry Bowman --- drivers/cxl/core/regs.c | 93 +++++++++++++++++++++++++++++++++++------ drivers/cxl/cxl.h | 5 +++ drivers/cxl/mem.c | 41 ++++++++++++------ 3 files changed, 115 insertions(+), 24 deletions(-) diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 1476a0299c9b..108a349d8101 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -332,10 +332,36 @@ int cxl_find_regblock(struct pci_dev *pdev, enum cxl_regloc_type type, } EXPORT_SYMBOL_NS_GPL(cxl_find_regblock, CXL); +static void __iomem *cxl_map_reg(struct device *dev, struct cxl_register_map *map, + char *name) +{ + + if (!request_mem_region(map->resource, map->max_size, name)) + return 0; + + map->base = ioremap(map->resource, map->max_size); + if (!map->base) { + release_mem_region(map->resource, map->max_size); + return 0; + } + + return map->base; +} + +static void cxl_unmap_reg(struct device *dev, struct cxl_register_map *map) +{ + iounmap(map->base); + release_mem_region(map->resource, map->max_size); +} + resource_size_t cxl_rcrb_to_component(struct device *dev, resource_size_t rcrb, enum cxl_rcrb which) { + struct cxl_register_map map = { + .resource = rcrb, + .max_size = SZ_4K + }; resource_size_t component_reg_phys; void __iomem *addr; u32 bar0, bar1; @@ -343,7 +369,10 @@ resource_size_t cxl_rcrb_to_component(struct device *dev, u32 id; if (which == CXL_RCRB_UPSTREAM) - rcrb += SZ_4K; + map.resource += SZ_4K; + + if (!cxl_map_reg(dev, &map, "CXL RCRB")) + return CXL_RESOURCE_NONE; /* * RCRB's BAR[0..1] point to component block containing CXL @@ -351,21 +380,12 @@ resource_size_t cxl_rcrb_to_component(struct device *dev, * the PCI Base spec here, esp. 64 bit extraction and memory * ranges alignment (6.0, 7.5.1.2.1). */ - if (!request_mem_region(rcrb, SZ_4K, "CXL RCRB")) - return CXL_RESOURCE_NONE; - addr = ioremap(rcrb, SZ_4K); - if (!addr) { - dev_err(dev, "Failed to map region %pr\n", addr); - release_mem_region(rcrb, SZ_4K); - return CXL_RESOURCE_NONE; - } - + addr = map.base; id = readl(addr + PCI_VENDOR_ID); cmd = readw(addr + PCI_COMMAND); bar0 = readl(addr + PCI_BASE_ADDRESS_0); bar1 = readl(addr + PCI_BASE_ADDRESS_1); - iounmap(addr); - release_mem_region(rcrb, SZ_4K); + cxl_unmap_reg(dev, &map); /* * Sanity check, see CXL 3.0 Figure 9-8 CXL Device that Does Not @@ -396,3 +416,52 @@ resource_size_t cxl_rcrb_to_component(struct device *dev, return component_reg_phys; } EXPORT_SYMBOL_NS_GPL(cxl_rcrb_to_component, CXL); + +u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb) +{ + struct cxl_register_map map = { + .resource = rcrb, + .max_size = SZ_4K, + }; + u32 cap_hdr; + u16 offset = 0; + + if (!cxl_map_reg(dev, &map, "CXL RCRB")) + return 0; + + cap_hdr = readl(map.base + offset); + while (PCI_EXT_CAP_ID(cap_hdr) != PCI_EXT_CAP_ID_ERR) { + + offset = PCI_EXT_CAP_NEXT(cap_hdr); + if (!offset) { + cxl_unmap_reg(dev, &map); + return 0; + } + cap_hdr = readl(map.base + offset); + } + + dev_dbg(dev, "found AER extended capability (0x%x)\n", offset); + cxl_unmap_reg(dev, &map); + + return offset; +} +EXPORT_SYMBOL_NS_GPL(cxl_rcrb_to_aer, CXL); + +u16 cxl_component_to_ras(struct device *dev, resource_size_t component_reg_phys) +{ + struct cxl_register_map map = { + .resource = component_reg_phys, + .max_size = CXL_COMPONENT_REG_BLOCK_SIZE, + }; + + if (!cxl_map_reg(dev, &map, "component")) + return 0; + + cxl_probe_component_regs(dev, map.base, &map.component_map); + cxl_unmap_reg(dev, &map); + if (!map.component_map.ras.valid) + return 0; + + return map.component_map.ras.offset; +} +EXPORT_SYMBOL_NS_GPL(cxl_component_to_ras, CXL); diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index d853a0238ad7..9fd7df48ce99 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -270,6 +270,9 @@ enum cxl_rcrb { resource_size_t cxl_rcrb_to_component(struct device *dev, resource_size_t rcrb, enum cxl_rcrb which); +u16 cxl_rcrb_to_aer(struct device *dev, resource_size_t rcrb); +u16 cxl_component_to_ras(struct device *dev, + resource_size_t component_reg_phys); #define CXL_RESOURCE_NONE ((resource_size_t) -1) #define CXL_TARGET_STRLEN 20 @@ -601,6 +604,8 @@ struct cxl_dport { int port_id; resource_size_t component_reg_phys; resource_size_t rcrb; + u16 aer_cap; + u16 ras_cap; bool rch; struct cxl_port *port; }; diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 39c4b54f0715..12e8e8ebaac0 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -45,13 +45,38 @@ static int cxl_mem_dpa_show(struct seq_file *file, void *data) return 0; } +static void cxl_rcrb_setup(struct cxl_dev_state *cxlds, + struct cxl_dport *parent_dport) +{ + struct cxl_memdev *cxlmd = cxlds->cxlmd; + + if (!parent_dport->rch) + return; + + /* + * The component registers for an RCD might come from the + * host-bridge RCRB if they are not already mapped via the + * typical register locator mechanism. + */ + if (cxlds->component_reg_phys == CXL_RESOURCE_NONE) + cxlds->component_reg_phys = cxl_rcrb_to_component( + &cxlmd->dev, parent_dport->rcrb, CXL_RCRB_UPSTREAM); + + /* RCH AER is required. CXL3.0 Spec Table 8-12 */ + parent_dport->aer_cap = cxl_rcrb_to_aer(parent_dport->dport, + parent_dport->rcrb); + + /* RCH RAS is required. CXL3.0 Spec Table 8-22 */ + parent_dport->ras_cap = cxl_component_to_ras(parent_dport->dport, + parent_dport->component_reg_phys); +} + static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, struct cxl_dport *parent_dport) { struct cxl_port *parent_port = parent_dport->port; struct cxl_dev_state *cxlds = cxlmd->cxlds; struct cxl_port *endpoint, *iter, *down; - resource_size_t component_reg_phys; int rc; /* @@ -66,17 +91,9 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, ep->next = down; } - /* - * The component registers for an RCD might come from the - * host-bridge RCRB if they are not already mapped via the - * typical register locator mechanism. - */ - if (parent_dport->rch && cxlds->component_reg_phys == CXL_RESOURCE_NONE) - component_reg_phys = cxl_rcrb_to_component( - &cxlmd->dev, parent_dport->rcrb, CXL_RCRB_UPSTREAM); - else - component_reg_phys = cxlds->component_reg_phys; - endpoint = devm_cxl_add_port(host, &cxlmd->dev, component_reg_phys, + cxl_rcrb_setup(cxlds, parent_dport); + + endpoint = devm_cxl_add_port(host, &cxlmd->dev, cxlds->component_reg_phys, parent_dport); if (IS_ERR(endpoint)) return PTR_ERR(endpoint); From patchwork Thu Mar 23 21:38:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13186108 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FDB0C6FD1C for ; Thu, 23 Mar 2023 21:38:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231320AbjCWViu (ORCPT ); Thu, 23 Mar 2023 17:38:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231307AbjCWVis (ORCPT ); Thu, 23 Mar 2023 17:38:48 -0400 Received: from NAM11-CO1-obe.outbound.protection.outlook.com (mail-co1nam11on2050.outbound.protection.outlook.com [40.107.220.50]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3AD51DBBC; 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Thu, 23 Mar 2023 21:38:37 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT081.mail.protection.outlook.com (10.13.172.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6222.17 via Frontend Transport; Thu, 23 Mar 2023 21:38:37 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 23 Mar 2023 16:38:36 -0500 From: Terry Bowman To: , , , , , , , , , CC: , Subject: [PATCH v2 2/5] efi/cper: Export cper_mem_err_unpack() for CXL logging Date: Thu, 23 Mar 2023 16:38:05 -0500 Message-ID: <20230323213808.398039-3-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323213808.398039-1-terry.bowman@amd.com> References: <20230323213808.398039-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT081:EE_|LV2PR12MB5966:EE_ X-MS-Office365-Filtering-Correlation-Id: c9428e2d-00bb-4faf-62eb-08db2be6f5f9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 21:38:37.1510 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c9428e2d-00bb-4faf-62eb-08db2be6f5f9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT081.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5966 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The CXL driver plans to use cper_print_aer() for restricted CXL host (RCH) logging. This is not currently possible because CXL is a loadable module and cper_print_aer() depends on cper_mem_err_unpack() which is not exported. Export cper_mem_err_unpack() to enable cper_print_aer() usage in CXL and other loadable modules. Signed-off-by: Terry Bowman Cc: Ard Biesheuvel Cc: linux-efi@vger.kernel.org --- drivers/firmware/efi/cper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/firmware/efi/cper.c b/drivers/firmware/efi/cper.c index 35c37f667781..ff15e12160ae 100644 --- a/drivers/firmware/efi/cper.c +++ b/drivers/firmware/efi/cper.c @@ -350,6 +350,7 @@ const char *cper_mem_err_unpack(struct trace_seq *p, return ret; } +EXPORT_SYMBOL_GPL(cper_mem_err_unpack); static void cper_print_mem(const char *pfx, const struct cper_sec_mem_err *mem, int len) From patchwork Thu Mar 23 21:38:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13186109 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 666E9C761AF for ; Thu, 23 Mar 2023 21:39:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231364AbjCWVjK (ORCPT ); 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Thu, 23 Mar 2023 16:38:47 -0500 From: Terry Bowman To: , , , , , , , , , CC: , Subject: [PATCH v2 3/5] pci/aer: Export cper_print_aer() for CXL driver logging Date: Thu, 23 Mar 2023 16:38:06 -0500 Message-ID: <20230323213808.398039-4-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323213808.398039-1-terry.bowman@amd.com> References: <20230323213808.398039-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT078:EE_|PH7PR12MB8054:EE_ X-MS-Office365-Filtering-Correlation-Id: 39a495ed-7ef4-4e03-8a98-08db2be6fc80 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: QlCq3QwaTQzlgyGwXtSlQDYuevD/zK15CBkT6osL2wT1HnLbQugx+pAIZjBQOOMof90Y1ilmTimeY/ekIgIRQ1R99LoYrOFujrZdcNpDO/cyiaxwzKKcolLXVnJkDDm/CNdtTcPTicjld3RmYIKmX+potINNFQMqCMErvDC/3wFAK5ba+szOPy4fC+xv/1rbDtYwaJZlNN3xXtBbM0WvxI1t9yJLTW4acFIJ84hwNYO50vO/zeUnFQ/MfTCiql4m572NeB5uPVXuiYZe0Lx8fn3LGq6+rPU6umebOapxJeS7+M6rTNdM++VJ/j8EvMGJrwOCCxcBEAwptTGSrZeMO2kkUYWb0wmkxg2ZR4XYy/l6ezm76XGIOUoO6cOEKzwLxhS/u4LeJbL8WUqxnODdHYoFbdFSDVWONNrvYpUWrj+Y3qzC797kTmPm2Gs4XKAvqpQQipVThXV+kR1rZgivl79haA/l1Y64EEYJQqJ070PFXlOOszOe/ky95NyeqJlCXnkCEH9b9MgpnJvcbItzo4eW1/PuNTvDJRUAtub5q4aJfNFpUdk7IVBKvRBK51SROiI/RQHvtgkqgImzO5Rt3gmku2AphJl4fnzRvqROVXjB7Z2SY0kUFxPlWjUH/MVC9jPcfdFbhAmc+aII0LQ6xH9xbsvoUTKCCS2BIE0nksOqw4mxiuMZY/Cq8/5zJ8FcuGd47r34kVTTNr6WoU10YtIcbuIbpM3jfY9US/ViBSRFT1dOVp9cxwLGukutbeM0 X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230025)(4636009)(346002)(376002)(39860400002)(396003)(136003)(451199018)(40470700004)(36840700001)(46966006)(478600001)(40460700003)(70586007)(8676002)(4326008)(4744005)(36860700001)(110136005)(70206006)(6636002)(81166007)(7416002)(41300700001)(5660300002)(44832011)(82740400003)(426003)(8936002)(26005)(6666004)(47076005)(1076003)(2616005)(336012)(316002)(16526019)(186003)(7696005)(54906003)(86362001)(82310400005)(36756003)(40480700001)(921005)(356005)(2906002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 21:38:48.1187 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 39a495ed-7ef4-4e03-8a98-08db2be6fc80 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT078.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8054 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org The CXL driver plans to use cper_print_aer() for restricted CXL host (RCH) logging. cper_print_aer() is not exported and as a result is not available to the CXL driver or other loadable modules. Export cper_print_aer() making it available to CXL and other loadable modules. Signed-off-by: Terry Bowman Cc: Mahesh J Salgaonkar Cc: "Oliver O'Halloran" Cc: Bjorn Helgaas Cc: linux-pci@vger.kernel.org Reviewed-by: Kuppuswamy Sathyanarayanan Acked-by: Bjorn Helgaas --- drivers/pci/pcie/aer.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 625f7b2cafe4..7f0f52d094a4 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -809,6 +809,7 @@ void cper_print_aer(struct pci_dev *dev, int aer_severity, trace_aer_event(dev_name(&dev->dev), (status & ~mask), aer_severity, tlp_header_valid, &aer->header_log); } +EXPORT_SYMBOL_GPL(cper_print_aer); #endif /** From patchwork Thu Mar 23 21:38:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Bowman, Terry" X-Patchwork-Id: 13186110 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D245C6FD1C for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT011.mail.protection.outlook.com (10.13.172.108) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6222.21 via Frontend Transport; Thu, 23 Mar 2023 21:38:59 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 23 Mar 2023 16:38:58 -0500 From: Terry Bowman To: , , , , , , , , , CC: , Subject: [PATCH v2 4/5] cxl/pci: Forward RCH downstream port-detected errors to the CXL.mem dev handler Date: Thu, 23 Mar 2023 16:38:07 -0500 Message-ID: <20230323213808.398039-5-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323213808.398039-1-terry.bowman@amd.com> References: <20230323213808.398039-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT011:EE_|DM4PR12MB5086:EE_ X-MS-Office365-Filtering-Correlation-Id: 94d182c9-945a-4824-3e61-08db2be70319 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 21:38:59.1701 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 94d182c9-945a-4824-3e61-08db2be70319 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT011.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5086 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org From: Robert Richter In RCD mode a CXL device (RCD) is exposed as an RCiEP, but CXL downstream and upstream ports are not enumerated and not visible in the PCIe hierarchy. Protocol and link errors are sent to an RCEC. Now, RCH downstream port-detected errors are signaled as internal AER errors (UIE/CIE) with the RCEC's source ID. A CXL handler must then inspect the error status in various CXL registers residing in the dport's component register space (CXL RAS cap) or the dport's RCRB (AER ext cap). [1] This patch connects errors showing up in the RCEC's error handler with the CXL subsystem. Implement this by forwarding the error to all CXL devices below the RCEC. Since the entire CXL device is controlled only using PCIe Configuration Space of device 0, Function 0, only pass it there [2]. These devices have the Memory Device class code set (PCI_CLASS_MEMORY_CXL, 502h) and the existing cxl_pci driver can implement the handler. The CXL device driver is then responsible to enable error reporting in the RCEC's AER cap (esp. CIE and UIE) and to inspect the dport's CXL registers in addition (CXL RAS cap and AER ext cap). The reason for choosing this implementation is that a CXL RCEC device is bound to the AER port driver, but the driver does not allow it to register a custom specific handler to support CXL. Connecting the RCEC hard-wired with a CXL handler does not work, as the CXL subsystem might not be present all the time. The alternative to add an implementation to the portdrv to allow the registration of a custom RCEC error handler isn't worth doing it as CXL would be its only user. Instead, just check for an CXL RCEC and pass it down to the connected CXL device's error handler. [1] CXL 3.0 spec, 12.2.1.1 RCH Downstream Port-detected Errors [2] CXL 3.0 spec, 8.1.3 PCIe DVSEC for CXL Devices Co-developed-by: Terry Bowman Signed-off-by: Terry Bowman Signed-off-by: Robert Richter Cc: "Oliver O'Halloran" Cc: Bjorn Helgaas Cc: linuxppc-dev@lists.ozlabs.org Cc: linux-pci@vger.kernel.org --- drivers/pci/pcie/aer.c | 45 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 7f0f52d094a4..d250a4caa85a 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -943,6 +943,49 @@ static bool find_source_device(struct pci_dev *parent, return true; } +#if IS_ENABLED(CONFIG_CXL_PCI) + +static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info); + +static int handle_cxl_error_iter(struct pci_dev *dev, void *data) +{ + struct aer_err_info *e_info = (struct aer_err_info *)data; + + if (dev->devfn != PCI_DEVFN(0, 0)) + return 0; + + /* Right now there is only a CXL.mem driver */ + if ((dev->class >> 8) != PCI_CLASS_MEMORY_CXL) + return 0; + + /* pci_dev_put() in handle_error_source() */ + dev = pci_dev_get(dev); + if (dev) + handle_error_source(dev, e_info); + + return 0; +} + +static bool is_internal_error(struct aer_err_info *info) +{ + if (info->severity == AER_CORRECTABLE) + return info->status & PCI_ERR_COR_INTERNAL; + + return info->status & PCI_ERR_UNC_INTN; +} + +static void handle_cxl_error(struct pci_dev *dev, struct aer_err_info *info) +{ + if (pci_pcie_type(dev) == PCI_EXP_TYPE_RC_EC && + is_internal_error(info)) + pcie_walk_rcec(dev, handle_cxl_error_iter, info); +} + +#else +static inline void handle_cxl_error(struct pci_dev *dev, + struct aer_err_info *info) { } +#endif + /** * handle_error_source - handle logging error into an event log * @dev: pointer to pci_dev data structure of error source device @@ -954,6 +997,8 @@ static void handle_error_source(struct pci_dev *dev, struct aer_err_info *info) { int aer = dev->aer_cap; + handle_cxl_error(dev, info); + if (info->severity == AER_CORRECTABLE) { /* * Correctable error does not need software intervention. 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Thu, 23 Mar 2023 21:39:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT092.mail.protection.outlook.com (10.13.173.44) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6222.22 via Frontend Transport; Thu, 23 Mar 2023 21:39:10 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Thu, 23 Mar 2023 16:39:09 -0500 From: Terry Bowman To: , , , , , , , , , CC: , Subject: [PATCH v2 5/5] cxl/pci: Add RCH downstream port error logging Date: Thu, 23 Mar 2023 16:38:08 -0500 Message-ID: <20230323213808.398039-6-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323213808.398039-1-terry.bowman@amd.com> References: <20230323213808.398039-1-terry.bowman@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT092:EE_|PH8PR12MB7445:EE_ X-MS-Office365-Filtering-Correlation-Id: 74c5df4c-62d0-48a3-d3b6-08db2be709e1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 21:39:10.5510 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 74c5df4c-62d0-48a3-d3b6-08db2be709e1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT092.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7445 Precedence: bulk List-ID: X-Mailing-List: linux-cxl@vger.kernel.org RCH downstream port error logging is missing in the current CXL driver. The missing AER and RAS error logging is needed for communicating driver error details to userspace. Update the driver to include PCIe AER and CXL RAS error logging. Add RCH downstream port error handling into the existing RCiEP handler. The downstream port error handler is added to the RCiEP error handler because the downstream port is implemented in a RCRB, is not PCI enumerable, and as a result is not directly accessible to the PCI AER root port driver. The AER root port driver calls the RCiEP handler for handling RCD errors and RCH downstream port protocol errors. Update the cxl_mem driver to map the RCH RAS and AER register discovered earlier. The RAS and AER registers will be used in the RCH error handlers. Disable RCH downstream port's root port cmd interrupts. Enable RCEC AER CIE/UIE reporting because they are disabled by default.[1] Update existing RCiEP correctable and uncorrectable handlers to also call the RCH handler. The RCH handler will read the downstream port AER registers, check for error severity, and if an error exists will log using an existing kernel AER trace routine. The RCH handler will also reuse the existing RAS logging routine to log downstream port RAS errors if they exist. [1] CXL 3.0 Spec, 12.2.1.1 - RCH Downstream Port Detected Errors Co-developed-by: Robert Richter Signed-off-by: Robert Richter Signed-off-by: Terry Bowman --- drivers/cxl/core/pci.c | 126 +++++++++++++++++++++++++++++++++---- drivers/cxl/core/regs.c | 1 + drivers/cxl/cxl.h | 13 ++++ drivers/cxl/mem.c | 134 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 262 insertions(+), 12 deletions(-) diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c index 7328a2552411..6e36471969ba 100644 --- a/drivers/cxl/core/pci.c +++ b/drivers/cxl/core/pci.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -605,32 +606,88 @@ void read_cdat_data(struct cxl_port *port) } EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); -void cxl_cor_error_detected(struct pci_dev *pdev) +/* Get AER severity. Return false if there is no error. */ +static bool cxl_rch_get_aer_severity(struct aer_capability_regs *aer_regs, + int *severity) +{ + if (aer_regs->uncor_status & ~aer_regs->uncor_mask) { + if (aer_regs->uncor_status & PCI_ERR_ROOT_FATAL_RCV) + *severity = AER_FATAL; + else + *severity = AER_NONFATAL; + return true; + } + + if (aer_regs->cor_status & ~aer_regs->cor_mask) { + *severity = AER_CORRECTABLE; + return true; + } + + return false; +} + +/* + * Copy the AER capability registers to a buffer. This is necessary + * because RCRB AER capability is MMIO mapped. Clear the status + * after copying. + * + * @aer_base: base address of AER capability block in RCRB + * @aer_regs: destination for copying AER capability + */ +static bool cxl_rch_get_aer_info(void __iomem *aer_base, + struct aer_capability_regs *aer_regs) +{ + int read_cnt = PCI_AER_CAPABILITY_LENGTH / sizeof(u32); + u32 *aer_regs_buf = (u32 *)aer_regs; + int n; + + if (!aer_base) + return false; + + for (n = 0; n < read_cnt; n++) + aer_regs_buf[n] = readl(aer_base + n * sizeof(u32)); + + writel(aer_regs->uncor_status, aer_base + PCI_ERR_UNCOR_STATUS); + writel(aer_regs->cor_status, aer_base + PCI_ERR_COR_STATUS); + + return true; +} + +static void __cxl_log_correctable_ras(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { - struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); void __iomem *addr; u32 status; - if (!cxlds->regs.ras) + if (!ras_base) return; - addr = cxlds->regs.ras + CXL_RAS_CORRECTABLE_STATUS_OFFSET; + addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; status = readl(addr); if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); trace_cxl_aer_correctable_error(cxlds->cxlmd, status); } } -EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL); + +static void cxl_log_correctable_ras_endpoint(struct cxl_dev_state *cxlds) +{ + return __cxl_log_correctable_ras(cxlds, cxlds->regs.ras); +} + +static void cxl_log_correctable_ras_dport(struct cxl_dev_state *cxlds) +{ + return __cxl_log_correctable_ras(cxlds, cxlds->regs.dport_ras); +} /* CXL spec rev3.0 8.2.4.16.1 */ -static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log) +static void header_log_copy(void __iomem *ras_base, u32 *log) { void __iomem *addr; u32 *log_addr; int i, log_u32_size = CXL_HEADERLOG_SIZE / sizeof(u32); - addr = cxlds->regs.ras + CXL_RAS_HEADER_LOG_OFFSET; + addr = ras_base + CXL_RAS_HEADER_LOG_OFFSET; log_addr = log; for (i = 0; i < log_u32_size; i++) { @@ -644,17 +701,18 @@ static void header_log_copy(struct cxl_dev_state *cxlds, u32 *log) * Log the state of the RAS status registers and prepare them to log the * next error status. Return 1 if reset needed. */ -static bool cxl_report_and_clear(struct cxl_dev_state *cxlds) +static bool __cxl_report_and_clear(struct cxl_dev_state *cxlds, + void __iomem *ras_base) { u32 hl[CXL_HEADERLOG_SIZE_U32]; void __iomem *addr; u32 status; u32 fe; - if (!cxlds->regs.ras) + if (!ras_base) return false; - addr = cxlds->regs.ras + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; + addr = ras_base + CXL_RAS_UNCORRECTABLE_STATUS_OFFSET; status = readl(addr); if (!(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK)) return false; @@ -662,7 +720,7 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds) /* If multiple errors, log header points to first error from ctrl reg */ if (hweight32(status) > 1) { void __iomem *rcc_addr = - cxlds->regs.ras + CXL_RAS_CAP_CONTROL_OFFSET; + ras_base + CXL_RAS_CAP_CONTROL_OFFSET; fe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK, readl(rcc_addr))); @@ -670,13 +728,54 @@ static bool cxl_report_and_clear(struct cxl_dev_state *cxlds) fe = status; } - header_log_copy(cxlds, hl); + header_log_copy(ras_base, hl); trace_cxl_aer_uncorrectable_error(cxlds->cxlmd, status, fe, hl); writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); return true; } +static bool cxl_report_and_clear(struct cxl_dev_state *cxlds) +{ + return __cxl_report_and_clear(cxlds, cxlds->regs.ras); +} + +static bool cxl_report_and_clear_dport(struct cxl_dev_state *cxlds) +{ + return __cxl_report_and_clear(cxlds, cxlds->regs.dport_ras); +} + +static void cxl_rch_log_error(struct cxl_dev_state *cxlds) +{ + struct pci_dev *pdev = to_pci_dev(cxlds->dev); + struct aer_capability_regs aer_regs; + int severity; + + if (!cxl_rch_get_aer_info(cxlds->regs.aer, &aer_regs)) + return; + + if (!cxl_rch_get_aer_severity(&aer_regs, &severity)) + return; + + cper_print_aer(pdev, severity, &aer_regs); + + if (severity == AER_CORRECTABLE) + cxl_log_correctable_ras_dport(cxlds); + else + cxl_report_and_clear_dport(cxlds); +} + +void cxl_cor_error_detected(struct pci_dev *pdev) +{ + struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); + + if (cxlds->rcd) + cxl_rch_log_error(cxlds); + + cxl_log_correctable_ras_endpoint(cxlds); +} +EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, CXL); + pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, pci_channel_state_t state) { @@ -685,6 +784,9 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev, struct device *dev = &cxlmd->dev; bool ue; + if (cxlds->rcd) + cxl_rch_log_error(cxlds); + /* * A frozen channel indicates an impending reset which is fatal to * CXL.mem operation, and will likely crash the system. On the off diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c index 108a349d8101..7130f35891da 100644 --- a/drivers/cxl/core/regs.c +++ b/drivers/cxl/core/regs.c @@ -198,6 +198,7 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, return ret_val; } +EXPORT_SYMBOL_NS_GPL(devm_cxl_iomap_block, CXL); int cxl_map_component_regs(struct device *dev, struct cxl_component_regs *regs, struct cxl_register_map *map, unsigned long map_mask) diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h index 9fd7df48ce99..7036e34354bc 100644 --- a/drivers/cxl/cxl.h +++ b/drivers/cxl/cxl.h @@ -66,6 +66,8 @@ #define CXL_DECODER_MIN_GRANULARITY 256 #define CXL_DECODER_MAX_ENCODED_IG 6 +#define PCI_AER_CAPABILITY_LENGTH 56 + static inline int cxl_hdm_decoder_count(u32 cap_hdr) { int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr); @@ -209,6 +211,15 @@ struct cxl_regs { struct_group_tagged(cxl_device_regs, device_regs, void __iomem *status, *mbox, *memdev; ); + + /* + * Pointer to RCH cxl_dport AER. (only for RCH/RCD mode) + * @dport_aer: CXL 2.0 12.2.11 RCH Downstream Port-detected Errors + */ + struct_group_tagged(cxl_rch_regs, rch_regs, + void __iomem *aer; + void __iomem *dport_ras; + ); }; struct cxl_reg_map { @@ -249,6 +260,8 @@ struct cxl_register_map { }; }; +void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr, + resource_size_t length); void cxl_probe_component_regs(struct device *dev, void __iomem *base, struct cxl_component_reg_map *map); void cxl_probe_device_regs(struct device *dev, void __iomem *base, diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c index 12e8e8ebaac0..e217c44ed749 100644 --- a/drivers/cxl/mem.c +++ b/drivers/cxl/mem.c @@ -4,6 +4,7 @@ #include #include #include +#include #include "cxlmem.h" #include "cxlpci.h" @@ -45,6 +46,132 @@ static int cxl_mem_dpa_show(struct seq_file *file, void *data) return 0; } +static int rcec_enable_aer_ints(struct pci_dev *pdev) +{ + struct pci_dev *rcec = pdev->rcec; + int aer, rc; + u32 mask; + + if (!rcec) + return -ENODEV; + + /* + * Internal errors are masked by default, unmask RCEC's here + * PCI6.0 7.8.4.3 Uncorrectable Error Mask Register (Offset 08h) + * PCI6.0 7.8.4.6 Correctable Error Mask Register (Offset 14h) + */ + aer = rcec->aer_cap; + rc = pci_read_config_dword(rcec, aer + PCI_ERR_UNCOR_MASK, &mask); + if (rc) + return rc; + mask &= ~PCI_ERR_UNC_INTN; + rc = pci_write_config_dword(rcec, aer + PCI_ERR_UNCOR_MASK, mask); + if (rc) + return rc; + + rc = pci_read_config_dword(rcec, aer + PCI_ERR_COR_MASK, &mask); + if (rc) + return rc; + mask &= ~PCI_ERR_COR_INTERNAL; + rc = pci_write_config_dword(rcec, aer + PCI_ERR_COR_MASK, mask); + + return rc; +} + +static void disable_aer(void *_pdev) +{ + struct pci_dev *pdev = (struct pci_dev *)_pdev; + + pci_disable_pcie_error_reporting(pdev); + + /* + * Keep the RCEC's internal AER enabled. There + * could be other RCiEPs using this RCEC. + */ +} + +static void rch_disable_root_ints(void __iomem *aer_base) +{ + u32 aer_cmd_mask, aer_cmd; + + /* + * Disable RCH root port command interrupts. + * CXL3.0 12.2.1.1 - RCH Downstream Port-detected Errors + */ + aer_cmd_mask = (PCI_ERR_ROOT_CMD_COR_EN | + PCI_ERR_ROOT_CMD_NONFATAL_EN | + PCI_ERR_ROOT_CMD_FATAL_EN); + aer_cmd = readl(aer_base + PCI_ERR_ROOT_COMMAND); + aer_cmd &= ~aer_cmd_mask; + writel(aer_cmd, aer_base + PCI_ERR_ROOT_COMMAND); +} + +static int cxl_ras_setup_interrupts(struct cxl_dev_state *cxlds) +{ + struct pci_dev *pdev = to_pci_dev(cxlds->dev); + int rc; + + if (cxlds->rcd) { + rch_disable_root_ints(cxlds->regs.aer); + + rc = rcec_enable_aer_ints(pdev); + if (rc) + return rc; + } + + rc = pci_enable_pcie_error_reporting(pdev); + if (rc) + return rc; + + return devm_add_action_or_reset(&pdev->dev, disable_aer, pdev); +} + +static int cxl_rch_map_ras(struct cxl_dev_state *cxlds, + struct cxl_dport *parent_dport) +{ + struct device *dev = parent_dport->dport; + resource_size_t aer_phys, ras_phys; + void __iomem *aer, *dport_ras; + + if (!parent_dport->rch) + return 0; + + if (!parent_dport->aer_cap || !parent_dport->ras_cap || + parent_dport->component_reg_phys == CXL_RESOURCE_NONE) + return -ENODEV; + + aer_phys = parent_dport->aer_cap + parent_dport->rcrb; + aer = devm_cxl_iomap_block(dev, aer_phys, + PCI_AER_CAPABILITY_LENGTH); + + if (!aer) + return -ENOMEM; + + ras_phys = parent_dport->ras_cap + parent_dport->component_reg_phys; + dport_ras = devm_cxl_iomap_block(dev, ras_phys, + CXL_RAS_CAPABILITY_LENGTH); + + if (!dport_ras) + return -ENOMEM; + + cxlds->regs.aer = aer; + cxlds->regs.dport_ras = dport_ras; + + return 0; +} + +static int cxl_setup_ras(struct cxl_dev_state *cxlds, + struct cxl_dport *parent_dport) +{ + int rc; + + rc = cxl_rch_map_ras(cxlds, parent_dport); + if (rc) + return rc; + + return cxl_ras_setup_interrupts(cxlds); +} + static void cxl_rcrb_setup(struct cxl_dev_state *cxlds, struct cxl_dport *parent_dport) { @@ -93,6 +220,13 @@ static int devm_cxl_add_endpoint(struct device *host, struct cxl_memdev *cxlmd, cxl_rcrb_setup(cxlds, parent_dport); + rc = cxl_setup_ras(cxlds, parent_dport); + /* Continue with RAS setup errors */ + if (rc) + dev_warn(&cxlmd->dev, "CXL RAS setup failed: %d\n", rc); + else + dev_info(&cxlmd->dev, "CXL error handling enabled\n"); + endpoint = devm_cxl_add_port(host, &cxlmd->dev, cxlds->component_reg_phys, parent_dport); if (IS_ERR(endpoint))