From patchwork Thu Mar 23 22:51:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13186130 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A745C6FD1C for ; Thu, 23 Mar 2023 22:51:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231699AbjCWWv5 (ORCPT ); Thu, 23 Mar 2023 18:51:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231596AbjCWWvs (ORCPT ); Thu, 23 Mar 2023 18:51:48 -0400 Received: from mail-io1-xd31.google.com (mail-io1-xd31.google.com [IPv6:2607:f8b0:4864:20::d31]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EA08D2CC78; Thu, 23 Mar 2023 15:51:43 -0700 (PDT) Received: by mail-io1-xd31.google.com with SMTP id p17so80013ioj.10; Thu, 23 Mar 2023 15:51:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679611903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dwzADQniZ1WNKPleXotCSep6PL7MAO9u3e2Lj6vkwpY=; b=WLgLJsY4lIu9scZZcqsQQ6Sz8ntBRk+sXuRTKwSgb3DiniWkIOUieBrTIM57f25oEx 5nBbUfPHDHIG6L8EQuDrZYcglLKg1UQ+KvFn7uJanaY8QCypPJNMR6CndCXmwWUwZrBi AK7j1vZa0u7HPq9t7A8NQ6MUfpyD2mTRUURPuc6I/B3/rWkWQC4EEDDFy+iCcL2Q5tja Z/NM41rKoun0LJJaCEQA4O0xhh9x443XRtE0KG5pO92ORfhhGd4+QmGX3XSydkKzjb6v 6D4zo5SqatR8pHLJuMi5R1RLfOz7G596wQou7aAmU0yVxfvNsQtecpt24JV82uQ5ygMa UeBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679611903; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dwzADQniZ1WNKPleXotCSep6PL7MAO9u3e2Lj6vkwpY=; b=SWXTYffFhQDtGp6o8QUYcRR7wOT+ctifXs43iSQ+NTxlmA+hVIr3B7kw67Mn5mvTRp c2Wslep+bCGoPkrxNy+Xm80zRbXxbwdMmoLLUNsoQwqaQOBznHUZNqSxlIwYtFsRD1K0 lDA+tFsxwh8+kIIwqoQhZNE/RYvvd1M29DnB+xegA/h47z0c/eTPkirXZ0J7HJ7z/BYj FJW0NEoY+7Xb9f/c7NpmCfjLIFREZNtoSsbUKKBpWqRvHFtHJ26n4E4o/jUMRg52vYox NvJ2BPz1pqLuHMcLEUUL09mT8F3bbubhwoJujBy+fBhlTcMGRup2gcliLKeidj3N9Qse CDQw== X-Gm-Message-State: AO0yUKWZYO1vwuHs4fzCcCLedh+agwxxpHIxu0yxAtSbAtfF2ln+BTZb EXlHu19uHlNFlijoUb2iIa7aI5WjLqc= X-Google-Smtp-Source: AK7set/3x35JehsbnDVlYQVfBzkh/qwX6SheUjt6AoIu4EFxebli+D1Axx7KPL/nwJ1xY1w7umkFTQ== X-Received: by 2002:a5e:9813:0:b0:750:a574:7c3c with SMTP id s19-20020a5e9813000000b00750a5747c3cmr603659ioj.1.1679611902844; Thu, 23 Mar 2023 15:51:42 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:f38d:f05d:4666:1249]) by smtp.gmail.com with ESMTPSA id f102-20020a0284ef000000b0040631e8bf89sm6266988jai.38.2023.03.23.15.51.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 15:51:42 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Peng Fan , Fabio Estevam , Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 1/4] clk: imx: composite-8m: Add support to determine_rate Date: Thu, 23 Mar 2023 17:51:25 -0500 Message-Id: <20230323225128.117061-2-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323225128.117061-1-aford173@gmail.com> References: <20230323225128.117061-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Similar to imx/clk-composite-93 and imx/clk-divider-gate, the imx8m_clk_composite_divider_ops can support determine_rate. Without this the parent clocks are set to a fixed value, and if a consumer needs a slower reate, the clock is divided, but the division is only as good as the parent clock rate. With this added, the system can attempt to adjust the parent rate if the proper flags are set which can lead to a more precise clock value. Signed-off-by: Adam Ford Reviewed-by: Peng Fan Reviewed-by: Fabio Estevam --- V3: Change name clk_divider_determine_rate to imx8m_clk_divider_determine_rate to match naming convention V2: No Change diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..3b63e47f088f 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -119,10 +119,17 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, return ret; } +static int clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return clk_divider_ops.determine_rate(hw, req); +} + static const struct clk_ops imx8m_clk_composite_divider_ops = { .recalc_rate = imx8m_clk_composite_divider_recalc_rate, .round_rate = imx8m_clk_composite_divider_round_rate, .set_rate = imx8m_clk_composite_divider_set_rate, + .determine_rate = clk_divider_determine_rate, }; static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) From patchwork Thu Mar 23 22:51:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13186131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 80EF0C761AF for ; Thu, 23 Mar 2023 22:51:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231708AbjCWWv6 (ORCPT ); Thu, 23 Mar 2023 18:51:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231614AbjCWWvu (ORCPT ); Thu, 23 Mar 2023 18:51:50 -0400 Received: from mail-io1-xd32.google.com (mail-io1-xd32.google.com [IPv6:2607:f8b0:4864:20::d32]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 953442CC74; Thu, 23 Mar 2023 15:51:45 -0700 (PDT) Received: by mail-io1-xd32.google.com with SMTP id k17so99287iob.1; Thu, 23 Mar 2023 15:51:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679611904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RB081nZVc8dV6VyELhQ3vJcnmVLV2KlhEV8rp6VNfxY=; b=DevLSpZI1a3F/+379l0Zvj4w4XbRQvDKbOpvV0cg607xGcW5H8AV0vIqnaJ+2uOLDM qYioT5oSWGj/OvxIdVR6D58xOqo8W9QIgJEprnIDSkoCN0A7fqHPU7QcnCIW6uFCYGx/ WZ9kAIOMJ3+EbrUHZE3KkJ/VtCwElycR5fqU5snaNd5KmNxUvs7P7PrSOdjgHA3aNZwb UvFltyjGpeIVKmGLOn62W3mh+rjVDuwVh+rDCmdqKQfIinj8sQ2WA8EZFTcKhPQYF5CS Xh6YW/7KTAuQjlzimGJLELBzUwYUU3d5RkQLaOo5cxZgrvRjNYPw8WI847Xj5Ny/kXH9 Z7fQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679611904; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RB081nZVc8dV6VyELhQ3vJcnmVLV2KlhEV8rp6VNfxY=; b=zSAsxEJPsxV1CSm48llqG7sNBMISbg1vmc1GaNQT3FkkVXq+kAz8y0H7xj+AOlevVo XNUkUvjYicCmD6GZI89pCydg+npprnUUiTie5Z0gKceNqSBW4WESoDTemxYwrN/8o8+C FDGFRyrMcIKCzV4eMIcKaGW+aDTuPktWKGVto8CR9oKfi54T4CAPqQAl9i2JJuSEsEJy y0BlyAb1Cu9QufGfUVTIJJ7e2a8wNxoJ9c4tAX7rDU7fmuc7eT8EvcuP3ZMIMOt81nAg ZNaGRb80PF3zG333fOpVWMpkKu+Bzvc9Kupe9Fgi4u2GknhWcYSPKOvQIc28EsSGmViy eBOw== X-Gm-Message-State: AO0yUKXqEbJkzHR1K9JEnWmczhOJJGw8KAdjQEp7qUk3f6uWHWFwSEX0 scwxSAhijc3TzlWGU8TwJZg4olaREVU= X-Google-Smtp-Source: AK7set8ak+pGnjfuehu8Nk4l3mhAMokOhWPHXUploByWew8sAVBHMzAFrRekwGB4V7Ldzfcp5YKZag== X-Received: by 2002:a5e:d606:0:b0:750:6c44:3454 with SMTP id w6-20020a5ed606000000b007506c443454mr563080iom.12.1679611904360; Thu, 23 Mar 2023 15:51:44 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:f38d:f05d:4666:1249]) by smtp.gmail.com with ESMTPSA id f102-20020a0284ef000000b0040631e8bf89sm6266988jai.38.2023.03.23.15.51.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 15:51:44 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Fabio Estevam , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 2/4] clk: imx: Add imx8m_clk_hw_composite_flags macro Date: Thu, 23 Mar 2023 17:51:26 -0500 Message-Id: <20230323225128.117061-3-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323225128.117061-1-aford173@gmail.com> References: <20230323225128.117061-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 3d94722bbf99..621b0e84ef27 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -417,6 +417,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, _imx8m_clk_hw_composite(name, parent_names, reg, \ 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) +#define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \ + _imx8m_clk_hw_composite(name, parent_names, reg, \ + 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags) + #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ _imx8m_clk_hw_composite(name, parent_names, reg, \ 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) From patchwork Thu Mar 23 22:51:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13186132 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 53445C74A5B for ; Thu, 23 Mar 2023 22:52:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231655AbjCWWwL (ORCPT ); Thu, 23 Mar 2023 18:52:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231651AbjCWWvx (ORCPT ); Thu, 23 Mar 2023 18:51:53 -0400 Received: from mail-io1-xd2d.google.com (mail-io1-xd2d.google.com [IPv6:2607:f8b0:4864:20::d2d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0A139193F7; Thu, 23 Mar 2023 15:51:47 -0700 (PDT) Received: by mail-io1-xd2d.google.com with SMTP id bl9so83924iob.8; Thu, 23 Mar 2023 15:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679611906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g/Q6xa6hn+k+lfvS3cph2ZGvXNMdvP6vRrG80AxIr6U=; b=FCXfX5PvSoceV10qCbE1jx70Fi05EPoQtylGGlRD+AloQC6EVlHOTiGTdSEONPOpw7 aiRf4HMl0D/f9MB124+hHwAcH/d/G5Xtx7VWD6z3vMVVMtmrjzrwSpZYs9b2nS2ZAHGe 9I7UESwPl6BFsS3cFYmUeBPRI4JNBxYpqIHjFz5Nc3V0WXdIghKIwSRiV1OtK3hJExrT 869q9MxHbVGbqnNVYUXRO/UM0hxuWxWlqqsdWQg0+kjk0hqPJCurrxNWznWKkco0uZs4 cXtPAU3VO5xtWPYhNsib3+mOJIw3MmC4zGnjtfs+6BtGa4hxq1GQ5ZTRYeQ2sAVjABb3 B1nQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679611906; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g/Q6xa6hn+k+lfvS3cph2ZGvXNMdvP6vRrG80AxIr6U=; b=oH/fSMKI55r9XIpEgtzr3lGzqE9KhFL0+yBSFnZOQlHv41c/0feX8RQsYQZg9BA9bR jNmQHIM671d4GndRym+/435X+xhSxo8wGrlB5W7GH4+yj1Z2qnnYJJbwR87UcipAZorB NST+NKzRUh2xdiNEsR9psnOYIc9L4L5GLKKQwqGlj8kutcn2iY1SerlNpjcGC4Gdc73/ t2BOcBmPYLFqXOh7AaFsm8Hj/lakwVzq32/1kBvnogqmo77Ct9KD1Kqh19b0ggJYKgyh tNHJcr0pNcPmLI3EejnL83VDmehBMBdDfOwKMoXfGNYrVvRXRB6NUqdCQzWduW9tOeK6 Zw+Q== X-Gm-Message-State: AO0yUKVQ3uXN+Jj33h3gOrZTPOYDKl6C6q7llLSvWiVsSu3vZ8d4Yw+y 4rKQMGP+poFtLnfmCkTUTYN+5SuaAu0= X-Google-Smtp-Source: AK7set+HXZbnRpJ4vJgFWLXBvQvp+3+IFKwxKAE1HpNe0KTAVrXLlCOxrjlgJHjQGXFztvrFFhy/sg== X-Received: by 2002:a5d:8b9a:0:b0:758:6d1e:2978 with SMTP id p26-20020a5d8b9a000000b007586d1e2978mr553873iol.10.1679611905938; Thu, 23 Mar 2023 15:51:45 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:f38d:f05d:4666:1249]) by smtp.gmail.com with ESMTPSA id f102-20020a0284ef000000b0040631e8bf89sm6266988jai.38.2023.03.23.15.51.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 15:51:45 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Fabio Estevam , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 3/4] clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate Date: Thu, 23 Mar 2023 17:51:27 -0500 Message-Id: <20230323225128.117061-4-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323225128.117061-1-aford173@gmail.com> References: <20230323225128.117061-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org By default the display pixel clock needs to be evenly divide down from 594MHz which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll1 594000000 video_pll1_bypass 594000000 video_pll1_out 594000000 lcdif_pixel 148500000 Now that composite-8m supports determine_rate, we can allow lcdif_pixel to set the parent rate which then switches every clock in the chain to a new frequency when lcdif_pixel cannot evenly divide from video_pll1_out. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index b618892170f2..075f643e3f35 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -468,7 +468,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_hw_composite("pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380); hws[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_hw_composite("pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400); hws[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_hw_composite("dc_pixel", imx8mm_dc_pixel_sels, base + 0xa480); - hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500); + hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite_flags("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); hws[IMX8MM_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mm_sai1_sels, base + 0xa580); hws[IMX8MM_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mm_sai2_sels, base + 0xa600); hws[IMX8MM_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mm_sai3_sels, base + 0xa680); From patchwork Thu Mar 23 22:51:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13186133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C1DCC7619A for ; Thu, 23 Mar 2023 22:52:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231680AbjCWWwM (ORCPT ); Thu, 23 Mar 2023 18:52:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231678AbjCWWvy (ORCPT ); Thu, 23 Mar 2023 18:51:54 -0400 Received: from mail-io1-xd2f.google.com (mail-io1-xd2f.google.com [IPv6:2607:f8b0:4864:20::d2f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4ACE19F29; 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Thu, 23 Mar 2023 15:51:47 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Fabio Estevam , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V3 4/4] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate Date: Thu, 23 Mar 2023 17:51:28 -0500 Message-Id: <20230323225128.117061-5-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323225128.117061-1-aford173@gmail.com> References: <20230323225128.117061-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 148500000 disp_pixel_clk 148500000 Now that composite-8m supports determine_rate, we can allow disp_pixel to set the parent rate which then switches every clock in the chain to a new frequency when disp_pixel cannot evenly divide from video_pll_out. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index a042ed3a9d6c..4b23a4648600 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -470,7 +470,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000); hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080); - hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500); + hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite_flags("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600); hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mn_sai3_sels, base + 0xa680); hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mn_sai5_sels, base + 0xa780);