From patchwork Thu Mar 23 23:01:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13186147 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47F58C74A5B for ; Thu, 23 Mar 2023 23:01:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229997AbjCWXBf (ORCPT ); Thu, 23 Mar 2023 19:01:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229660AbjCWXBd (ORCPT ); Thu, 23 Mar 2023 19:01:33 -0400 Received: from mail-il1-x131.google.com (mail-il1-x131.google.com [IPv6:2607:f8b0:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27CF4B464; Thu, 23 Mar 2023 16:01:32 -0700 (PDT) Received: by mail-il1-x131.google.com with SMTP id i19so99035ila.10; Thu, 23 Mar 2023 16:01:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679612491; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xoCYglyZRXBAsXij28ODxM/pUlkw5MAovi/FF2CLHQ8=; b=EuLUTSOXPcNUYVeKnTB4g9KwdaJWobchhRiVJyyhfD91KWS+b0MlS4OMpooyKBAgdV xzItG1xrsWtlkihU9MEE62fZDbxXLWsB1oyAZ9l81RR09vJtVXDgKzfNUfItxVgzgEER KkH1kc77ClORzJv+QgH0phBb8q1NHPyuTQPTdjiUg8DiHZdDgl4uuudjhHPPxK1tUqT7 Bto8XS+HZJogUJF/gclufOTDTb8E3lCnvPY40uH/UjHICTRruzl6NXH9LGXfEQz8iDvy DDDfQhNRw83hx23TMXfD9o9aWYobLjqDkO6EYD3g32v5cuEfY8Nw+hiyMC3N0sYaBkq4 npiw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679612491; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xoCYglyZRXBAsXij28ODxM/pUlkw5MAovi/FF2CLHQ8=; b=YXpYZL5xUmokQ/npIKG8eIRVySs90/eNWSdDlLKV+lKt8+yq/N250sKoFiPH258UMl /Fn9Sg0bPEIaz7s4KzTozMOZqwC7vGREMN0PqJF7nCJ0rMztzcHEgsMWpPchfNgiH8sn ZxvsRyLBwirR13V725m2c1Ru1ujg3fB/5LscOnSlrTYaiZ3VNCIQmC7xG8kmuuT+WtY5 0AVPb6w1xPbsd2W5F99o7HPDhmF0pPPsMjlZEk4AwEhU31KBRQCs5bJDeWMco5qzSBlV UrTedQuY/xzIJ/UDjaPQBr387dcYq4CZ2By7jeqzrh15ne8Ux5kK1l+HAJqF+b6q+fcP vyXw== X-Gm-Message-State: AAQBX9cyK09JuLDbgaILw69tvoQduH2/tMBPgvuYB2DaLDGF2TF9qZ5b oBv9xUsZRyas2Yt0p8ZBDRxOhihwU4E= X-Google-Smtp-Source: AKy350aB8mG/RWYSizA0hQrtNJ+VzeQIYF95T4UM+86HtnAts5iISqBLXr56ECHs23F+T51U/wzZWw== X-Received: by 2002:a92:cb47:0:b0:325:da54:ae8b with SMTP id f7-20020a92cb47000000b00325da54ae8bmr703358ilq.9.1679612491131; Thu, 23 Mar 2023 16:01:31 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:f38d:f05d:4666:1249]) by smtp.gmail.com with ESMTPSA id w20-20020a056e0213f400b00314201bcbdfsm5405492ilj.3.2023.03.23.16.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 16:01:30 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Peng Fan , Fabio Estevam , Abel Vesa , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 1/4] clk: imx: composite-8m: Add support to determine_rate Date: Thu, 23 Mar 2023 18:01:24 -0500 Message-Id: <20230323230127.120883-2-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323230127.120883-1-aford173@gmail.com> References: <20230323230127.120883-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Similar to imx/clk-composite-93 and imx/clk-divider-gate, the imx8m_clk_composite_divider_ops can support determine_rate. Without this the parent clocks are set to a fixed value, and if a consumer needs a slower reate, the clock is divided, but the division is only as good as the parent clock rate. With this added, the system can attempt to adjust the parent rate if the proper flags are set which can lead to a more precise clock value. Signed-off-by: Adam Ford Reviewed-by: Peng Fan Reviewed-by: Fabio Estevam --- V4: Sorry for the noise. I forgot to 'git ammend' What V3 was supposed to be. V3: Change name clk_divider_determine_rate to imx8m_clk_divider_determine_rate to match naming convention V2: No Change diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c index cbf0d7955a00..6883a8199b6c 100644 --- a/drivers/clk/imx/clk-composite-8m.c +++ b/drivers/clk/imx/clk-composite-8m.c @@ -119,10 +119,17 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw, return ret; } +static int imx8m_clk_divider_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + return clk_divider_ops.determine_rate(hw, req); +} + static const struct clk_ops imx8m_clk_composite_divider_ops = { .recalc_rate = imx8m_clk_composite_divider_recalc_rate, .round_rate = imx8m_clk_composite_divider_round_rate, .set_rate = imx8m_clk_composite_divider_set_rate, + .determine_rate = imx8m_clk_divider_determine_rate, }; static u8 imx8m_clk_composite_mux_get_parent(struct clk_hw *hw) From patchwork Thu Mar 23 23:01:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13186148 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C05DC761AF for ; Thu, 23 Mar 2023 23:01:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229830AbjCWXBr (ORCPT ); Thu, 23 Mar 2023 19:01:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229960AbjCWXBe (ORCPT ); Thu, 23 Mar 2023 19:01:34 -0400 Received: from mail-il1-x12f.google.com (mail-il1-x12f.google.com [IPv6:2607:f8b0:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF50EB464; Thu, 23 Mar 2023 16:01:33 -0700 (PDT) Received: by mail-il1-x12f.google.com with SMTP id s7so94715ilv.12; Thu, 23 Mar 2023 16:01:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679612493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RB081nZVc8dV6VyELhQ3vJcnmVLV2KlhEV8rp6VNfxY=; b=X6UBU55JTHWlJqMB3S20dS+Wy+yffRoBqr+j3zoDuWC0/Mi4B4FuCuIWN4McJwLwTm wNOeVDKR3MMRFr4lDsfweYTODJz32M5fWi7wDAFuOwxF1tS0CuT08O5UdpozWSUmwNK8 yqt3bISWBB/0zrnvFXUtxhdxruhcLK4nmJoeHsXX6WI0v8447WCou5u9cAAPHtV4hFwp IR+5fy8SSv1jVeBPB/1TEtptRXWd7ZOzj7DpCSlNzLeL8uAREwnInAnZExQcMVJ3LmoE HrUhlZqqb1KwoXuYRYrgUuHzEKbzMB45JlBDeGjNnA0VVF2Gv46TjKf3K4jk7UjJ444j cuRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679612493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RB081nZVc8dV6VyELhQ3vJcnmVLV2KlhEV8rp6VNfxY=; b=JPXmFKdWnONSn+r7nQuY9DT2kwlrr2DlGJM5pVRj00XYkc1Bs+oTniAIAug46R5Qu7 y4PS+clv0BnKp//Cbe5/dfkfz7RQU0FiAX0YMHo3jnQu/WQaBEdSiCHOfxLaBuiZFOH/ o6vd9MRLlxbqcLCYNxUBNdiwbl4RL36YQkTlNRAfeXQ8vdG450Lakl4Z3ceqXK5DHPbf uirlCF0NK3SzZaOHvp1Cz7ORqRz80Oz2vWU2Xwn9tGrEVQBaw70Oqka844oOQ4g03bUk +R3M7dcTVMXXkQsTXkDnv679NFvtmxwYntKxzWx5j9TE2xUVuo61q1XTSKrJSxVERZ6j hPJw== X-Gm-Message-State: AAQBX9cRx+eF1fBLjw1Wh7niySxW9WurkpCk4LXbD90OHmuYkgSZnGiu rzxfx7yO0lNfTkLfWNv3CRgPiRGJ2Ao= X-Google-Smtp-Source: AKy350bCXvTy/YRdJXkCgkE98FughAgIeIl5gAg2lVjYZrSOt6dZAG/XykJ6Fo8r/E9EmWO1Cr561g== X-Received: by 2002:a92:ce06:0:b0:325:cf0c:e578 with SMTP id b6-20020a92ce06000000b00325cf0ce578mr1001324ilo.12.1679612492744; Thu, 23 Mar 2023 16:01:32 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:f38d:f05d:4666:1249]) by smtp.gmail.com with ESMTPSA id w20-20020a056e0213f400b00314201bcbdfsm5405492ilj.3.2023.03.23.16.01.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 16:01:32 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Fabio Estevam , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 2/4] clk: imx: Add imx8m_clk_hw_composite_flags macro Date: Thu, 23 Mar 2023 18:01:25 -0500 Message-Id: <20230323230127.120883-3-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323230127.120883-1-aford173@gmail.com> References: <20230323230127.120883-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 3d94722bbf99..621b0e84ef27 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -417,6 +417,10 @@ struct clk_hw *__imx8m_clk_hw_composite(const char *name, _imx8m_clk_hw_composite(name, parent_names, reg, \ 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT) +#define imx8m_clk_hw_composite_flags(name, parent_names, reg, flags) \ + _imx8m_clk_hw_composite(name, parent_names, reg, \ + 0, IMX_COMPOSITE_CLK_FLAGS_DEFAULT | flags) + #define imx8m_clk_hw_composite_critical(name, parent_names, reg) \ _imx8m_clk_hw_composite(name, parent_names, reg, \ 0, IMX_COMPOSITE_CLK_FLAGS_CRITICAL) From patchwork Thu Mar 23 23:01:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13186149 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8572DC7619A for ; Thu, 23 Mar 2023 23:01:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230213AbjCWXBo (ORCPT ); Thu, 23 Mar 2023 19:01:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230267AbjCWXBf (ORCPT ); Thu, 23 Mar 2023 19:01:35 -0400 Received: from mail-il1-x131.google.com (mail-il1-x131.google.com [IPv6:2607:f8b0:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DD8EEC4B; Thu, 23 Mar 2023 16:01:35 -0700 (PDT) Received: by mail-il1-x131.google.com with SMTP id i19so99092ila.10; Thu, 23 Mar 2023 16:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1679612494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g/Q6xa6hn+k+lfvS3cph2ZGvXNMdvP6vRrG80AxIr6U=; b=PvnomUgwJhFFGVd77ArauD7bqMvzE1OYSjS9WYvf8/bzz9nXv12fSe+z9+pR4ncTJA hiq2WqRoiJ3etczBYlNNUzckpD74VJbCWJZJXNEkBGaUjZcw4mbrYUr+SQ4c7uKseN4U H5T+m7AHTZmN00OUqUNnUgRziFRiNCJRzjfaEu7jRdWBttETEPtUsu3kJ6o5fOnPzxU1 Tb8xPYcwP+3xhL9b4tfCDZGpbSh7GAWBKWI9oGwP8fU4WMaRgRgzbVaf243v/Y0EzCpc SOCCxzK23qu1blumomrhdEr9Wmfm8Qz3ez0lwfacVogdBZzB07fd4PjkJIDvbydRprmZ EG9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679612494; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g/Q6xa6hn+k+lfvS3cph2ZGvXNMdvP6vRrG80AxIr6U=; b=I/lEOyU1MmM6aS1Ur2M5H11jZotakP9NeIgv3vl5gymjV6WF+hkQZ+HVyCNZfKBGIn YGEeUR61V1o3Q6//JUWPenK45hB74/EoR/lHUbTlnedARBLaDjHovsJyDD43h89nesBz AqZICk5FLHp9+4jp3ddM0cJumUyVFiv+U3uSLC5qq50cUEppf1R8IfJ7TMaYoox6SYWH yGfFILGf9apEi4bPQ6qyeqajviCs/me2ntx+U7R0APt4ZneZxxvpUhSA3QdsLELWd+85 FIiwRaEB08M7nY1iEgdi/fqyTsqO3K+73zsJuzqbZWj1bIBgo2qwDQLRNTnhfMRqeTNQ Pzkw== X-Gm-Message-State: AAQBX9eEhfTW0/eu39KHwIBXpwopIhBBwgYcF81wNiALRugT3SJu/iiX w9/Aam73nCuKNZhw0DxHy/D1fchAdtQ= X-Google-Smtp-Source: AKy350Zu7vFYu8YnzXAXL+VgxNGS+TQ/V7MzyBfsmY5bmH5svzZC3FbmUUPldLCXwQJFji1aQJQLGw== X-Received: by 2002:a92:4b0d:0:b0:323:ec3:49b7 with SMTP id m13-20020a924b0d000000b003230ec349b7mr908478ilg.11.1679612494427; Thu, 23 Mar 2023 16:01:34 -0700 (PDT) Received: from aford-IdeaCentre-A730.lan ([2601:447:d001:897f:f38d:f05d:4666:1249]) by smtp.gmail.com with ESMTPSA id w20-20020a056e0213f400b00314201bcbdfsm5405492ilj.3.2023.03.23.16.01.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Mar 2023 16:01:34 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Fabio Estevam , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 3/4] clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate Date: Thu, 23 Mar 2023 18:01:26 -0500 Message-Id: <20230323230127.120883-4-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323230127.120883-1-aford173@gmail.com> References: <20230323230127.120883-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org By default the display pixel clock needs to be evenly divide down from 594MHz which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll1 594000000 video_pll1_bypass 594000000 video_pll1_out 594000000 lcdif_pixel 148500000 Now that composite-8m supports determine_rate, we can allow lcdif_pixel to set the parent rate which then switches every clock in the chain to a new frequency when lcdif_pixel cannot evenly divide from video_pll1_out. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam diff --git a/drivers/clk/imx/clk-imx8mm.c b/drivers/clk/imx/clk-imx8mm.c index b618892170f2..075f643e3f35 100644 --- a/drivers/clk/imx/clk-imx8mm.c +++ b/drivers/clk/imx/clk-imx8mm.c @@ -468,7 +468,7 @@ static int imx8mm_clocks_probe(struct platform_device *pdev) hws[IMX8MM_CLK_PCIE1_PHY] = imx8m_clk_hw_composite("pcie1_phy", imx8mm_pcie1_phy_sels, base + 0xa380); hws[IMX8MM_CLK_PCIE1_AUX] = imx8m_clk_hw_composite("pcie1_aux", imx8mm_pcie1_aux_sels, base + 0xa400); hws[IMX8MM_CLK_DC_PIXEL] = imx8m_clk_hw_composite("dc_pixel", imx8mm_dc_pixel_sels, base + 0xa480); - hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500); + hws[IMX8MM_CLK_LCDIF_PIXEL] = imx8m_clk_hw_composite_flags("lcdif_pixel", imx8mm_lcdif_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); hws[IMX8MM_CLK_SAI1] = imx8m_clk_hw_composite("sai1", imx8mm_sai1_sels, base + 0xa580); hws[IMX8MM_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mm_sai2_sels, base + 0xa600); hws[IMX8MM_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mm_sai3_sels, base + 0xa680); From patchwork Thu Mar 23 23:01:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Adam Ford X-Patchwork-Id: 13186150 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0AE0C74A5B for ; Thu, 23 Mar 2023 23:01:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231146AbjCWXBs (ORCPT ); Thu, 23 Mar 2023 19:01:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230369AbjCWXBh (ORCPT ); Thu, 23 Mar 2023 19:01:37 -0400 Received: from mail-il1-x131.google.com (mail-il1-x131.google.com [IPv6:2607:f8b0:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 226CCDBCB; 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Thu, 23 Mar 2023 16:01:35 -0700 (PDT) From: Adam Ford To: linux-clk@vger.kernel.org Cc: aford@beaconembedded.com, Adam Ford , Fabio Estevam , Abel Vesa , Peng Fan , Michael Turquette , Stephen Boyd , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , NXP Linux Team , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH V4 4/4] clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate Date: Thu, 23 Mar 2023 18:01:27 -0500 Message-Id: <20230323230127.120883-5-aford173@gmail.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230323230127.120883-1-aford173@gmail.com> References: <20230323230127.120883-1-aford173@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 148500000 disp_pixel_clk 148500000 Now that composite-8m supports determine_rate, we can allow disp_pixel to set the parent rate which then switches every clock in the chain to a new frequency when disp_pixel cannot evenly divide from video_pll_out. Signed-off-by: Adam Ford Reviewed-by: Fabio Estevam diff --git a/drivers/clk/imx/clk-imx8mn.c b/drivers/clk/imx/clk-imx8mn.c index a042ed3a9d6c..4b23a4648600 100644 --- a/drivers/clk/imx/clk-imx8mn.c +++ b/drivers/clk/imx/clk-imx8mn.c @@ -470,7 +470,7 @@ static int imx8mn_clocks_probe(struct platform_device *pdev) hws[IMX8MN_CLK_DRAM_ALT] = imx8m_clk_hw_fw_managed_composite("dram_alt", imx8mn_dram_alt_sels, base + 0xa000); hws[IMX8MN_CLK_DRAM_APB] = imx8m_clk_hw_fw_managed_composite_critical("dram_apb", imx8mn_dram_apb_sels, base + 0xa080); - hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500); + hws[IMX8MN_CLK_DISP_PIXEL] = imx8m_clk_hw_composite_flags("disp_pixel", imx8mn_disp_pixel_sels, base + 0xa500, CLK_SET_RATE_PARENT); hws[IMX8MN_CLK_SAI2] = imx8m_clk_hw_composite("sai2", imx8mn_sai2_sels, base + 0xa600); hws[IMX8MN_CLK_SAI3] = imx8m_clk_hw_composite("sai3", imx8mn_sai3_sels, base + 0xa680); hws[IMX8MN_CLK_SAI5] = imx8m_clk_hw_composite("sai5", imx8mn_sai5_sels, base + 0xa780);