From patchwork Fri Mar 24 09:36:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 13186582 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B88C4C6FD1C for ; Fri, 24 Mar 2023 09:37:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231583AbjCXJg7 (ORCPT ); Fri, 24 Mar 2023 05:36:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231514AbjCXJg5 (ORCPT ); Fri, 24 Mar 2023 05:36:57 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [217.70.178.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB8E023D99; Fri, 24 Mar 2023 02:36:55 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 14A6610000F; Fri, 24 Mar 2023 09:36:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1679650614; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Odm7qShtV6wGQf5vqVQshQRG9PVCO1dlSKvAJeUzWto=; b=J5v3PHJJlWSaIH/MWKTkrFnB8rt1h6EY250/dPlXLVFc335knI7tnBKeDg8xVzFyptn7n2 kBYfHFXQtHp4ANDf9lpubTfP8oI1xboFMbomIIjDM/qZi7ZI4uGh8kITYzOVn0DRz6PkqO VhCzFhvJQN3vD7ShyYDxbZWpAK+l+4NI9ZKaV2Dq37SryvbT1IHQ9wmRmX0wHYtZSJ8g7Q Om4PqfPrUrfEY7qRwlHSIhzwewVPoP17x/tRxCihkRFjB5Q8ePtRXCneiuu2o3LYIA8YPX MGIXARjCWZ/2EruTS6ONQaDvkbvIC2PNLUZfgqHv89aTvOy5XXJeoD+QxAphXw== From: Maxime Chevallier To: Mark Brown , Greg Kroah-Hartman , rafael@kernel.org, Colin Foster , Vladimir Oltean , Lee Jones , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Heiner Kallweit , Russell King Cc: Maxime Chevallier , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: [RFC 1/7] regmap: add a helper to translate the register address Date: Fri, 24 Mar 2023 10:36:38 +0100 Message-Id: <20230324093644.464704-2-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230324093644.464704-1-maxime.chevallier@bootlin.com> References: <20230324093644.464704-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC Register addresses passed to regmap operations can be offset with regmap.reg_base and downshifted with regmap.reg_downshift. Add a helper to apply both these operations and return the translated address, that we can then use to perform the actual register operation ont the underlying bus. Signed-off-by: Maxime Chevallier --- drivers/base/regmap/regmap.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index d2a54eb0efd9..a4e4367648bf 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -1676,6 +1676,12 @@ static void regmap_set_work_buf_flag_mask(struct regmap *map, int max_bytes, buf[i] |= (mask >> (8 * i)) & 0xff; } +static unsigned int regmap_reg_addr(struct regmap *map, unsigned int reg) +{ + reg += map->reg_base; + return reg >> map->format.reg_downshift; +} + static int _regmap_raw_write_impl(struct regmap *map, unsigned int reg, const void *val, size_t val_len, bool noinc) { @@ -1753,8 +1759,7 @@ static int _regmap_raw_write_impl(struct regmap *map, unsigned int reg, return ret; } - reg += map->reg_base; - reg >>= map->format.reg_downshift; + reg = regmap_reg_addr(map, reg); map->format.format_reg(map->work_buf, reg, map->reg_shift); regmap_set_work_buf_flag_mask(map, map->format.reg_bytes, map->write_flag_mask); @@ -1924,8 +1929,7 @@ static int _regmap_bus_formatted_write(void *context, unsigned int reg, return ret; } - reg += map->reg_base; - reg >>= map->format.reg_downshift; + reg = regmap_reg_addr(map, reg); map->format.format_write(map, reg, val); trace_regmap_hw_write_start(map, reg, 1); @@ -1942,8 +1946,7 @@ static int _regmap_bus_reg_write(void *context, unsigned int reg, { struct regmap *map = context; - reg += map->reg_base; - reg >>= map->format.reg_downshift; + reg = regmap_reg_addr(map, reg); return map->bus->reg_write(map->bus_context, reg, val); } @@ -2494,8 +2497,7 @@ static int _regmap_raw_multi_reg_write(struct regmap *map, unsigned int reg = regs[i].reg; unsigned int val = regs[i].def; trace_regmap_hw_write_start(map, reg, 1); - reg += map->reg_base; - reg >>= map->format.reg_downshift; + reg = regmap_reg_addr(map, reg); map->format.format_reg(u8, reg, map->reg_shift); u8 += reg_bytes + pad_bytes; map->format.format_val(u8, val, 0); @@ -2821,8 +2823,7 @@ static int _regmap_raw_read(struct regmap *map, unsigned int reg, void *val, return ret; } - reg += map->reg_base; - reg >>= map->format.reg_downshift; + reg = regmap_reg_addr(map, reg); map->format.format_reg(map->work_buf, reg, map->reg_shift); regmap_set_work_buf_flag_mask(map, map->format.reg_bytes, map->read_flag_mask); @@ -2842,8 +2843,7 @@ static int _regmap_bus_reg_read(void *context, unsigned int reg, { struct regmap *map = context; - reg += map->reg_base; - reg >>= map->format.reg_downshift; + reg = regmap_reg_addr(map, reg); return map->bus->reg_read(map->bus_context, reg, val); } @@ -3235,8 +3235,7 @@ static int _regmap_update_bits(struct regmap *map, unsigned int reg, *change = false; if (regmap_volatile(map, reg) && map->reg_update_bits) { - reg += map->reg_base; - reg >>= map->format.reg_downshift; + reg = regmap_reg_addr(map, reg); ret = map->reg_update_bits(map->bus_context, reg, mask, val); if (ret == 0 && change) *change = true; From patchwork Fri Mar 24 09:36:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 13186583 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1E91C6FD20 for ; Fri, 24 Mar 2023 09:37:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231708AbjCXJhQ (ORCPT ); Fri, 24 Mar 2023 05:37:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231669AbjCXJhF (ORCPT ); Fri, 24 Mar 2023 05:37:05 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [IPv6:2001:4b98:dc4:8::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 075C923D99; Fri, 24 Mar 2023 02:37:00 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 823AE10000B; Fri, 24 Mar 2023 09:36:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1679650619; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=P2Hf3CyBE1M1ZSzvmtnhpsHtD4ulFZUJigNP2kIndHE=; b=FKAM9peeuA+PH2hCx7Lpn923cVj1ybMQ/8TN4DrVdmhszBYuujwIa6mzcq6xCgz2LFooEH gRPaihCd2v4Gy0JuvaPp2qBAxdy1dvUA09E9hxSdXMXu9NQ5L81dEB8F2ORsDn4CcqMO77 KCHk++76+XpwvI9xaVr8eGz/Kt30CDbE9Gej7Z0Vwrd7j+TZsNtsGAurnFFmB/T+Ba1NWp 2Ep+BbFpM/xJ5heCWM2ML0qRe19ghIGyPd72YWQFQbddCD1pVBE89D/KkTBZxU2SSRMt/1 RSeaafTwQQ6hWslc7H7AWnoTiwLIYBidFhwb9cBE8cP6DDPefu/gf8swCKt/Vw== From: Maxime Chevallier To: Mark Brown , Greg Kroah-Hartman , rafael@kernel.org, Colin Foster , Vladimir Oltean , Lee Jones , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Heiner Kallweit , Russell King Cc: Maxime Chevallier , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: [RFC 2/7] regmap: check for alignment on translated register addresses Date: Fri, 24 Mar 2023 10:36:39 +0100 Message-Id: <20230324093644.464704-3-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230324093644.464704-1-maxime.chevallier@bootlin.com> References: <20230324093644.464704-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC With regmap->reg_base and regmap->reg_downshift, the actual register address that is going to be used for the next operation might not be the same as the one we have as an input. Addresses can be offset with reg_base and shifted, which will affect alignment. Check for alignment on the real register address. Signed-off-by: Maxime Chevallier --- drivers/base/regmap/regmap.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index a4e4367648bf..726f59612fd6 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -2016,7 +2016,7 @@ int regmap_write(struct regmap *map, unsigned int reg, unsigned int val) { int ret; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; map->lock(map->lock_arg); @@ -2043,7 +2043,7 @@ int regmap_write_async(struct regmap *map, unsigned int reg, unsigned int val) { int ret; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; map->lock(map->lock_arg); @@ -2258,7 +2258,7 @@ int regmap_noinc_write(struct regmap *map, unsigned int reg, return -EINVAL; if (val_len % map->format.val_bytes) return -EINVAL; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; if (val_len == 0) return -EINVAL; @@ -2399,7 +2399,7 @@ int regmap_bulk_write(struct regmap *map, unsigned int reg, const void *val, int ret = 0, i; size_t val_bytes = map->format.val_bytes; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; /* @@ -2638,7 +2638,7 @@ static int _regmap_multi_reg_write(struct regmap *map, int reg = regs[i].reg; if (!map->writeable_reg(map->dev, reg)) return -EINVAL; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; } @@ -2789,7 +2789,7 @@ int regmap_raw_write_async(struct regmap *map, unsigned int reg, if (val_len % map->format.val_bytes) return -EINVAL; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; map->lock(map->lock_arg); @@ -2911,7 +2911,7 @@ int regmap_read(struct regmap *map, unsigned int reg, unsigned int *val) { int ret; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; map->lock(map->lock_arg); @@ -2945,7 +2945,7 @@ int regmap_raw_read(struct regmap *map, unsigned int reg, void *val, if (val_len % map->format.val_bytes) return -EINVAL; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; if (val_count == 0) return -EINVAL; @@ -3040,7 +3040,7 @@ int regmap_noinc_read(struct regmap *map, unsigned int reg, if (val_len % map->format.val_bytes) return -EINVAL; - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; if (val_len == 0) return -EINVAL; @@ -3162,7 +3162,7 @@ int regmap_bulk_read(struct regmap *map, unsigned int reg, void *val, size_t val_bytes = map->format.val_bytes; bool vol = regmap_volatile_range(map, reg, val_count); - if (!IS_ALIGNED(reg, map->reg_stride)) + if (!IS_ALIGNED(regmap_reg_addr(map, reg), map->reg_stride)) return -EINVAL; if (val_count == 0) return -EINVAL; From patchwork Fri Mar 24 09:36:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 13186584 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 11E6EC76196 for ; Fri, 24 Mar 2023 09:37:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231669AbjCXJhT (ORCPT ); Fri, 24 Mar 2023 05:37:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231602AbjCXJhG (ORCPT ); Fri, 24 Mar 2023 05:37:06 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [IPv6:2001:4b98:dc4:8::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E1F524C98; Fri, 24 Mar 2023 02:37:04 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 8584A100015; Fri, 24 Mar 2023 09:36:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1679650623; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ya2n9BSLCKw2UN7tvwjwr02RTqzpvvXHPx/OBwXBY1E=; b=fndyXpHryL7YQKlmX8ZIcCG8Ai+ANP8YQynTi8SIOuE5wZfRJqgBwcyt1bCC3+9TTFpRtU CzyynAZn5njEA4PlprcSwmvsclzZywk7c48bvMjtrqudKHq2wmCOik0NiOspRhES5geQfr 94H92JCirWYmY5NCOq/1GR9t3PSGpQUprpE6/h6X0LCm5zTs+Rvg6Jqwh0dTn+pEAtZUlJ wle1WndMMjo9gsBUcZs/aoaeLPqQgazGcX7gSjQvtCKYEffeea1zGOXAzWi2JLMwlg9Pa8 wccrPWCpodwbZwJ+dCV4uXReZvRq8rJWWI2sNMrpQLSr8ooWA7TOmNM4kfxZ8w== From: Maxime Chevallier To: Mark Brown , Greg Kroah-Hartman , rafael@kernel.org, Colin Foster , Vladimir Oltean , Lee Jones , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Heiner Kallweit , Russell King Cc: Maxime Chevallier , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: [RFC 3/7] regmap: allow upshifting register addresses before performing operations Date: Fri, 24 Mar 2023 10:36:40 +0100 Message-Id: <20230324093644.464704-4-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230324093644.464704-1-maxime.chevallier@bootlin.com> References: <20230324093644.464704-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC Similar to the existing reg_downshift mechanism, that is used to translate register addresses on busses that have a smaller address stride, it's also possible to want to upshift register addresses. Such a case was encountered when network PHYs and PCS that usually sit on a MDIO bus (16-bits register with a stride of 1) are integrated directly as memory-mapped devices. Here, the same register layout defined in 802.3 is used, but the register now have a larger stride. Introduce a mechanism to also allow upshifting register addresses. Re-purpose reg_downshift into a more generic, signed reg_shift, whose sign indicates the direction of the shift. To avoid confusion, also introduce macros to explicitly indicate if we want to downshift or upshift. For bisectability, change any use of reg_downshift to use reg_shift. Signed-off-by: Maxime Chevallier --- drivers/base/regmap/internal.h | 2 +- drivers/base/regmap/regmap.c | 10 ++++++++-- drivers/mfd/ocelot-spi.c | 2 +- include/linux/regmap.h | 15 ++++++++++++--- 4 files changed, 22 insertions(+), 7 deletions(-) diff --git a/drivers/base/regmap/internal.h b/drivers/base/regmap/internal.h index da8996e7a1f1..2ef53936652b 100644 --- a/drivers/base/regmap/internal.h +++ b/drivers/base/regmap/internal.h @@ -31,7 +31,7 @@ struct regmap_format { size_t buf_size; size_t reg_bytes; size_t pad_bytes; - size_t reg_downshift; + int reg_shift; size_t val_bytes; void (*format_write)(struct regmap *map, unsigned int reg, unsigned int val); diff --git a/drivers/base/regmap/regmap.c b/drivers/base/regmap/regmap.c index 726f59612fd6..c4cde4f45b05 100644 --- a/drivers/base/regmap/regmap.c +++ b/drivers/base/regmap/regmap.c @@ -814,7 +814,7 @@ struct regmap *__regmap_init(struct device *dev, map->format.reg_bytes = DIV_ROUND_UP(config->reg_bits, 8); map->format.pad_bytes = config->pad_bits / 8; - map->format.reg_downshift = config->reg_downshift; + map->format.reg_shift = config->reg_shift; map->format.val_bytes = DIV_ROUND_UP(config->val_bits, 8); map->format.buf_size = DIV_ROUND_UP(config->reg_bits + config->val_bits + config->pad_bits, 8); @@ -1679,7 +1679,13 @@ static void regmap_set_work_buf_flag_mask(struct regmap *map, int max_bytes, static unsigned int regmap_reg_addr(struct regmap *map, unsigned int reg) { reg += map->reg_base; - return reg >> map->format.reg_downshift; + + if (map->format.reg_shift > 0) + reg >>= map->format.reg_shift; + else if (map->format.reg_shift < 0) + reg <<= -(map->format.reg_shift); + + return reg; } static int _regmap_raw_write_impl(struct regmap *map, unsigned int reg, diff --git a/drivers/mfd/ocelot-spi.c b/drivers/mfd/ocelot-spi.c index 2ecd271de2fb..2d1349a10ca9 100644 --- a/drivers/mfd/ocelot-spi.c +++ b/drivers/mfd/ocelot-spi.c @@ -125,7 +125,7 @@ static int ocelot_spi_initialize(struct device *dev) static const struct regmap_config ocelot_spi_regmap_config = { .reg_bits = 24, .reg_stride = 4, - .reg_downshift = 2, + .reg_shift = REGMAP_DOWNSHIFT(2), .val_bits = 32, .write_flag_mask = 0x80, diff --git a/include/linux/regmap.h b/include/linux/regmap.h index 4d10790adeb0..f02c3857b023 100644 --- a/include/linux/regmap.h +++ b/include/linux/regmap.h @@ -46,6 +46,14 @@ struct sdw_slave; #define REGMAP_MDIO_C45_DEVAD_MASK GENMASK(20, 16) #define REGMAP_MDIO_C45_REGNUM_MASK GENMASK(15, 0) +/* + * regmap.reg_shift indicates by how much we must shift registers prior to + * performing any operation. It's a signed value, positive numbers means + * downshifting the register's address, while negative numbers means upshifting. + */ +#define REGMAP_UPSHIFT(s) (-(s)) +#define REGMAP_DOWNSHIFT(s) (s) + /* An enum of all the supported cache types */ enum regcache_type { REGCACHE_NONE, @@ -246,8 +254,9 @@ typedef void (*regmap_unlock)(void *); * @reg_stride: The register address stride. Valid register addresses are a * multiple of this value. If set to 0, a value of 1 will be * used. - * @reg_downshift: The number of bits to downshift the register before - * performing any operations. + * @reg_shift: The number of bits to shift the register before performing any + * operations. Any positive number will be downshifted, and negative + * values will be upshifted * @reg_base: Value to be added to every register address before performing any * operation. * @pad_bits: Number of bits of padding between register and value. @@ -381,7 +390,7 @@ struct regmap_config { int reg_bits; int reg_stride; - int reg_downshift; + int reg_shift; unsigned int reg_base; int pad_bits; int val_bits; From patchwork Fri Mar 24 09:36:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 13186585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 509B7C6FD20 for ; Fri, 24 Mar 2023 09:37:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231944AbjCXJhj (ORCPT ); Fri, 24 Mar 2023 05:37:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231824AbjCXJha (ORCPT ); Fri, 24 Mar 2023 05:37:30 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [IPv6:2001:4b98:dc4:8::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 086CD2596C; Fri, 24 Mar 2023 02:37:11 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 902EF100007; Fri, 24 Mar 2023 09:37:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1679650630; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PjAcdhdUxcOsTOcGYGylxKe370xV/9wJPyxiOPxbjJQ=; b=aD7qwCNeffDbZvrw87ON/4Mt8iFPClmi2/+tKAwBZZmLe+K46FDsiAApGI5eDGo3psk9tB XojG9bMLW7hZrFLpDOdHywmG2hVDGbtcktohEHjX7mlNd0moM4T1metH7P5MYrwnBbkn7W rAOhJvnie7dXxkGDQqePWgx6LKj1X+eFOdUdQG5X9Pq+RfSkI2fGxyTKqXHoILYg440PID AC2M0aIFq5J3hbR/wdld0ZasvVgzYptp6fMZ1jKfay2GMFjlWsVUAggbnKnqoH7pi0hpXN 8jyB5xCFZXrosWTqvEgcgf0j9SEu6RT3VBooWtrIeCIYRmVGsZ6YF9ZHB+vPVw== From: Maxime Chevallier To: Mark Brown , Greg Kroah-Hartman , rafael@kernel.org, Colin Foster , Vladimir Oltean , Lee Jones , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Heiner Kallweit , Russell King Cc: Maxime Chevallier , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: [RFC 4/7] mfd: ocelot-spi: Change the regmap stride to reflect the real one Date: Fri, 24 Mar 2023 10:36:41 +0100 Message-Id: <20230324093644.464704-5-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230324093644.464704-1-maxime.chevallier@bootlin.com> References: <20230324093644.464704-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-State: RFC When used over SPI, the register addresses needs to be translated, compared to when used over MMIO. The translation consists in applying an offset with reg_base, then downshifting the registers by 2. This actually changes the register stride from 4 to 1. Signed-off-by: Maxime Chevallier --- drivers/mfd/ocelot-spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mfd/ocelot-spi.c b/drivers/mfd/ocelot-spi.c index 2d1349a10ca9..107cda0544aa 100644 --- a/drivers/mfd/ocelot-spi.c +++ b/drivers/mfd/ocelot-spi.c @@ -124,7 +124,7 @@ static int ocelot_spi_initialize(struct device *dev) static const struct regmap_config ocelot_spi_regmap_config = { .reg_bits = 24, - .reg_stride = 4, + .reg_stride = 1, .reg_shift = REGMAP_DOWNSHIFT(2), .val_bits = 32, From patchwork Fri Mar 24 09:36:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 13186586 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 975BFC6FD1C for ; Fri, 24 Mar 2023 09:37:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231907AbjCXJhw (ORCPT ); Fri, 24 Mar 2023 05:37:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231901AbjCXJhd (ORCPT ); Fri, 24 Mar 2023 05:37:33 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [217.70.178.231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8DB8625E0A; Fri, 24 Mar 2023 02:37:16 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id ED121100012; Fri, 24 Mar 2023 09:37:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1679650635; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=S8SjFQJjZONjT3KnDkDgI1G1ROLQBpJXsDx1sy1hpgQ=; b=ieqNy0H0w3qiPW3wNDLZF99vm7rtrpTFfQ1YQ8sxr1B6E1+aq95+INUgTykZ357R4w331b Cjwcnia45HaH/vkUkunUTSp7GeIzuOCkQmibEEXf/lBHSPedxNf1cjJVdNx3XhIHZtWmpv MnQUtxjsLmP3ztMqYe2Ge5IbP52a6sANbQFCl8sAa3vr3Pp/+DT9NQDJJcWaPDRkiUI38S Y3NsIorlkbM87siVGSpkcCl4Mipu+C7VZ+3SRYKO1hwwUSSqjY6BMZnaaSWDcED3Se6raK eng5CyJWxQ+SdpFkqDRi60e8/Wty5+pO3GL2CiWJ2zfdCtqbF/hWPzO5A0tWnw== From: Maxime Chevallier To: Mark Brown , Greg Kroah-Hartman , rafael@kernel.org, Colin Foster , Vladimir Oltean , Lee Jones , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Heiner Kallweit , Russell King Cc: Maxime Chevallier , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: [RFC 5/7] net: mdio: Introduce a regmap-based mdio driver Date: Fri, 24 Mar 2023 10:36:42 +0100 Message-Id: <20230324093644.464704-6-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230324093644.464704-1-maxime.chevallier@bootlin.com> References: <20230324093644.464704-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC There exists several examples today of devices that embed an ethernet PHY or PCS directly inside an SoC. In this situation, either the device is controlled through a vendor-specific register set, or sometimes exposes the standard 802.3 registers that are typically accessed over MDIO. As phylib and phylink are designed to use mdiodevices, this driver allows creating a virtual MDIO bus, that translates mdiodev register accesses to regmap accesses. The reason we use regmap is because there are at least 3 such devices known today, 2 of them are Altera TSE PCS's, memory-mapped, exposed with a 4-byte stride in stmmac's dwmac-socfpga variant, and a 2-byte stride in altera-tse. The other one (nxp,sja1110-base-tx-mdio) is exposed over SPI. Signed-off-by: Maxime Chevallier --- MAINTAINERS | 7 +++ drivers/net/mdio/Kconfig | 11 +++++ drivers/net/mdio/Makefile | 1 + drivers/net/mdio/mdio-regmap.c | 85 ++++++++++++++++++++++++++++++++ include/linux/mdio/mdio-regmap.h | 25 ++++++++++ 5 files changed, 129 insertions(+) create mode 100644 drivers/net/mdio/mdio-regmap.c create mode 100644 include/linux/mdio/mdio-regmap.h diff --git a/MAINTAINERS b/MAINTAINERS index 8d5bc223f305..10b3a1800e0d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -12751,6 +12751,13 @@ F: Documentation/devicetree/bindings/net/ieee802154/mcr20a.txt F: drivers/net/ieee802154/mcr20a.c F: drivers/net/ieee802154/mcr20a.h +MDIO REGMAP DRIVER +M: Maxime Chevallier +L: netdev@vger.kernel.org +S: Maintained +F: drivers/net/mdio/mdio-regmap.c +F: include/linux/mdio/mdio-regmap.h + MEASUREMENT COMPUTING CIO-DAC IIO DRIVER M: William Breathitt Gray L: linux-iio@vger.kernel.org diff --git a/drivers/net/mdio/Kconfig b/drivers/net/mdio/Kconfig index 90309980686e..671e4bb82e3e 100644 --- a/drivers/net/mdio/Kconfig +++ b/drivers/net/mdio/Kconfig @@ -182,6 +182,17 @@ config MDIO_IPQ8064 This driver supports the MDIO interface found in the network interface units of the IPQ8064 SoC +config MDIO_REGMAP + tristate "Regmap-based virtual MDIO bus driver" + depends on REGMAP + help + This driver allows using MDIO devices that are not sitting on a + regular MDIO bus, but still exposes the standard 802.3 register + layout. It's regmap-based so that it can be used on integrated, + memory-mapped PHYs, SPI PHYs and so on. A new virtual MDIO bus is + created, and its read/write operations are mapped to the underlying + regmap. + config MDIO_THUNDER tristate "ThunderX SOCs MDIO buses" depends on 64BIT diff --git a/drivers/net/mdio/Makefile b/drivers/net/mdio/Makefile index 7d4cb4c11e4e..1015f0db4531 100644 --- a/drivers/net/mdio/Makefile +++ b/drivers/net/mdio/Makefile @@ -19,6 +19,7 @@ obj-$(CONFIG_MDIO_MOXART) += mdio-moxart.o obj-$(CONFIG_MDIO_MSCC_MIIM) += mdio-mscc-miim.o obj-$(CONFIG_MDIO_MVUSB) += mdio-mvusb.o obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o +obj-$(CONFIG_MDIO_REGMAP) += mdio-regmap.o obj-$(CONFIG_MDIO_SUN4I) += mdio-sun4i.o obj-$(CONFIG_MDIO_THUNDER) += mdio-thunder.o obj-$(CONFIG_MDIO_XGENE) += mdio-xgene.o diff --git a/drivers/net/mdio/mdio-regmap.c b/drivers/net/mdio/mdio-regmap.c new file mode 100644 index 000000000000..c85d62c2f55c --- /dev/null +++ b/drivers/net/mdio/mdio-regmap.c @@ -0,0 +1,85 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* Driver for MMIO-Mapped MDIO devices. Some IPs expose internal PHYs or PCS + * within the MMIO-mapped area + * + * Copyright (C) 2023 Maxime Chevallier + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRV_NAME "mdio-regmap" + +static int mdio_regmap_read_c22(struct mii_bus *bus, int addr, int regnum) +{ + struct mdio_regmap_config *ctx = bus->priv; + unsigned int val; + int ret; + + if (!(ctx->valid_addr & BIT(addr))) + return -ENODEV; + + ret = regmap_read(ctx->regmap, regnum, &val); + if (ret < 0) + return ret; + + return val; +} + +static int mdio_regmap_write_c22(struct mii_bus *bus, int addr, int regnum, + u16 val) +{ + struct mdio_regmap_config *ctx = bus->priv; + + if (!(ctx->valid_addr & BIT(addr))) + return -ENODEV; + + return regmap_write(ctx->regmap, regnum, val); +} + +struct mii_bus *devm_mdio_regmap_register(struct device *dev, + const struct mdio_regmap_config *config) +{ + struct mdio_regmap_config *mrc; + struct mii_bus *mii; + int rc; + + if (!config->parent) + return ERR_PTR(-EINVAL); + + if (!config->valid_addr) + return ERR_PTR(-EINVAL); + + mii = devm_mdiobus_alloc_size(config->parent, sizeof(*mrc)); + if (!mii) + return ERR_PTR(-ENOMEM); + + mrc = mii->priv; + memcpy(mrc, config, sizeof(*mrc)); + + mrc->regmap = config->regmap; + mrc->parent = config->parent; + mrc->valid_addr = config->valid_addr; + + mii->name = DRV_NAME; + strncpy(mii->id, config->name, MII_BUS_ID_SIZE); + mii->parent = config->parent; + mii->read = mdio_regmap_read_c22; + mii->write = mdio_regmap_write_c22; + + rc = devm_mdiobus_register(dev, mii); + if (rc) { + dev_err(config->parent, "Cannot register MDIO bus![%s] (%d)\n", mii->id, rc); + return ERR_PTR(rc); + } + + return mii; +} + diff --git a/include/linux/mdio/mdio-regmap.h b/include/linux/mdio/mdio-regmap.h new file mode 100644 index 000000000000..ea428e5a2913 --- /dev/null +++ b/include/linux/mdio/mdio-regmap.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Driver for MMIO-Mapped MDIO devices. Some IPs expose internal PHYs or PCS + * within the MMIO-mapped area + * + * Copyright (C) 2023 Maxime Chevallier + */ +#ifndef MDIO_REGMAP_H +#define MDIO_REGMAP_H + +#define MDIO_REGMAP_NAME 63 + +struct device; +struct regmap; + +struct mdio_regmap_config { + struct device *parent; + struct regmap *regmap; + char name[MDIO_REGMAP_NAME]; + u32 valid_addr; +}; + +struct mii_bus *devm_mdio_regmap_register(struct device *dev, + const struct mdio_regmap_config *config); + +#endif From patchwork Fri Mar 24 09:36:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 13186587 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 07CEAC6FD20 for ; Fri, 24 Mar 2023 09:37:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231652AbjCXJhy (ORCPT ); Fri, 24 Mar 2023 05:37:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231794AbjCXJhe (ORCPT ); Fri, 24 Mar 2023 05:37:34 -0400 Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [IPv6:2001:4b98:dc4:8::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2196C27D5A; Fri, 24 Mar 2023 02:37:18 -0700 (PDT) Received: (Authenticated sender: maxime.chevallier@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 615B210000A; Fri, 24 Mar 2023 09:37:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1679650637; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=PcKUBQLSHXFtjE2P6mUGL1MaMfPe6D0uqDsP8lwztxk=; b=DRPhLqRlivFZFcn5sxGWGvCvXLueJeNRU6a6x1Ss+Al8tkSCb8NSP4kMCm0bGeaimo7Nn/ DBS4IgPw4qKpwM+CKk5aRBe2r4qrh5V2NJBa/MMKRf6fLx/PGKt0Ca8rn3mcpX8YIbYxID kgRiYLhwaT0JEsWGCb2QJC4omPtV4n/8xeePK+h77lBwoSzIIFjwcpGB//OvKc1SWHdMFu e+xMKCL8C+k8kdQhv1L4vbhDZxA0z61ukf9AtZNDRxvBNZkFcfgqmw4Y22YhUL9fosbded D04rhcRphDJ+N/xjfpbUufoZedAA+xUhLxlbKFrt1LHA/etxfGI6zdwEgnMR5Q== From: Maxime Chevallier To: Mark Brown , Greg Kroah-Hartman , rafael@kernel.org, Colin Foster , Vladimir Oltean , Lee Jones , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Heiner Kallweit , Russell King Cc: Maxime Chevallier , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: [RFC 6/7] net: ethernet: altera-tse: Convert to mdio-regmap and use PCS Lynx Date: Fri, 24 Mar 2023 10:36:43 +0100 Message-Id: <20230324093644.464704-7-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230324093644.464704-1-maxime.chevallier@bootlin.com> References: <20230324093644.464704-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC The newly introduced regmap-based MDIO driver allows for an easy mapping of an mdiodevice onto the memory-mapped TSE PCS, which is actually a Lynx PCS. Convert Altera TSE to use this PCS instead of the pcs-altera-tse, which is nothing more than a memory-mapped Lynx PCS. Signed-off-by: Maxime Chevallier --- drivers/net/ethernet/altera/altera_tse.h | 1 + drivers/net/ethernet/altera/altera_tse_main.c | 54 ++++++++++++++++--- 2 files changed, 49 insertions(+), 6 deletions(-) diff --git a/drivers/net/ethernet/altera/altera_tse.h b/drivers/net/ethernet/altera/altera_tse.h index db5eed06e92d..d50cf440d01b 100644 --- a/drivers/net/ethernet/altera/altera_tse.h +++ b/drivers/net/ethernet/altera/altera_tse.h @@ -477,6 +477,7 @@ struct altera_tse_private { struct phylink *phylink; struct phylink_config phylink_config; struct phylink_pcs *pcs; + struct mdio_device *pcs_mdiodev; }; /* Function prototypes diff --git a/drivers/net/ethernet/altera/altera_tse_main.c b/drivers/net/ethernet/altera/altera_tse_main.c index 66e3af73ec41..c5f4b5e24376 100644 --- a/drivers/net/ethernet/altera/altera_tse_main.c +++ b/drivers/net/ethernet/altera/altera_tse_main.c @@ -27,14 +27,16 @@ #include #include #include +#include #include #include #include #include #include -#include +#include #include #include +#include #include #include @@ -1139,13 +1141,21 @@ static int altera_tse_probe(struct platform_device *pdev) const struct of_device_id *of_id = NULL; struct altera_tse_private *priv; struct resource *control_port; + struct regmap *pcs_regmap; struct resource *dma_res; struct resource *pcs_res; + struct mii_bus *pcs_bus; struct net_device *ndev; void __iomem *descmap; - int pcs_reg_width = 2; int ret = -ENODEV; + struct regmap_config pcs_regmap_cfg; + + struct mdio_regmap_config mrc = { + .parent = &pdev->dev, + .valid_addr = 0x1, + }; + ndev = alloc_etherdev(sizeof(struct altera_tse_private)); if (!ndev) { dev_err(&pdev->dev, "Could not allocate network device\n"); @@ -1263,9 +1273,30 @@ static int altera_tse_probe(struct platform_device *pdev) ret = request_and_map(pdev, "pcs", &pcs_res, &priv->pcs_base); if (ret) { + /* If we can't find a dedicated resource for the PCS, fallback + * to the internal PCS, that has a different address stride + */ priv->pcs_base = priv->mac_dev + tse_csroffs(mdio_phy0); - pcs_reg_width = 4; + pcs_regmap_cfg.reg_bits = 32; + /* Values are MDIO-like values, on 16 bits */ + pcs_regmap_cfg.val_bits = 16; + pcs_regmap_cfg.reg_stride = 4; + pcs_regmap_cfg.reg_shift = REGMAP_UPSHIFT(2); + } else { + pcs_regmap_cfg.reg_bits = 16; + pcs_regmap_cfg.val_bits = 16; + pcs_regmap_cfg.reg_stride = 2; + pcs_regmap_cfg.reg_shift = REGMAP_UPSHIFT(1); + } + + /* Create a regmap for the PCS so that it can be used by the PCS driver */ + pcs_regmap = devm_regmap_init_mmio(&pdev->dev, priv->pcs_base, + &pcs_regmap_cfg); + if (IS_ERR(pcs_regmap)) { + ret = PTR_ERR(pcs_regmap); + goto err_free_netdev; } + mrc.regmap = pcs_regmap; /* Rx IRQ */ priv->rx_irq = platform_get_irq_byname(pdev, "rx_irq"); @@ -1389,7 +1420,15 @@ static int altera_tse_probe(struct platform_device *pdev) (unsigned long) control_port->start, priv->rx_irq, priv->tx_irq); - priv->pcs = alt_tse_pcs_create(ndev, priv->pcs_base, pcs_reg_width); + snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-pcs-mii", ndev->name); + pcs_bus = devm_mdio_regmap_register(&pdev->dev, &mrc); + priv->pcs_mdiodev = mdio_device_create(pcs_bus, 0); + + priv->pcs = lynx_pcs_create(priv->pcs_mdiodev); + if (!priv->pcs) { + ret = -ENODEV; + goto err_init_phy; + } priv->phylink_config.dev = &ndev->dev; priv->phylink_config.type = PHYLINK_NETDEV; @@ -1412,11 +1451,12 @@ static int altera_tse_probe(struct platform_device *pdev) if (IS_ERR(priv->phylink)) { dev_err(&pdev->dev, "failed to create phylink\n"); ret = PTR_ERR(priv->phylink); - goto err_init_phy; + goto err_pcs; } return 0; - +err_pcs: + mdio_device_free(priv->pcs_mdiodev); err_init_phy: unregister_netdev(ndev); err_register_netdev: @@ -1438,6 +1478,8 @@ static int altera_tse_remove(struct platform_device *pdev) altera_tse_mdio_destroy(ndev); unregister_netdev(ndev); phylink_destroy(priv->phylink); + mdio_device_free(priv->pcs_mdiodev); + free_netdev(ndev); return 0; From patchwork Fri Mar 24 09:36:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Chevallier X-Patchwork-Id: 13186588 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 47AE3C6FD20 for ; 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bh=za8AOVXueg+FjzCZ7CZ6vNt9s/rL1y1jmlagfOqWjbU=; b=GmC2Apq3q5y9NgKIseSa/8qxd5n6B1VFTt3Esb+wffgtk9imn0pl6yO6idivqYWu7UQp2+ 87//YxT1pZkzhBqDmZp129WMEconkE7icHGMO/StbUs6zN3m6j00IHd1Duv4Nx7PCL20O+ SgdWP/spCgsxtXF9I8PKk5jBMCLWypsODVph+ipSe5sp78f/JC2rqIzvmi7rWbTbP3VJCm y8J/mcH48Zow9vyWnOZ+YOJ817xgfcWcgud3f/ndvVV1zi/rfVCnmUHcrqrmzPfEJuglh3 le74FYixxJKRWbf+OHf4FG+figLJN9Xabj8JcJMypRc0Irzg2eYsh3OwqxHUkQ== From: Maxime Chevallier To: Mark Brown , Greg Kroah-Hartman , rafael@kernel.org, Colin Foster , Vladimir Oltean , Lee Jones , davem@davemloft.net, Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , Heiner Kallweit , Russell King Cc: Maxime Chevallier , linux-kernel@vger.kernel.org, netdev@vger.kernel.org, thomas.petazzoni@bootlin.com Subject: [RFC 7/7] net: pcs: Drop the TSE PCS driver Date: Fri, 24 Mar 2023 10:36:44 +0100 Message-Id: <20230324093644.464704-8-maxime.chevallier@bootlin.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230324093644.464704-1-maxime.chevallier@bootlin.com> References: <20230324093644.464704-1-maxime.chevallier@bootlin.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org X-Patchwork-State: RFC Now that we can easily create a mdio-device that represents a memory-mapped device that exposes an MDIO-like register layout, we don't need the Altera TSE PCS anymore, since we can use the Lynx PCS instead. Signed-off-by: Maxime Chevallier --- MAINTAINERS | 7 -- drivers/net/pcs/Kconfig | 6 -- drivers/net/pcs/Makefile | 1 - drivers/net/pcs/pcs-altera-tse.c | 160 ------------------------------- include/linux/pcs-altera-tse.h | 17 ---- 5 files changed, 191 deletions(-) delete mode 100644 drivers/net/pcs/pcs-altera-tse.c delete mode 100644 include/linux/pcs-altera-tse.h diff --git a/MAINTAINERS b/MAINTAINERS index 10b3a1800e0d..e2e648a46e3f 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -909,13 +909,6 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/ethernet/altera/ -ALTERA TSE PCS -M: Maxime Chevallier -L: netdev@vger.kernel.org -S: Supported -F: drivers/net/pcs/pcs-altera-tse.c -F: include/linux/pcs-altera-tse.h - ALTERA UART/JTAG UART SERIAL DRIVERS M: Tobias Klauser L: linux-serial@vger.kernel.org diff --git a/drivers/net/pcs/Kconfig b/drivers/net/pcs/Kconfig index 6e7e6c346a3e..6289b7c765f1 100644 --- a/drivers/net/pcs/Kconfig +++ b/drivers/net/pcs/Kconfig @@ -26,10 +26,4 @@ config PCS_RZN1_MIIC on RZ/N1 SoCs. This PCS converts MII to RMII/RGMII or can be set in pass-through mode for MII. -config PCS_ALTERA_TSE - tristate - help - This module provides helper functions for the Altera Triple Speed - Ethernet SGMII PCS, that can be found on the Intel Socfpga family. - endmenu diff --git a/drivers/net/pcs/Makefile b/drivers/net/pcs/Makefile index 4c780d8f2e98..0ff5388fcdea 100644 --- a/drivers/net/pcs/Makefile +++ b/drivers/net/pcs/Makefile @@ -6,4 +6,3 @@ pcs_xpcs-$(CONFIG_PCS_XPCS) := pcs-xpcs.o pcs-xpcs-nxp.o obj-$(CONFIG_PCS_XPCS) += pcs_xpcs.o obj-$(CONFIG_PCS_LYNX) += pcs-lynx.o obj-$(CONFIG_PCS_RZN1_MIIC) += pcs-rzn1-miic.o -obj-$(CONFIG_PCS_ALTERA_TSE) += pcs-altera-tse.o diff --git a/drivers/net/pcs/pcs-altera-tse.c b/drivers/net/pcs/pcs-altera-tse.c deleted file mode 100644 index d616749761f4..000000000000 --- a/drivers/net/pcs/pcs-altera-tse.c +++ /dev/null @@ -1,160 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Copyright (C) 2022 Bootlin - * - * Maxime Chevallier - */ - -#include -#include -#include -#include - -/* SGMII PCS register addresses - */ -#define SGMII_PCS_LINK_TIMER_0 0x12 -#define SGMII_PCS_LINK_TIMER_1 0x13 -#define SGMII_PCS_IF_MODE 0x14 -#define PCS_IF_MODE_SGMII_ENA BIT(0) -#define PCS_IF_MODE_USE_SGMII_AN BIT(1) -#define PCS_IF_MODE_SGMI_HALF_DUPLEX BIT(4) -#define PCS_IF_MODE_SGMI_PHY_AN BIT(5) -#define SGMII_PCS_SW_RESET_TIMEOUT 100 /* usecs */ - -struct altera_tse_pcs { - struct phylink_pcs pcs; - void __iomem *base; - int reg_width; -}; - -static struct altera_tse_pcs *phylink_pcs_to_tse_pcs(struct phylink_pcs *pcs) -{ - return container_of(pcs, struct altera_tse_pcs, pcs); -} - -static u16 tse_pcs_read(struct altera_tse_pcs *tse_pcs, int regnum) -{ - if (tse_pcs->reg_width == 4) - return readl(tse_pcs->base + regnum * 4); - else - return readw(tse_pcs->base + regnum * 2); -} - -static void tse_pcs_write(struct altera_tse_pcs *tse_pcs, int regnum, - u16 value) -{ - if (tse_pcs->reg_width == 4) - writel(value, tse_pcs->base + regnum * 4); - else - writew(value, tse_pcs->base + regnum * 2); -} - -static int tse_pcs_reset(struct altera_tse_pcs *tse_pcs) -{ - u16 bmcr; - - /* Reset PCS block */ - bmcr = tse_pcs_read(tse_pcs, MII_BMCR); - bmcr |= BMCR_RESET; - tse_pcs_write(tse_pcs, MII_BMCR, bmcr); - - return read_poll_timeout(tse_pcs_read, bmcr, (bmcr & BMCR_RESET), - 10, SGMII_PCS_SW_RESET_TIMEOUT, 1, - tse_pcs, MII_BMCR); -} - -static int alt_tse_pcs_validate(struct phylink_pcs *pcs, - unsigned long *supported, - const struct phylink_link_state *state) -{ - if (state->interface == PHY_INTERFACE_MODE_SGMII || - state->interface == PHY_INTERFACE_MODE_1000BASEX) - return 1; - - return -EINVAL; -} - -static int alt_tse_pcs_config(struct phylink_pcs *pcs, unsigned int mode, - phy_interface_t interface, - const unsigned long *advertising, - bool permit_pause_to_mac) -{ - struct altera_tse_pcs *tse_pcs = phylink_pcs_to_tse_pcs(pcs); - u32 ctrl, if_mode; - - ctrl = tse_pcs_read(tse_pcs, MII_BMCR); - if_mode = tse_pcs_read(tse_pcs, SGMII_PCS_IF_MODE); - - /* Set link timer to 1.6ms, as per the MegaCore Function User Guide */ - tse_pcs_write(tse_pcs, SGMII_PCS_LINK_TIMER_0, 0x0D40); - tse_pcs_write(tse_pcs, SGMII_PCS_LINK_TIMER_1, 0x03); - - if (interface == PHY_INTERFACE_MODE_SGMII) { - if_mode |= PCS_IF_MODE_USE_SGMII_AN | PCS_IF_MODE_SGMII_ENA; - } else if (interface == PHY_INTERFACE_MODE_1000BASEX) { - if_mode &= ~(PCS_IF_MODE_USE_SGMII_AN | PCS_IF_MODE_SGMII_ENA); - } - - ctrl |= (BMCR_SPEED1000 | BMCR_FULLDPLX | BMCR_ANENABLE); - - tse_pcs_write(tse_pcs, MII_BMCR, ctrl); - tse_pcs_write(tse_pcs, SGMII_PCS_IF_MODE, if_mode); - - return tse_pcs_reset(tse_pcs); -} - -static void alt_tse_pcs_get_state(struct phylink_pcs *pcs, - struct phylink_link_state *state) -{ - struct altera_tse_pcs *tse_pcs = phylink_pcs_to_tse_pcs(pcs); - u16 bmsr, lpa; - - bmsr = tse_pcs_read(tse_pcs, MII_BMSR); - lpa = tse_pcs_read(tse_pcs, MII_LPA); - - phylink_mii_c22_pcs_decode_state(state, bmsr, lpa); -} - -static void alt_tse_pcs_an_restart(struct phylink_pcs *pcs) -{ - struct altera_tse_pcs *tse_pcs = phylink_pcs_to_tse_pcs(pcs); - u16 bmcr; - - bmcr = tse_pcs_read(tse_pcs, MII_BMCR); - bmcr |= BMCR_ANRESTART; - tse_pcs_write(tse_pcs, MII_BMCR, bmcr); - - /* This PCS seems to require a soft reset to re-sync the AN logic */ - tse_pcs_reset(tse_pcs); -} - -static const struct phylink_pcs_ops alt_tse_pcs_ops = { - .pcs_validate = alt_tse_pcs_validate, - .pcs_get_state = alt_tse_pcs_get_state, - .pcs_config = alt_tse_pcs_config, - .pcs_an_restart = alt_tse_pcs_an_restart, -}; - -struct phylink_pcs *alt_tse_pcs_create(struct net_device *ndev, - void __iomem *pcs_base, int reg_width) -{ - struct altera_tse_pcs *tse_pcs; - - if (reg_width != 4 && reg_width != 2) - return ERR_PTR(-EINVAL); - - tse_pcs = devm_kzalloc(&ndev->dev, sizeof(*tse_pcs), GFP_KERNEL); - if (!tse_pcs) - return ERR_PTR(-ENOMEM); - - tse_pcs->pcs.ops = &alt_tse_pcs_ops; - tse_pcs->base = pcs_base; - tse_pcs->reg_width = reg_width; - - return &tse_pcs->pcs; -} -EXPORT_SYMBOL_GPL(alt_tse_pcs_create); - -MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("Altera TSE PCS driver"); -MODULE_AUTHOR("Maxime Chevallier "); diff --git a/include/linux/pcs-altera-tse.h b/include/linux/pcs-altera-tse.h deleted file mode 100644 index 92ab9f08e835..000000000000 --- a/include/linux/pcs-altera-tse.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (C) 2022 Bootlin - * - * Maxime Chevallier - */ - -#ifndef __LINUX_PCS_ALTERA_TSE_H -#define __LINUX_PCS_ALTERA_TSE_H - -struct phylink_pcs; -struct net_device; - -struct phylink_pcs *alt_tse_pcs_create(struct net_device *ndev, - void __iomem *pcs_base, int reg_width); - -#endif /* __LINUX_PCS_ALTERA_TSE_H */