From patchwork Wed Jan 30 09:40:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10788021 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4CD29188D for ; Wed, 30 Jan 2019 09:40:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A9D82E465 for ; Wed, 30 Jan 2019 09:40:55 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2E98C2E475; Wed, 30 Jan 2019 09:40:55 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5C4C42E477 for ; Wed, 30 Jan 2019 09:40:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730319AbfA3Jkw (ORCPT ); Wed, 30 Jan 2019 04:40:52 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:38534 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfA3Jkw (ORCPT ); Wed, 30 Jan 2019 04:40:52 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 0BC9A25B813; Wed, 30 Jan 2019 20:40:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1548841245; bh=nJAiZ6zbJvXM8xOUn1U2tbIZzK1ZXt1D6ga7CfPNAto=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PnYicBeEhpeLN5b5jOa1D0N71olg1gwj8yEBQn3rhz6+qC7ST7okeAAauJSC6TQ9Y xZmYBfXZk5h7oLMuwj/LrA9u7s9HqDFMlqXcUgF+StbL7H145X+JjHm6DH5Rwqm3iD IwjDY30p9ClMAaWIhgaifS+XR4HSY7E/EqlecW6M= Received: by reginn.horms.nl (Postfix, from userid 7100) id 2ABEA9401EF; Wed, 30 Jan 2019 10:40:43 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Takeshi Kihara , Simon Horman Subject: [PATCH v2 1/6] clk: renesas: rcar-gen3: Parameterise Z and Z2 clock fixed divisor Date: Wed, 30 Jan 2019 10:40:24 +0100 Message-Id: <20190130094029.9604-2-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190130094029.9604-1-horms+renesas@verge.net.au> References: <20190130094029.9604-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Parameterise Z and Z2 clock fixed divisor to allow clocks with a fixed divisor other than 2, the value used by all such clocks supported to date. This is in preparation for supporting the Z2 clock on the R-Car E3 (r8a77990) SoC which has a fixed divisor of 4. Signed-off-by: Takeshi Kihara [simon: squashed several patches; rewrote changelog; added r8a774a1 change] Signed-off-by: Simon Horman --- drivers/clk/renesas/r8a774a1-cpg-mssr.c | 4 ++-- drivers/clk/renesas/r8a7795-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a7796-cpg-mssr.c | 5 +++-- drivers/clk/renesas/r8a77965-cpg-mssr.c | 2 +- drivers/clk/renesas/rcar-gen3-cpg.c | 23 ++++++++++++++--------- drivers/clk/renesas/rcar-gen3-cpg.h | 4 ++++ 6 files changed, 27 insertions(+), 16 deletions(-) diff --git a/drivers/clk/renesas/r8a774a1-cpg-mssr.c b/drivers/clk/renesas/r8a774a1-cpg-mssr.c index 10e852518870..103253bee055 100644 --- a/drivers/clk/renesas/r8a774a1-cpg-mssr.c +++ b/drivers/clk/renesas/r8a774a1-cpg-mssr.c @@ -71,8 +71,8 @@ static const struct cpg_core_clk r8a774a1_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A774A1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A774A1_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A774A1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A774A1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A774A1_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c index 86842c9fd314..919861e6d428 100644 --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c @@ -3,6 +3,7 @@ * r8a7795 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2015 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * * Based on clk-rcar-gen3.c * @@ -73,8 +74,8 @@ static struct cpg_core_clk r8a7795_core_clks[] __initdata = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A7795_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A7795_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7795_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a7796-cpg-mssr.c b/drivers/clk/renesas/r8a7796-cpg-mssr.c index 12c455859f2c..93983ec37e61 100644 --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c @@ -3,6 +3,7 @@ * r8a7796 Clock Pulse Generator / Module Standby and Software Reset * * Copyright (C) 2016 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * * Based on r8a7795-cpg-mssr.c * @@ -73,8 +74,8 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), - DEF_BASE("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2), + DEF_GEN3_Z("z", R8A7796_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), + DEF_GEN3_Z("z2", R8A7796_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL2, 2), DEF_FIXED("ztr", R8A7796_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A7796_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A7796_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/r8a77965-cpg-mssr.c b/drivers/clk/renesas/r8a77965-cpg-mssr.c index eb1cca58a1e1..f8f73558c1ec 100644 --- a/drivers/clk/renesas/r8a77965-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77965-cpg-mssr.c @@ -71,7 +71,7 @@ static const struct cpg_core_clk r8a77965_core_clks[] __initconst = { DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32), /* Core Clock Outputs */ - DEF_BASE("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0), + DEF_GEN3_Z("z", R8A77965_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2), DEF_FIXED("ztr", R8A77965_CLK_ZTR, CLK_PLL1_DIV2, 6, 1), DEF_FIXED("ztrd2", R8A77965_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1), DEF_FIXED("zt", R8A77965_CLK_ZT, CLK_PLL1_DIV2, 4, 1), diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index be2ccbd6d623..d50dd53121bb 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -81,6 +81,7 @@ struct cpg_z_clk { void __iomem *reg; void __iomem *kick_reg; unsigned long mask; + unsigned int fixed_div; }; #define to_z_clk(_hw) container_of(_hw, struct cpg_z_clk, hw) @@ -95,17 +96,18 @@ static unsigned long cpg_z_clk_recalc_rate(struct clk_hw *hw, val = readl(zclk->reg) & zclk->mask; mult = 32 - (val >> __ffs(zclk->mask)); - /* Factor of 2 is for fixed divider */ - return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, 32 * 2); + return DIV_ROUND_CLOSEST_ULL((u64)parent_rate * mult, + 32 * zclk->fixed_div); } static long cpg_z_clk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { - /* Factor of 2 is for fixed divider */ - unsigned long prate = *parent_rate / 2; + struct cpg_z_clk *zclk = to_z_clk(hw); + unsigned long prate; unsigned int mult; + prate = *parent_rate / zclk->fixed_div;; mult = div_u64(rate * 32ULL, prate); mult = clamp(mult, 1U, 32U); @@ -120,8 +122,8 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned int i; u32 val, kick; - /* Factor of 2 is for fixed divider */ - mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * 2, parent_rate); + mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div, + parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) @@ -167,7 +169,8 @@ static const struct clk_ops cpg_z_clk_ops = { static struct clk * __init cpg_z_clk_register(const char *name, const char *parent_name, void __iomem *reg, - unsigned long mask) + unsigned long mask, + unsigned int div) { struct clk_init_data init; struct cpg_z_clk *zclk; @@ -187,6 +190,7 @@ static struct clk * __init cpg_z_clk_register(const char *name, zclk->kick_reg = reg + CPG_FRQCRB; zclk->hw.init = &init; zclk->mask = mask; + zclk->fixed_div = div; /* PLLVCO x 1/div x SYS-CPU divider */ clk = clk_register(NULL, &zclk->hw); if (IS_ERR(clk)) @@ -565,11 +569,12 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, case CLK_TYPE_GEN3_Z: return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_ZFC_MASK); + base, CPG_FRQCRC_ZFC_MASK, core->div); case CLK_TYPE_GEN3_Z2: return cpg_z_clk_register(core->name, __clk_get_name(parent), - base, CPG_FRQCRC_Z2FC_MASK); + base, CPG_FRQCRC_Z2FC_MASK, + core->div); case CLK_TYPE_GEN3_OSC: /* diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h index f4fb6cf16688..60038e245e8b 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.h +++ b/drivers/clk/renesas/rcar-gen3-cpg.h @@ -3,6 +3,7 @@ * R-Car Gen3 Clock Pulse Generator * * Copyright (C) 2015-2018 Glider bvba + * Copyright (C) 2018 Renesas Electronics Corp. * */ @@ -48,6 +49,9 @@ enum rcar_gen3_clk_types { DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \ (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1)) +#define DEF_GEN3_Z(_name, _id, _type, _parent, _div) \ + DEF_BASE(_name, _id, _type, _parent, .div = _div) + struct rcar_gen3_cpg_pll_config { u8 extal_div; u8 pll1_mult; From patchwork Wed Jan 30 09:40:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10788019 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 1C45C184E for ; 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Wed, 30 Jan 2019 04:40:53 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 0DD9325BE91; Wed, 30 Jan 2019 20:40:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1548841245; bh=iEhMJruFvmlAneE/4lrBc0v0QceiwLpPvctbdnyfBLA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gT7GPU5mElWCYCYjyg6rwrLayHl1fxF7RM/nGkdHLPiGV1Kgeke+jrM96b3u3wBGC 27X6N5PhN96JlKX2bpzazkwnrKp7jGhtRkwyxHnvfr4wrrN4/wBV3L0XMg0Pq6nEpi IL7lzKd5MOktxVsuIrD0PhpIei1ip/3dAkNQEFbc= Received: by reginn.horms.nl (Postfix, from userid 7100) id 3F4EE940461; Wed, 30 Jan 2019 10:40:43 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Takeshi Kihara , Simon Horman Subject: [PATCH v2 2/6] clk: renesas: rcar-gen3: Support r8a77990 Z2 clock divider Date: Wed, 30 Jan 2019 10:40:25 +0100 Message-Id: <20190130094029.9604-3-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190130094029.9604-1-horms+renesas@verge.net.au> References: <20190130094029.9604-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Add support for the Z2 clock divider for the R-Car E3 (r8a77990) SoC. On this SoC the Z2 clock divider bits of the FRQCRC register are found at bit[12:8] rather than the more common location bit[4:0]. Signed-off-by: Takeshi Kihara [simon: reworked changelog] Signed-off-by: Simon Horman --- drivers/clk/renesas/rcar-gen3-cpg.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index d50dd53121bb..db3b2efb40e9 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -74,6 +74,7 @@ static void cpg_simple_notifier_register(struct raw_notifier_head *notifiers, #define CPG_FRQCRB_KICK BIT(31) #define CPG_FRQCRC 0x000000e0 #define CPG_FRQCRC_ZFC_MASK GENMASK(12, 8) +#define CPG_FRQCRC_Z2FC_SFT_8_MASK GENMASK(12, 8) #define CPG_FRQCRC_Z2FC_MASK GENMASK(4, 0) struct cpg_z_clk { @@ -365,6 +366,7 @@ static u32 cpg_quirks __initdata; #define PLL_ERRATA BIT(0) /* Missing PLL0/2/4 post-divider */ #define RCKCR_CKSEL BIT(1) /* Manual RCLK parent selection */ #define SD_SKIP_FIRST BIT(2) /* Skip first clock in SD table */ +#define Z2FC_BIT_MASK_SFT_8 BIT(3) /* Use Z2FC bit mask range to [12:8] */ static struct clk * __init cpg_sd_clk_register(const struct cpg_core_clk *core, void __iomem *base, const char *parent_name, @@ -445,6 +447,10 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { .soc_id = "r8a7796", .revision = "ES1.1", .data = (void *)SD_SKIP_FIRST, }, + { + .soc_id = "r8a77990", + .data = (void *)Z2FC_BIT_MASK_SFT_8, + }, { /* sentinel */ } }; @@ -572,6 +578,12 @@ struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, base, CPG_FRQCRC_ZFC_MASK, core->div); case CLK_TYPE_GEN3_Z2: + if (cpg_quirks & Z2FC_BIT_MASK_SFT_8) + return cpg_z_clk_register(core->name, + __clk_get_name(parent), base, + CPG_FRQCRC_Z2FC_SFT_8_MASK, + core->div); + return cpg_z_clk_register(core->name, __clk_get_name(parent), base, CPG_FRQCRC_Z2FC_MASK, core->div); From patchwork Wed Jan 30 09:40:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10788025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 22D31184E for ; Wed, 30 Jan 2019 09:40:56 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0FA0A2E475 for ; Wed, 30 Jan 2019 09:40:56 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 03F7F2E479; Wed, 30 Jan 2019 09:40:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AE7F22E475 for ; Wed, 30 Jan 2019 09:40:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730394AbfA3Jkz (ORCPT ); Wed, 30 Jan 2019 04:40:55 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:38534 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfA3Jkz (ORCPT ); Wed, 30 Jan 2019 04:40:55 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 2D9BF25BED6; Wed, 30 Jan 2019 20:40:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1548841245; bh=diRwoxuhVvnwarnNhYu7lBRcX76ElJSDh5g8v/SgZ8s=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=P9i8B2qW5MuB6guQCvDXs9VWzxguNcBBlhRgFl8wmUIVPK7jTuQ/fR8NbYggvqw2a xaxWg905IPzoNajN8Be8MtTuzsykjm/eW+qKx50F9koY9wFwha71WZMhy/RjQGZGdh JhImm/MiCA4g/b7dtsAYbTUzhvWihlCeD4Q4vm0c= Received: by reginn.horms.nl (Postfix, from userid 7100) id 51ADB940480; Wed, 30 Jan 2019 10:40:43 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Simon Horman Subject: [PATCH v2 3/6] clk: renesas: rcar-gen3: Support Z and Z2 clocks with high frequency parents Date: Wed, 30 Jan 2019 10:40:26 +0100 Message-Id: <20190130094029.9604-4-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190130094029.9604-1-horms+renesas@verge.net.au> References: <20190130094029.9604-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Support Z and Z2 clocks with parent frequencies greater than UINT32_MAX Hz (~4.29GHz). The DIV_ROUND_CLOSEST_ULL() macro accepts a 64bit numerator and 32bit denominator. This leads to truncation of the numerator, which is the Z or Z2 parent clock frequency in HZ, on platforms where frequency of that clock is greater than UINT32_MAX Hz. To resolve this problem the DIV_ROUND_CLOSEST() macro, which accepts the prevailing types of the numerator and denominator, is used. In this case the type of the numerator is unsigned long long (64 bit) and the type of the denominator is unsigned long (64bit on 64bit platforms and 32bit on 32bit platforms). This allows parents whose frequency is greater than UINT32_MAX Hz on 64bit platforms. This appears to be sufficient as this driver is only intended for use on 64bit systems. And in particular, the motivation for this change is to allow a 4.8GHz clock on the R-Car Gen3 E3 (r8a77990) SoC which is a 64bit platform. Signed-off-by: Simon Horman --- drivers/clk/renesas/rcar-gen3-cpg.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index db3b2efb40e9..d21fdeb520e1 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -123,8 +123,7 @@ static int cpg_z_clk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned int i; u32 val, kick; - mult = DIV_ROUND_CLOSEST_ULL(rate * 32ULL * zclk->fixed_div, - parent_rate); + mult = DIV_ROUND_CLOSEST(rate * 32ULL * zclk->fixed_div, parent_rate); mult = clamp(mult, 1U, 32U); if (readl(zclk->kick_reg) & CPG_FRQCRB_KICK) From patchwork Wed Jan 30 09:40:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10788029 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5197B184E for ; Wed, 30 Jan 2019 09:40:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3F7CD2E465 for ; Wed, 30 Jan 2019 09:40:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 340482E476; Wed, 30 Jan 2019 09:40:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DBDA82E475 for ; Wed, 30 Jan 2019 09:40:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728672AbfA3Jk4 (ORCPT ); Wed, 30 Jan 2019 04:40:56 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:38534 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfA3Jk4 (ORCPT ); Wed, 30 Jan 2019 04:40:56 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 3DF0B25BEE2; Wed, 30 Jan 2019 20:40:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1548841245; bh=t3mViI4BMFCFTed45UIRBwP1+G5Zs97zPipA2hsfmE8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aiejCFAZzvsxqqJuwfBahCDHWMncwPpfZSeVV7ejXezMDMcersDzHRBY+AjMKUO6G 4MTCCq7fezC7+sLlT17Aq7tjYM07GZn504J88Ow90B014cO2PN5TAfHMBq8reIpb/L OtpEzaGLc3NtfT4OiSqMHf6JveLlO+Jd6U94TmFI= Received: by reginn.horms.nl (Postfix, from userid 7100) id 62B1A940600; Wed, 30 Jan 2019 10:40:43 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Takeshi Kihara , Simon Horman Subject: [PATCH v2 4/6] clk: renesas: r8a77990: Add Z2 clock Date: Wed, 30 Jan 2019 10:40:27 +0100 Message-Id: <20190130094029.9604-5-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190130094029.9604-1-horms+renesas@verge.net.au> References: <20190130094029.9604-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Takeshi Kihara Adds support for R-Car E3 (r8a77990) Z2 clock. Signed-off-by: Takeshi Kihara [simon: reworked changelog] Signed-off-by: Simon Horman --- drivers/clk/renesas/r8a77990-cpg-mssr.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/clk/renesas/r8a77990-cpg-mssr.c b/drivers/clk/renesas/r8a77990-cpg-mssr.c index 9a278c75c918..05dc28e4ec5f 100644 --- a/drivers/clk/renesas/r8a77990-cpg-mssr.c +++ b/drivers/clk/renesas/r8a77990-cpg-mssr.c @@ -81,6 +81,7 @@ static const struct cpg_core_clk r8a77990_core_clks[] __initconst = { /* Core Clock Outputs */ DEF_FIXED("za2", R8A77990_CLK_ZA2, CLK_PLL0D24, 1, 1), DEF_FIXED("za8", R8A77990_CLK_ZA8, CLK_PLL0D8, 1, 1), + DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL0, 4), DEF_FIXED("ztr", R8A77990_CLK_ZTR, CLK_PLL1, 6, 1), DEF_FIXED("zt", R8A77990_CLK_ZT, CLK_PLL1, 4, 1), DEF_FIXED("zx", R8A77990_CLK_ZX, CLK_PLL1, 3, 1), From patchwork Wed Jan 30 09:40:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10788037 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 0C17C13B5 for ; Wed, 30 Jan 2019 09:41:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EBDBD2E476 for ; Wed, 30 Jan 2019 09:40:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DFFEB2E475; Wed, 30 Jan 2019 09:40:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9C63B2E475 for ; Wed, 30 Jan 2019 09:40:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729519AbfA3Jk7 (ORCPT ); Wed, 30 Jan 2019 04:40:59 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:38534 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfA3Jk7 (ORCPT ); Wed, 30 Jan 2019 04:40:59 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 5DA6A25BEE5; Wed, 30 Jan 2019 20:40:47 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1548841247; bh=eH5xe79FEpbYVrh06cEnNXrarYdO0U71TqiYXYNJeqw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=KlAHQcbWtoxqrQHWRZcpcuC5F1UnBUGysRREO4HbSw0ebV1kBhFQNkXOrAJFFujaz yJp1COMcfJt681uhpPLk9oSNKTy+V7DCf05op8mPRZU7z2x/GP1iX5ZtjTA4AADOu7 gPOJz7oLmbiwvfqXR6Mg2rNsHucxJoU0XTDo57mA= Received: by reginn.horms.nl (Postfix, from userid 7100) id 7D785940796; Wed, 30 Jan 2019 10:40:43 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Simon Horman Subject: [PATCH/RFT v2 5/6] clk: renesas: rcar-gen3: Support r8a7745 Z2 clock divider Date: Wed, 30 Jan 2019 10:40:28 +0100 Message-Id: <20190130094029.9604-6-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190130094029.9604-1-horms+renesas@verge.net.au> References: <20190130094029.9604-1-horms+renesas@verge.net.au> MIME-Version: 1.0 Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On the RZ/G2E (r8a7745) SoC the Z2FC bits of the RFQCRC register, which control the frequency division ratio for the Z2φ clock are located at bit[12:8] rather than the more common location bit[4:0]. This change is made with reference to the User's Manual v0.61. Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Simon Horman --- drivers/clk/renesas/rcar-gen3-cpg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/renesas/rcar-gen3-cpg.c b/drivers/clk/renesas/rcar-gen3-cpg.c index d21fdeb520e1..dfd2b9caeaf5 100644 --- a/drivers/clk/renesas/rcar-gen3-cpg.c +++ b/drivers/clk/renesas/rcar-gen3-cpg.c @@ -450,6 +450,10 @@ static const struct soc_device_attribute cpg_quirks_match[] __initconst = { .soc_id = "r8a77990", .data = (void *)Z2FC_BIT_MASK_SFT_8, }, + { + .soc_id = "r8a7745", + .data = (void *)Z2FC_BIT_MASK_SFT_8, + }, { /* sentinel */ } }; From patchwork Wed Jan 30 09:40:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Horman X-Patchwork-Id: 10788031 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5B68A184E for ; Wed, 30 Jan 2019 09:40:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 487272E465 for ; Wed, 30 Jan 2019 09:40:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3D12B2E477; Wed, 30 Jan 2019 09:40:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.7 required=2.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E34712E465 for ; Wed, 30 Jan 2019 09:40:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730411AbfA3Jk5 (ORCPT ); Wed, 30 Jan 2019 04:40:57 -0500 Received: from kirsty.vergenet.net ([202.4.237.240]:38534 "EHLO kirsty.vergenet.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726427AbfA3Jk5 (ORCPT ); Wed, 30 Jan 2019 04:40:57 -0500 Received: from reginn.horms.nl (watermunt.horms.nl [80.127.179.77]) by kirsty.vergenet.net (Postfix) with ESMTPA id 5C69325BEE4; Wed, 30 Jan 2019 20:40:47 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=verge.net.au; s=mail; t=1548841247; bh=nopU2/9+aKGh2eK7pnutWvSUEQ+2keJfLiSpR7qnVTE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=j1cvUH9Te/tPMwqHDcxbR0+cmDSnYIAAVBFP88SSlbEB26Ix7qDor/r2Plmi323+C VxXOZzhplAXYfP1dfuB8QXrd45rf+aCfUNMnIPnZdptnS9geUNruF5E2/L0i24PMFd XUvxtXr4hl2yIFpp9qnaNhxowB/12R+RRgGoBK0o= Received: by reginn.horms.nl (Postfix, from userid 7100) id 8FEB7940790; Wed, 30 Jan 2019 10:40:43 +0100 (CET) From: Simon Horman To: Geert Uytterhoeven Cc: Magnus Damm , linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Fabrizio Castro , Biju Das , Simon Horman Subject: [PATCH/RFT v2 6/6] clk: renesas: r8a7745: Implement Z2 as a variable clock Date: Wed, 30 Jan 2019 10:40:29 +0100 Message-Id: <20190130094029.9604-7-horms+renesas@verge.net.au> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190130094029.9604-1-horms+renesas@verge.net.au> References: <20190130094029.9604-1-horms+renesas@verge.net.au> Sender: linux-clk-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On the RZ/G2E (r8a7745) SoC the Z2 clock is not a fixed clock. Rather it is a clock with: * A parent of CLK_PLL0 running at 4.8GHz * A fixed divider of 4 * A variable divider controlled by the Z2FC bits of the RFQCRC register This can be described using the DEF_GEN3_Z with a clock type of CLK_TYPE_GEN3_Z2. This change is made with reference to the User's Manual v0.61. Fixes: 9127d54bb894 ("clk: renesas: cpg-mssr: Add R8A7745 support") Signed-off-by: Simon Horman --- drivers/clk/renesas/r8a7745-cpg-mssr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/renesas/r8a7745-cpg-mssr.c b/drivers/clk/renesas/r8a7745-cpg-mssr.c index 493874e5ebee..f2ea72d9d663 100644 --- a/drivers/clk/renesas/r8a7745-cpg-mssr.c +++ b/drivers/clk/renesas/r8a7745-cpg-mssr.c @@ -53,7 +53,7 @@ static const struct cpg_core_clk r8a7745_core_clks[] __initconst = { DEF_BASE("qspi", R8A7745_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2), DEF_BASE("rcan", R8A7745_CLK_RCAN, CLK_TYPE_GEN2_RCAN, CLK_USB_EXTAL), - DEF_FIXED("z2", R8A7745_CLK_Z2, CLK_PLL0, 1, 1), + DEF_GEN3_Z("z2", R8A77990_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL0, 4), DEF_FIXED("zg", R8A7745_CLK_ZG, CLK_PLL1, 6, 1), DEF_FIXED("zx", R8A7745_CLK_ZX, CLK_PLL1, 3, 1), DEF_FIXED("zs", R8A7745_CLK_ZS, CLK_PLL1, 6, 1),