From patchwork Tue Mar 28 05:02:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13190484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A68FEC76195 for ; Tue, 28 Mar 2023 05:02:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232126AbjC1FCj (ORCPT ); Tue, 28 Mar 2023 01:02:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232060AbjC1FCh (ORCPT ); Tue, 28 Mar 2023 01:02:37 -0400 Received: from mail-pl1-x64a.google.com (mail-pl1-x64a.google.com [IPv6:2607:f8b0:4864:20::64a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF5411FEC for ; Mon, 27 Mar 2023 22:02:35 -0700 (PDT) Received: by mail-pl1-x64a.google.com with SMTP id k1-20020a170902c40100b001a20f75cd40so7102993plk.22 for ; Mon, 27 Mar 2023 22:02:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679979755; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=9QQzDi7GpVjFTFh6qcWiIai3J9NNhOIoGlEpKZ27RWs=; b=mY/v2nMrskLnaRdL8PxIyDkfpE+DoOrXOIaNKRXjjXcQ5+mNG01/1daVWGMxdZUbSz 0X/zauNZwcX+8Zm3k68BG+RGNSdcyja88BeVBd5qr9clHstWPdC6E7QVdA/CzEJZ3x6e aNudBITsYYg6UWwx1hrbkk+0mqd9EcKbdQmwwLj+dhUC8xU7ewgY0AqEWLGdweSzFFOE RlCChVoMdONyXjxUodKiUa3YIxd3ObzDHBijJwUohG2hYQGaPZ73c4xVzEzbyljm1jCs gdlwBUkkHSYErzPUdO72NgBVOJcd9Ne+qcospZAp7J8A9l0/aUPU6bXD4zIzGv/f+o5d zMPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679979755; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=9QQzDi7GpVjFTFh6qcWiIai3J9NNhOIoGlEpKZ27RWs=; b=pU0QshBMUFQ9P5pNNg0Uclrrduc9NnWwxWbQXkr6ecLMoWmwYb6tOlfMsDOaPf1hOS ZQtcHQbprPDpjeZx7mP4V+ApSx0Wjbi5gVf03txxcaSJ1lTaznWFXiGRLViz/4kENf8J w/ZXE8A24dUk4WNe7V6DixJjhSK3mULb4dH5s638X44VsbJAvlnJ46d0O4gl4t3E//Mm CN+ccr5WqjIN7D7vuSsN98Ij0hOUkDfH5stOu62MjmWE9n/rKY7djPlfBj/3gRG31HGM hrhqDjzrBiLfImBlJz863bD7quPovVpeda4vDrP9uD6X4khImHXtRsOfNlh4YN5JP5hI JoiQ== X-Gm-Message-State: AAQBX9fojkd3Io9/RBdRCgm+Fdv7wpwHIQ656WeYSAiLhNxjZlBfhhc5 iSsmfoz8VfOOkyz+qPPPfl/S+y6SzQo= X-Google-Smtp-Source: AKy350Yz7WS3QMyCF1aufF2zTNYE4rEN3mngWZaZW0opNdJiV8W0yrSQVhWQ4SOZ/hvkC1C8UkUl6PsoecI= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a63:1714:0:b0:50b:18ac:fbea with SMTP id x20-20020a631714000000b0050b18acfbeamr3778876pgl.9.1679979755205; Mon, 27 Mar 2023 22:02:35 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 27 Mar 2023 22:02:29 -0700 In-Reply-To: <20230328050231.3008531-1-seanjc@google.com> Mime-Version: 1.0 References: <20230328050231.3008531-1-seanjc@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230328050231.3008531-2-seanjc@google.com> Subject: [kvm-unit-tests PATCH 1/3] x86: Add define for MSR_IA32_PRED_CMD's PRED_CMD_IBPB (bit 0) From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add a define for PRED_CMD_IBPB and use it to replace the open coded '1' in the nVMX library. Signed-off-by: Sean Christopherson --- lib/x86/msr.h | 1 + x86/vmexit.c | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/lib/x86/msr.h b/lib/x86/msr.h index c9869be5..29fff553 100644 --- a/lib/x86/msr.h +++ b/lib/x86/msr.h @@ -34,6 +34,7 @@ /* Intel MSRs. Some also available on other CPUs */ #define MSR_IA32_SPEC_CTRL 0x00000048 #define MSR_IA32_PRED_CMD 0x00000049 +#define PRED_CMD_IBPB BIT(0) #define MSR_IA32_PMC0 0x000004c1 #define MSR_IA32_PERFCTR0 0x000000c1 diff --git a/x86/vmexit.c b/x86/vmexit.c index b1eed8d1..2e8866e1 100644 --- a/x86/vmexit.c +++ b/x86/vmexit.c @@ -463,7 +463,7 @@ static int has_spec_ctrl(void) static void wr_ibpb_msr(void) { - wrmsr(MSR_IA32_PRED_CMD, 1); + wrmsr(MSR_IA32_PRED_CMD, PRED_CMD_IBPB); } static void toggle_cr0_wp(void) From patchwork Tue Mar 28 05:02:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13190485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1259BC76196 for ; Tue, 28 Mar 2023 05:02:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232140AbjC1FCl (ORCPT ); Tue, 28 Mar 2023 01:02:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41930 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229611AbjC1FCi (ORCPT ); Tue, 28 Mar 2023 01:02:38 -0400 Received: from mail-pl1-x649.google.com (mail-pl1-x649.google.com [IPv6:2607:f8b0:4864:20::649]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 67EAE2109 for ; Mon, 27 Mar 2023 22:02:37 -0700 (PDT) Received: by mail-pl1-x649.google.com with SMTP id e5-20020a17090301c500b001a1aa687e4bso7011580plh.17 for ; Mon, 27 Mar 2023 22:02:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1679979757; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:from:to:cc:subject:date:message-id:reply-to; bh=l30Bo4sseYT6mdSxEgWgPg1yNO2MfcdkDz2rkKS2SdU=; b=Wt78TPeZEgCHyu4d9zdIHXMOvryEqnRpb+HwloZGVwrDHTuKu7FunZSd7kmis8wVZv R97eJEhkSVHS/Lp2XQa5HqRnchMc35BXh4oggpCzXy13t9zTDYX4KGTwyqIa6C3/jf07 vsgSYGO4hH0+sNdq8MRvhLqvCh3kl5SRkXMd/N8FfoNe8WY8kkGsSTdLkgT42U2yP2wj z9lQWcE6hGtlX/+YCgUq6osTP9FrpzasqXYeVYkt6fH81V3iXBPzssDk0UZa1TIA1yK9 /MA8Yz/5aQafBUaoSbB256kHPyq6lxShXthn4jvG4LaKasiAce9DSZitctm4jUcb9plp kfbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1679979757; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:reply-to:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=l30Bo4sseYT6mdSxEgWgPg1yNO2MfcdkDz2rkKS2SdU=; b=27XGl/RimqtcmAe5JwONu0D9gXQmq5VSrzpsgOOmsCwvK8ukZH2bHqn+ENEhwROf1U PMBCMIfLrzAndpolN5iz6Co9AC1h3eUxH2EU4cxaPh0ZQKhHhNQjA5mtZGN8Ql1KIw5r uS0v6u7qwLqgWFeLKXGF2+aP2xqE5ddbWKIpxXwFvGkXFxp4TVdeha3rTaS2iPcsw2V5 Bhqx7p/IMdEC3VtKjTZywWDGd0/JUAQT5KadEd7jaTFJO7IWflYhvMgTowwx1kFA5EhI 0Rtat9BJkWqgLSObQMukTNk+ydZs/xb8PVcH0hFQE8H7M446e6YpPJw1sGjDS2xOl1/x 1T7Q== X-Gm-Message-State: AAQBX9ePPfSNes9UmuRlnjtkXMGU1L2g5xPcUcPTR+XWJzGn63q862BQ txzRYtLl1g3F50aVlMdVig4eM9aW88o= X-Google-Smtp-Source: AKy350aUdlrw4Pqu3hIjszPfWKHk80X8kwubH9Jjb7FGKp2I4b+whAllYWbumT4A4n7pLja32O0hpbp0cTw= X-Received: from zagreus.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:5c37]) (user=seanjc job=sendgmr) by 2002:a63:d958:0:b0:513:3030:10be with SMTP id e24-20020a63d958000000b00513303010bemr3230987pgj.3.1679979756945; Mon, 27 Mar 2023 22:02:36 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 27 Mar 2023 22:02:30 -0700 In-Reply-To: <20230328050231.3008531-1-seanjc@google.com> Mime-Version: 1.0 References: <20230328050231.3008531-1-seanjc@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230328050231.3008531-3-seanjc@google.com> Subject: [kvm-unit-tests PATCH 2/3] x86/msr: Add testcases for MSR_IA32_PRED_CMD and its IBPB command From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add test coverage to verify MSR_IA32_PRED_CMD is write-only, that it can be written with '0' (nop command) and '1' (IBPB command) when IBPB is supported by the CPU (SPEC_CTRL on Intel, IBPB on AMD), and that writing any other bit (1-63) triggers a #GP due to the bits/commands being reserved. Signed-off-by: Sean Christopherson --- x86/msr.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/x86/msr.c b/x86/msr.c index 97cf5987..13cb6391 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -85,6 +85,15 @@ static void test_msr_rw(u32 msr, const char *name, unsigned long long val) __test_msr_rw(msr, name, val, 0); } +static void test_wrmsr(u32 msr, const char *name, unsigned long long val) +{ + unsigned char vector = wrmsr_safe(msr, val); + + report(!vector, + "Expected success on WRSMR(%s, 0x%llx), got vector %d", + name, val, vector); +} + static void test_wrmsr_fault(u32 msr, const char *name, unsigned long long val) { unsigned char vector = wrmsr_safe(msr, val); @@ -271,6 +280,23 @@ static void test_x2apic_msrs(void) __test_x2apic_msrs(true); } +static void test_cmd_msrs(void) +{ + int i; + + test_rdmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD"); + if (this_cpu_has(X86_FEATURE_SPEC_CTRL) || + this_cpu_has(X86_FEATURE_AMD_IBPB)) { + test_wrmsr(MSR_IA32_PRED_CMD, "PRED_CMD", 0); + test_wrmsr(MSR_IA32_PRED_CMD, "PRED_CMD", PRED_CMD_IBPB); + } else { + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", 0); + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", PRED_CMD_IBPB); + } + for (i = 1; i < 64; i++) + test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", BIT_ULL(i)); +} + int main(int ac, char **av) { /* @@ -283,6 +309,7 @@ int main(int ac, char **av) test_misc_msrs(); test_mce_msrs(); test_x2apic_msrs(); + test_cmd_msrs(); } return report_summary(); From patchwork Tue Mar 28 05:02:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sean Christopherson X-Patchwork-Id: 13190486 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25513C761A6 for ; Tue, 28 Mar 2023 05:02:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232200AbjC1FCn (ORCPT ); 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Mon, 27 Mar 2023 22:02:38 -0700 (PDT) Reply-To: Sean Christopherson Date: Mon, 27 Mar 2023 22:02:31 -0700 In-Reply-To: <20230328050231.3008531-1-seanjc@google.com> Mime-Version: 1.0 References: <20230328050231.3008531-1-seanjc@google.com> X-Mailer: git-send-email 2.40.0.348.gf938b09366-goog Message-ID: <20230328050231.3008531-4-seanjc@google.com> Subject: [kvm-unit-tests PATCH 3/3] x86/msr: Add testcases for MSR_IA32_FLUSH_CMD and its L1D_FLUSH command From: Sean Christopherson To: Paolo Bonzini Cc: kvm@vger.kernel.org, Sean Christopherson Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Add test coverage to verify MSR_IA32_FLUSH_CMD is write-only, that it can be written with '0' (nop command) and '1' (L1D flush command) when the L1D flush command is suported, and that writing any other bit (1-63) triggers a #GP due to the bits/commands being reserved. Signed-off-by: Sean Christopherson --- lib/x86/msr.h | 3 +++ lib/x86/processor.h | 1 + x86/msr.c | 11 +++++++++++ 3 files changed, 15 insertions(+) diff --git a/lib/x86/msr.h b/lib/x86/msr.h index 29fff553..0e3fd037 100644 --- a/lib/x86/msr.h +++ b/lib/x86/msr.h @@ -36,6 +36,9 @@ #define MSR_IA32_PRED_CMD 0x00000049 #define PRED_CMD_IBPB BIT(0) +#define MSR_IA32_FLUSH_CMD 0x0000010b +#define L1D_FLUSH BIT(0) + #define MSR_IA32_PMC0 0x000004c1 #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 diff --git a/lib/x86/processor.h b/lib/x86/processor.h index aed6d180..e32c84f7 100644 --- a/lib/x86/processor.h +++ b/lib/x86/processor.h @@ -246,6 +246,7 @@ static inline bool is_intel(void) #define X86_FEATURE_SHSTK (CPUID(0x7, 0, ECX, 7)) #define X86_FEATURE_IBT (CPUID(0x7, 0, EDX, 20)) #define X86_FEATURE_SPEC_CTRL (CPUID(0x7, 0, EDX, 26)) +#define X86_FEATURE_FLUSH_L1D (CPUID(0x7, 0, EDX, 28)) #define X86_FEATURE_ARCH_CAPABILITIES (CPUID(0x7, 0, EDX, 29)) #define X86_FEATURE_PKS (CPUID(0x7, 0, ECX, 31)) diff --git a/x86/msr.c b/x86/msr.c index 13cb6391..f6be2be7 100644 --- a/x86/msr.c +++ b/x86/msr.c @@ -295,6 +295,17 @@ static void test_cmd_msrs(void) } for (i = 1; i < 64; i++) test_wrmsr_fault(MSR_IA32_PRED_CMD, "PRED_CMD", BIT_ULL(i)); + + test_rdmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD"); + if (this_cpu_has(X86_FEATURE_FLUSH_L1D)) { + test_wrmsr(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", 0); + test_wrmsr(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", L1D_FLUSH); + } else { + test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", 0); + test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", L1D_FLUSH); + } + for (i = 1; i < 64; i++) + test_wrmsr_fault(MSR_IA32_FLUSH_CMD, "FLUSH_CMD", BIT_ULL(i)); } int main(int ac, char **av)