From patchwork Wed Mar 29 22:24:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13193281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83591C74A5B for ; Wed, 29 Mar 2023 22:25:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9174C10E53E; Wed, 29 Mar 2023 22:25:06 +0000 (UTC) Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by gabe.freedesktop.org (Postfix) with ESMTPS id B73F210E1A4 for ; Wed, 29 Mar 2023 22:25:03 +0000 (UTC) Received: by mail-lf1-x12b.google.com with SMTP id c29so22171046lfv.3 for ; Wed, 29 Mar 2023 15:25:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680128702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=B/Gpn4+VfV0wCWDJ0YpMb1Da+cHbqOuOEqeu7hzsijo=; b=nDADtY1MNhUxuY6EGjRKHWNhT2q7zQLaqK91ZE3RoXB5dqE+denbqh6V+w/pvDckIm ziA9uOqyFRqDctqvJ0yJQw5G79+ToeSVEm39pRsnzbyrR/LnQIcpwg5GCPEf/2qZItoi nrue8Rko7VdFUgdueiy+rgNwvp/HhA0IKFOjSeqS67GN/yAZfaJwfTlEp9AyAmGsqyTV ZyC/6AVStmyAVIpo4L38QUyCsZH6Y00erOKa4UCbc5oNxFIduWa85OGcn+7hNK7eTydm B+Dqyl+FYHELJE6ttVsFKjqPU8PvhGDysthng0zkvjYiI0brRx1lWgacCTi5z6gBhg1e EI4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680128702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=B/Gpn4+VfV0wCWDJ0YpMb1Da+cHbqOuOEqeu7hzsijo=; b=b7Qfs4wil7uvXz6BXkiskqxQLD5QHjmgtIclEvcHbjPWrH+YBhyVkLmoUaVhOXibwb abBwasbGk1KaZu2kx6/4GE4p/0xBdSuP6Ue056JyPbOF80J3Lq6YQeedJmR2cmDyOgo8 Osqd7B2+n/1phR2KBq4P3H2pVfFI7rSews2oJYW76i1BWgFocA9QiM0XR9hy50iFKde0 kHlZO4yfPFNuaRCLOIAZejX7wobGJwkZqvBiZbbDpD+m0AVg1scizR8Isjz4oxiDlOPg K5HG/7mn824hEsfJOxnCQVzJE1RcoAk/FSFd5SjGjeDurnWjRwad5NfAgJ6i9UFedy7x QP+w== X-Gm-Message-State: AAQBX9fOuBcFtE3XrJPrOetx/ky6+av+cZDqmrAuQYdFa8aU/ZBNoIL3 tnVKoQgwwnOyJG+8A2LMEAzeEQ== X-Google-Smtp-Source: AKy350aKz0eSaRFpT7uZkTxnfGftY4OCRs6FePvYdaJqqR04XYMczWlf18G1+The6TPPmvj8l+u+vQ== X-Received: by 2002:ac2:51cc:0:b0:4cc:a107:4227 with SMTP id u12-20020ac251cc000000b004cca1074227mr1131212lfm.22.1680128701854; Wed, 29 Mar 2023 15:25:01 -0700 (PDT) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y26-20020ac255ba000000b004e9b307d2c8sm4724226lfg.238.2023.03.29.15.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 15:25:01 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Subject: [RFC PATCH 1/3] dt-bindings: display/msm/gpu: allow specifying MX domain A5xx Date: Thu, 30 Mar 2023 01:24:58 +0300 Message-Id: <20230329222500.1131836-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230329222500.1131836-1-dmitry.baryshkov@linaro.org> References: <20230329222500.1131836-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Some a5xx Adreno devices might need additional power domains to handle voltage scaling. While we do not (yet) have support for CPR3 providing voltage scaling, allow specifying MX domain to scale the memory cell voltage. Signed-off-by: Dmitry Baryshkov Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index d4191cca71fb..4dc1f6b2cdbf 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -78,7 +78,14 @@ properties: type: object power-domains: - maxItems: 1 + minItems: 1 + maxItems: 2 + + power-domain-names: + items: + - const: gx + - const: mx + minItems: 1 zap-shader: type: object From patchwork Wed Mar 29 22:24:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13193280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7744CC6FD18 for ; Wed, 29 Mar 2023 22:25:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4CAA110E1A7; Wed, 29 Mar 2023 22:25:06 +0000 (UTC) Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by gabe.freedesktop.org (Postfix) with ESMTPS id BAF1610E1A7 for ; Wed, 29 Mar 2023 22:25:04 +0000 (UTC) Received: by mail-lf1-x135.google.com with SMTP id k37so22201183lfv.0 for ; Wed, 29 Mar 2023 15:25:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680128702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XvOicm7FSZsvoLM+I7eZyYxaJPBR6NHXblQQPNco0kQ=; b=wMNTntBtw3JbTujEgRlvIK1ugsDeViUl3qgk6tzLyCNzeOSCIpPdJlk4I4ZNDMthb/ AOX3vvAr8/YUaGuvgou1JQShkvM+HTeh9Dlk5BK99T5N5VIENL0fP9By1KEgWziqA4N7 JzOSptsOGmJwUe+TJyqdNisp45Z9JFoy8z0Vn6BhsVitIrn2STBQY8Rq93pOEjuJo/Mi MwxqYbpUW1uhvQ1a5R7vzHPBs0M49qyPDg0l8xTcotdc/jupwSQuhWwVs+POh5EOJYbP /TRYVXC7ToT1tP301fMTyzCk7qgy6AFW1JNDonwO9hyngBswFUUaooNEich/MQxDijYx v5kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680128702; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XvOicm7FSZsvoLM+I7eZyYxaJPBR6NHXblQQPNco0kQ=; b=nQElkN2nhWoYbp/piR6HKgIUqRYAgNU6kGLHTppfFDHHcATkHQHIUs7ixtGmP/OGst hZP+OKNRj30mw/uPq/dg78Xt3ZnY3Pt+1fiievTFyGaKuDToyl0BJ77dL2CtSt7GCyea Zvegan2PC4ts+kaoISSKZlHeD7fBUS1Prwlkoj+Vy4+BoyhAfP4wxEy2ZepqaovUwXSy Tlrp67e9yODq0UUbLBBT+pGNPcA0zrUNom2+0iR555TVW+Xq4nSbndXTtuA2Lnp6lZ3F 2r3G+MZ//WvVArOenO4jDwtTFQHAopQjQBubeiIEn/A6/0d3iT5e9Qe3Qg+2pUh5FrXN QYbQ== X-Gm-Message-State: AAQBX9eM260615s3+y/I2SqFSrhDffxsKcS+M4TzkWCCu7+gb9GPiO1W lIU+iIY/sf+GsindqjzLz3AQOQ== X-Google-Smtp-Source: AKy350Yafz+44RhjayuM2tQER3bgUHCtIb4t+86yGSe52bNOnaGogVbbHxOlWGD5ykjwJGQWJoEEYg== X-Received: by 2002:ac2:46d4:0:b0:4e8:200:132b with SMTP id p20-20020ac246d4000000b004e80200132bmr6084675lfo.62.1680128702692; Wed, 29 Mar 2023 15:25:02 -0700 (PDT) Received: from eriador.lan (dzccz6yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y26-20020ac255ba000000b004e9b307d2c8sm4724226lfg.238.2023.03.29.15.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 15:25:02 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Subject: [RFC PATCH 2/3] drm/msm/a5xx: scale MX domain following the frequncy changes Date: Thu, 30 Mar 2023 01:24:59 +0300 Message-Id: <20230329222500.1131836-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230329222500.1131836-1-dmitry.baryshkov@linaro.org> References: <20230329222500.1131836-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" For some a5xx Adrenos we have to specify both GX and MX power domains. GX is used to power up the GPU clocks and logic. MX is used for scaling voltage of memory cells. In case the DT specifies several (GX, MX) power domains, none will be bound by the core. We have to manage GX manually. Also make sure that the MX domain is resumed and scaled to the proper performance state following the desired frequency. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 52 +++++++++++++++++++++++++++ drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 3 ++ 2 files changed, 55 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 0372f8908202..36b3d11dd5b0 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include "msm_gem.h" #include "msm_mmu.h" @@ -1053,6 +1054,13 @@ static void a5xx_destroy(struct msm_gpu *gpu) } adreno_gpu_cleanup(adreno_gpu); + + if (a5xx_gpu->mx_link) + device_link_del(a5xx_gpu->mx_link); + + if (a5xx_gpu->gxpd) + dev_pm_domain_detach(a5xx_gpu->gxpd, true); + kfree(a5xx_gpu); } @@ -1339,8 +1347,15 @@ static void a5xx_dump(struct msm_gpu *gpu) static int a5xx_pm_resume(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu); int ret; + if (a5xx_gpu->gxpd) { + ret = pm_runtime_resume_and_get(a5xx_gpu->gxpd); + if (ret < 0) + return ret; + } + /* Turn on the core power */ ret = msm_gpu_pm_resume(gpu); if (ret) @@ -1414,6 +1429,9 @@ static int a5xx_pm_suspend(struct msm_gpu *gpu) if (ret) return ret; + if (a5xx_gpu->gxpd) + pm_runtime_put(a5xx_gpu->gxpd); + if (a5xx_gpu->has_whereami) for (i = 0; i < gpu->nr_rings; i++) a5xx_gpu->shadow[i] = 0; @@ -1762,6 +1780,40 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) a5xx_gpu->lm_leakage = 0x4E001A; + /* + * If the device has several power domain (gx and mx), none are attached by the core. + */ + if (!pdev->dev.pm_domain) { + struct device **opp_virt_dev; + struct device *pd; + + /* FIXME: add cpr once it is supported */ + static const char *genpd_names[] = { "mx", NULL }; + + pd = dev_pm_domain_attach_by_name(&pdev->dev, "gx"); + if (IS_ERR(pd)) + return ERR_CAST(pd); + + /* GX is required for GPU to function */ + if (pd == NULL) + return ERR_PTR(-EINVAL); + + a5xx_gpu->gxpd = pd; + + ret = devm_pm_opp_attach_genpd(&pdev->dev, genpd_names, &opp_virt_dev); + if (ret) { + dev_pm_domain_detach(a5xx_gpu->gxpd, true); + return ERR_PTR(ret); + } + + a5xx_gpu->mx_link = device_link_add(&pdev->dev, opp_virt_dev[0], + DL_FLAG_RPM_ACTIVE | + DL_FLAG_PM_RUNTIME | + DL_FLAG_STATELESS); + if (!a5xx_gpu->mx_link) + return ERR_PTR(-ENODEV); + } + check_speed_bin(&pdev->dev); nr_rings = 4; diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h index c7187bcc5e90..36e910397c14 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.h @@ -44,6 +44,9 @@ struct a5xx_gpu { /* True if the microcode supports the WHERE_AM_I opcode */ bool has_whereami; + + struct device *gxpd; + struct device_link *mx_link; }; #define to_a5xx_gpu(x) container_of(x, struct a5xx_gpu, base) From patchwork Wed Mar 29 22:25:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 13193282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 93697C6FD18 for ; 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[2001:14ba:a085:4d00::8a5]) by smtp.gmail.com with ESMTPSA id y26-20020ac255ba000000b004e9b307d2c8sm4724226lfg.238.2023.03.29.15.25.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Mar 2023 15:25:03 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Clark , Sean Paul , Abhinav Kumar , Rob Herring , Krzysztof Kozlowski Subject: [RFC PATCH 3/3] arm64: dts: qcom: specify power domains for the GPU Date: Thu, 30 Mar 2023 01:25:00 +0300 Message-Id: <20230329222500.1131836-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230329222500.1131836-1-dmitry.baryshkov@linaro.org> References: <20230329222500.1131836-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, Stephen Boyd , freedreno@lists.freedesktop.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" The GPU on msm8996 is powered on by several power domains. Add configuration for the GFX CPR and MX domains. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8996.dtsi | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi index 905678e7175d..ff4fb30f9075 100644 --- a/arch/arm64/boot/dts/qcom/msm8996.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi @@ -521,6 +521,10 @@ rpmpd_opp5: opp5 { rpmpd_opp6: opp6 { opp-level = <6>; }; + + rpmpd_opp7: opp7 { + opp-level = <7>; + }; }; }; }; @@ -1228,7 +1232,8 @@ gpu: gpu@b00000 { interconnects = <&bimc MASTER_GRAPHICS_3D &bimc SLAVE_EBI_CH0>; interconnect-names = "gfx-mem"; - power-domains = <&mmcc GPU_GX_GDSC>; + power-domains = <&mmcc GPU_GX_GDSC>, <&rpmpd MSM8996_VDDMX>; + power-domain-names = "gx", "mx"; iommus = <&adreno_smmu 0>; nvmem-cells = <&speedbin_efuse>; @@ -1251,30 +1256,37 @@ gpu_opp_table: opp-table { opp-624000000 { opp-hz = /bits/ 64 <624000000>; opp-supported-hw = <0x09>; + required-opps = <&rpmpd_opp7>; }; opp-560000000 { opp-hz = /bits/ 64 <560000000>; opp-supported-hw = <0x0d>; + required-opps = <&rpmpd_opp7>; }; opp-510000000 { opp-hz = /bits/ 64 <510000000>; opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp5>; }; opp-401800000 { opp-hz = /bits/ 64 <401800000>; opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp5>; }; opp-315000000 { opp-hz = /bits/ 64 <315000000>; opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp4>; }; opp-214000000 { opp-hz = /bits/ 64 <214000000>; opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp4>; }; opp-133000000 { opp-hz = /bits/ 64 <133000000>; opp-supported-hw = <0xff>; + required-opps = <&rpmpd_opp4>; }; };