From patchwork Fri Mar 31 06:18:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13195248 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83704C77B6F for ; Fri, 31 Mar 2023 06:18:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230118AbjCaGSq (ORCPT ); Fri, 31 Mar 2023 02:18:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229760AbjCaGSm (ORCPT ); Fri, 31 Mar 2023 02:18:42 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01D322139; Thu, 30 Mar 2023 23:18:41 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32V4UlgL001134; Fri, 31 Mar 2023 06:18:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references; s=qcppdkim1; bh=raJSyLbuj6AZNZQxvZzHT259us+hxzpDGHg3diYclz8=; b=jY0fRKUMHgi/3elVtiIxaB/AOwZFkZnQ5xGyBra4f9FNcxZTk29lavCIdxy3Ig0qsmE4 Rn1GfxqE4wdrrh9z5cPwgrTvgn0fAvWUBdFNuIS4ORAsQgj2uSeYq89520ETLXTEm3cu qToyCKGvpgYZmc93IP/F3umwr6ndCf2DbSPI6Ko010zQUJTTM6PArbJSJeMhu4TYbxsW NBbRMnXeBgowvscpP1lreZku7BAIoCLyrrJdKl0VUuNfjUC6+jt5KAFvSvwjLwKA5MiL Ou73vdIi0yPUaPSehh0//8uUY8SWP8t/XBFJ/goqOFD+V9BMtNuog/ClqbRMbetJbL+A dQ== Received: from apblrppmta02.qualcomm.com (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com [103.229.18.19]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pn934tjbc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 31 Mar 2023 06:18:35 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32V6IV6x013884; Fri, 31 Mar 2023 06:18:32 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3pht1knm22-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 31 Mar 2023 06:18:31 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32V6IV8r013872; Fri, 31 Mar 2023 06:18:31 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 32V6IVW4013871; Fri, 31 Mar 2023 06:18:31 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id CB1F54EED; Fri, 31 Mar 2023 11:48:30 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v5 1/5] dt-bindings: PCI: qcom: Add SDX65 SoC Date: Fri, 31 Mar 2023 11:48:18 +0530 Message-Id: <1680243502-23744-2-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1680243502-23744-1-git-send-email-quic_rohiagar@quicinc.com> References: <1680243502-23744-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1q_FV2AIgQxvTvO0hAKmXc66jEc0WDpb X-Proofpoint-ORIG-GUID: 1q_FV2AIgQxvTvO0hAKmXc66jEc0WDpb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-31_02,2023-03-30_04,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxlogscore=783 clxscore=1011 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303310050 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add PCIe EP compatible string for SDX65 SoC. Signed-off-by: Rohit Agarwal Acked-by: Krzysztof Kozlowski Reviewed-by: Manivannan Sadhasivam --- Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index 89cfdee..096540b 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -13,6 +13,7 @@ properties: compatible: enum: - qcom,sdx55-pcie-ep + - qcom,sdx65-pcie-ep - qcom,sm8450-pcie-ep reg: @@ -109,6 +110,7 @@ allOf: contains: enum: - qcom,sdx55-pcie-ep + - qcom,sdx65-pcie-ep then: properties: clocks: From patchwork Fri Mar 31 06:18:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13195247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A4B4C77B6E for ; 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Fri, 31 Mar 2023 06:18:35 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 32V6IWdK013907; Fri, 31 Mar 2023 06:18:32 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3pht1knm28-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 31 Mar 2023 06:18:32 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32V6IV8t013872; Fri, 31 Mar 2023 06:18:32 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 32V6IVC3013882; Fri, 31 Mar 2023 06:18:32 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 1DA404F33; Fri, 31 Mar 2023 11:48:31 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v5 2/5] ARM: dts: qcom: sdx65: Add support for PCIe PHY Date: Fri, 31 Mar 2023 11:48:19 +0530 Message-Id: <1680243502-23744-3-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1680243502-23744-1-git-send-email-quic_rohiagar@quicinc.com> References: <1680243502-23744-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: KMeU-KtJCqGGF-9LM2blQoUkXinbaht8 X-Proofpoint-GUID: KMeU-KtJCqGGF-9LM2blQoUkXinbaht8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-31_02,2023-03-30_04,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1015 suspectscore=0 phishscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303310050 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add devicetree support for PCIe PHY used in SDX65 platform. This PHY is used by the PCIe EP controller. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx65.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 192f9f9..084daf8 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -293,6 +293,37 @@ status = "disabled"; }; + pcie_phy: phy@1c06000 { + compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; + reg = <0x01c06000 0x2000>; + + clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_RCHNG_PHY_CLK>, + <&gcc GCC_PCIE_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + resets = <&gcc GCC_PCIE_PHY_BCR>; + reset-names = "phy"; + + assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>; + assigned-clock-rates = <100000000>; + + power-domains = <&gcc PCIE_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + tcsr_mutex: hwlock@1f40000 { compatible = "qcom,tcsr-mutex"; reg = <0x01f40000 0x40000>; From patchwork Fri Mar 31 06:18:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13195251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1ADD1C77B62 for ; Fri, 31 Mar 2023 06:19:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230173AbjCaGTJ (ORCPT ); Fri, 31 Mar 2023 02:19:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57706 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230138AbjCaGSv (ORCPT ); Fri, 31 Mar 2023 02:18:51 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 330E165AD; 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Signed-off-by: Rohit Agarwal Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx65.dtsi | 56 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index 084daf8..7597365 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -293,6 +294,56 @@ status = "disabled"; }; + pcie_ep: pcie-ep@1c00000 { + compatible = "qcom,sdx65-pcie-ep", "qcom,sdx55-pcie-ep"; + reg = <0x01c00000 0x3000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40200000 0x100000>, + <0x01c03000 0x3000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "addr_space", + "mmio"; + + qcom,perst-regs = <&tcsr 0xb258 0xb270>; + + clocks = <&gcc GCC_PCIE_AUX_CLK>, + <&gcc GCC_PCIE_CFG_AHB_CLK>, + <&gcc GCC_PCIE_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_SLV_AXI_CLK>, + <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>, + <&gcc GCC_PCIE_SLEEP_CLK>, + <&gcc GCC_PCIE_0_CLKREF_EN>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "sleep", + "ref"; + + interrupts = , + ; + interrupt-names = "global", "doorbell"; + + resets = <&gcc GCC_PCIE_BCR>; + reset-names = "core"; + + power-domains = <&gcc PCIE_GDSC>; + + phys = <&pcie_phy>; + phy-names = "pcie-phy"; + + max-link-speed = <3>; + num-lanes = <2>; + + status = "disabled"; + }; + pcie_phy: phy@1c06000 { compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy"; reg = <0x01c06000 0x2000>; @@ -330,6 +381,11 @@ #hwlock-cells = <1>; }; + tcsr: syscon@1fcb000 { + compatible = "qcom,sdx65-tcsr", "syscon"; + reg = <0x01fc0000 0x1000>; + }; + remoteproc_mpss: remoteproc@4080000 { compatible = "qcom,sdx55-mpss-pas"; reg = <0x04080000 0x4040>; From patchwork Fri Mar 31 06:18:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13195249 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 35D84C77B6D for ; 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While at it, updating status as last property for each node. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index ed98c83..70720e6 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -245,6 +245,13 @@ status = "okay"; }; +&pcie_phy { + vdda-phy-supply = <&vreg_l1b_1p2>; + vdda-pll-supply = <&vreg_l4b_0p88>; + + status = "okay"; +}; + &qpic_bam { status = "okay"; }; @@ -265,8 +272,9 @@ }; &remoteproc_mpss { - status = "okay"; memory-region = <&mpss_adsp_mem>; + + status = "okay"; }; &usb { @@ -278,14 +286,16 @@ }; &usb_hsphy { - status = "okay"; vdda-pll-supply = <&vreg_l4b_0p88>; vdda33-supply = <&vreg_l10b_3p08>; vdda18-supply = <&vreg_l5b_1p8>; + + status = "okay"; }; &usb_qmpphy { - status = "okay"; vdda-phy-supply = <&vreg_l4b_0p88>; vdda-pll-supply = <&vreg_l1b_1p2>; + + status = "okay"; }; From patchwork Fri Mar 31 06:18:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rohit Agarwal X-Patchwork-Id: 13195250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 76D49C77B60 for ; Fri, 31 Mar 2023 06:18:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230132AbjCaGSu (ORCPT ); Fri, 31 Mar 2023 02:18:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230047AbjCaGSn (ORCPT ); Fri, 31 Mar 2023 02:18:43 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 298CE3C20; Thu, 30 Mar 2023 23:18:43 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32V5jFmJ019985; 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Fri, 31 Mar 2023 06:18:33 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTPS id 3pht1knm2n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NO); Fri, 31 Mar 2023 06:18:33 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 32V6IWid013895; Fri, 31 Mar 2023 06:18:32 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-rohiagar-hyd.qualcomm.com [10.213.106.138]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 32V6IWLH013915; Fri, 31 Mar 2023 06:18:32 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3970568) id 0746B4EED; Fri, 31 Mar 2023 11:48:32 +0530 (+0530) From: Rohit Agarwal To: agross@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org, bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, robh@kernel.org, krzysztof.kozlowski+dt@linaro.org, manivannan.sadhasivam@linaro.org Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Rohit Agarwal Subject: [PATCH v5 5/5] ARM: dts: qcom: sdx65-mtp: Enable PCIe EP Date: Fri, 31 Mar 2023 11:48:22 +0530 Message-Id: <1680243502-23744-6-git-send-email-quic_rohiagar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1680243502-23744-1-git-send-email-quic_rohiagar@quicinc.com> References: <1680243502-23744-1-git-send-email-quic_rohiagar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: HAc_AtjRW_6fXFm_xABy5V8BVs6rAu6j X-Proofpoint-ORIG-GUID: HAc_AtjRW_6fXFm_xABy5V8BVs6rAu6j X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-31_02,2023-03-30_04,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 impostorscore=0 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxlogscore=685 clxscore=1015 priorityscore=1501 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2303310050 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Enable PCIe Endpoint controller on the SDX65 MTP board based on Qualcomm SDX65 platform. Signed-off-by: Rohit Agarwal Reviewed-by: Konrad Dybcio --- arch/arm/boot/dts/qcom-sdx65-mtp.dts | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 70720e6..96da625 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -245,6 +245,18 @@ status = "okay"; }; +&pcie_ep { + pinctrl-0 = <&pcie_ep_clkreq_default + &pcie_ep_perst_default + &pcie_ep_wake_default>; + pinctrl-names = "default"; + + reset-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; + + status = "okay"; +}; + &pcie_phy { vdda-phy-supply = <&vreg_l1b_1p2>; vdda-pll-supply = <&vreg_l4b_0p88>; @@ -277,6 +289,29 @@ status = "okay"; }; +&tlmm { + pcie_ep_clkreq_default: pcie-ep-clkreq-default-state { + pins = "gpio56"; + function = "pcie_clkreq"; + drive-strength = <2>; + bias-disable; + }; + + pcie_ep_perst_default: pcie-ep-perst-default-state { + pins = "gpio57"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + pcie_ep_wake_default: pcie-ep-wake-default-state { + pins = "gpio53"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &usb { status = "okay"; };