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Mon, 3 Apr 2023 09:48:00 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Peng Fan , Jacky Bai Subject: [PATCH V3 1/7] clk: imx: fracn-gppll: fix the rate table Date: Mon, 3 Apr 2023 17:52:54 +0800 Message-Id: <20230403095300.3386988-2-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230403095300.3386988-1-peng.fan@oss.nxp.com> References: <20230403095300.3386988-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI2P153CA0034.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::17) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|AS8PR04MB8070:EE_ X-MS-Office365-Filtering-Correlation-Id: 196156e4-af61-43fe-3ac4-08db342882f4 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Fixes: c196175acdd3 ("clk: imx: clk-fracn-gppll: Add more freq config for video pll") Fixes: 044034efbeea ("clk: imx: clk-fracn-gppll: fix mfd value") Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index a2aaa14fc1ae..ec50c41e2a4c 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -60,18 +60,20 @@ struct clk_fracn_gppll { }; /* - * Fvco = Fref * (MFI + MFN / MFD) - * Fout = Fvco / (rdiv * odiv) + * Fvco = (Fref / rdiv) * (MFI + MFN / MFD) + * Fout = Fvco / odiv + * The (Fref / rdiv) should be in range 20MHz to 40MHz + * The Fvco should be in range 2.5Ghz to 5Ghz */ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { - PLL_FRACN_GP(650000000U, 81, 0, 1, 0, 3), + PLL_FRACN_GP(650000000U, 162, 50, 100, 0, 6), PLL_FRACN_GP(594000000U, 198, 0, 1, 0, 8), - PLL_FRACN_GP(560000000U, 70, 0, 1, 0, 3), - PLL_FRACN_GP(498000000U, 83, 0, 1, 0, 4), + PLL_FRACN_GP(560000000U, 140, 0, 1, 0, 6), + PLL_FRACN_GP(498000000U, 166, 0, 1, 0, 8), PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), - PLL_FRACN_GP(400000000U, 50, 0, 1, 0, 3), - PLL_FRACN_GP(393216000U, 81, 92, 100, 0, 5) + PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), + PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10) }; struct imx_fracn_gppll_clk imx_fracn_gppll = { From patchwork Mon Apr 3 09:52:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13197956 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5BE6C76196 for ; Mon, 3 Apr 2023 09:49:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232291AbjDCJtC (ORCPT ); Mon, 3 Apr 2023 05:49:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232366AbjDCJsX (ORCPT ); Mon, 3 Apr 2023 05:48:23 -0400 Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2075.outbound.protection.outlook.com [40.107.6.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E29881165D; 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Mon, 3 Apr 2023 09:48:05 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Peng Fan Subject: [PATCH V3 2/7] clk: imx: fracn-gppll: disable hardware select control Date: Mon, 3 Apr 2023 17:52:55 +0800 Message-Id: <20230403095300.3386988-3-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230403095300.3386988-1-peng.fan@oss.nxp.com> References: <20230403095300.3386988-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI2P153CA0034.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::17) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|AS8PR04MB8070:EE_ X-MS-Office365-Filtering-Correlation-Id: 2d72c10e-2561-44af-eb61-08db342885b3 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: qRbYy/H8Sq7iugQYryhjbAPtOnlJGG6cQyCocS9DR5/klc4t6vvbwwOVckU/sTe+ZhyZtTZpv2WSVS9GJREnk/MU09ZSjrLJvkPCTmla858EGuqYEqN9OgvVldz6vtz9ReYw5gvng+HQ8aG2584iBV+pEgzwJM1pWgGJtvPGbTdY3o4Un63TntdQ5flGlKXSrdrrRqjwzzxEQQNw1pwg847HYRcz4DmHSzv38G+3syDVVE6JGqwDhdXBZpAOXsYDn8dmPRl+2egvhT4QfGUr60HrIhpo4X3Lavz7j7ERNqHn2SisbYKcv0BkmDHq7OtKXnagz/tnkX5qP3YpoMDtxmo5HqMKZILpBHlE6bI5GqZFSbEo2t8tU872wpdp00ZSQNWgPCFxXA12WyuYSaHbtyNdpWJ4SHpvLvJPRYInSXYD9DLNlGkgOFMR2cPVgY+tmna+hC+aKuP3sByPi0/SA6VzC5AcMNqKfZa0FDqc4ETkEvs6giQtPgU5xdpG0yAPAYHfZR2ATOy6t0MONIOgAyisOxD8VdSCswmSaXAj3GQxcO+xVuteePVfdrQ3eORmpL/PhYqoJa1deRu/zc215lKhVOxT2m/k7u3fPhIDi8Lz3AzPziKNrW0w5EGMnc1HYgNPVElI42Ds+SNBUXEkYVtbhYylUjRX7YNiFfjRgeovUhgyUg+znfnvrghs/z3wKUWkzY5agesOPKqulp1Cbv3fXK1o9GSmZ9uloUje2TscAXkVzc8CIUPLvxUf9BRNeC7P0zbdjhgDsdA13k424XHcdbxDULelPBfma7AroxlPB2FIHvV1eDpfpaGM1+kGUtttGcq9qPsKc2nXx4iaCC6L7sIe4bKSVZ4dty8wBIEs5086pmgT4sghY8CaZ7txSr8n8r8zFDKLBKMWwHry4oabQiw4eXss0PeiC8LnLjuWXVp81zJoM0bmHIR7nMMbx3+/zYx3n69qe1Bjv2MbPpPqSA3M9lsC/t8IXhG/JtAXWmzAh3qoOnwmQJiGzM5riMWH6/QKGmIJS0DOzHdXuf33aj8PrX2m2BpbSj2CqPFWfdoLobIHQFiNvAiSmE1Uy4JddYCaPGnPOxrClWsWUgw8WZ+9TRycj/HMz4gWeFlpwOVMGXZtCac5bmiFf7qrHXqkLNNuDqCKzaG3hvy7sqmmUjXQ5G+wYX0NFB0hKU1mEm9TU6tpfHtQesILL0xcA5X/7ufDFS96X/1MRiu1u4kNFVH16UHyn0RG73ZqkaCGTL9vuyXESLZAd7RexeZmynjtUqPtPnzEy6ocr2Bb9WJ4PHW6U5nZsxXZAy6yUDHhD8L5jo4nZdfhwSNzFUTrF9p7o+cbtQwqWK0+aAEufF8WgPGqv4N4HPho9TrTLFZliQfk2yQVT4ve53RQ6CZaKt+ZCfkgZtTFKZxTsjYb43X9cRsbRZFYisSQdKcgns90ayDhy89JsR0RdQqX0i88yOefCIlWBeXDJWQddzoPoYYV13+h46WtMb7613PoHK5fSzsOeye5mTUfzHgAxjyzTRx0HTu9102devVoJjKFSwB5jV7pP9YJLXDJg20KBR8jGRCkmBEpLRi3Tx3HeXWk X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d72c10e-2561-44af-eb61-08db342885b3 X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2023 09:48:05.2978 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: hDETIK/+KWrg7/oH2kRhi9jricC4Fp4xe9zsRHIDIkvVFnm9c/v0h8Hc2vmx42OKxilNTHWwJ5tl4Bxp8KZKLQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8070 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan When programming PLL, should disable Hardware control select to make PLL controlled by register, not hardware inputs through OSCPLL. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index ec50c41e2a4c..f6674110a88e 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -15,6 +15,7 @@ #include "clk.h" #define PLL_CTRL 0x0 +#define HW_CTRL_SEL BIT(16) #define CLKMUX_BYPASS BIT(2) #define CLKMUX_EN BIT(1) #define POWERUP_MASK BIT(0) @@ -193,6 +194,11 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, rate = imx_get_pll_settings(pll, drate); + /* Hardware control select disable. PLL is control by register */ + tmp = readl_relaxed(pll->base + PLL_CTRL); + tmp &= ~HW_CTRL_SEL; + writel_relaxed(tmp, pll->base + PLL_CTRL); + /* Disable output */ tmp = readl_relaxed(pll->base + PLL_CTRL); tmp &= ~CLKMUX_EN; From patchwork Mon Apr 3 09:52:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13197957 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCFD0C77B62 for ; Mon, 3 Apr 2023 09:49:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232124AbjDCJtK (ORCPT ); Mon, 3 Apr 2023 05:49:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55302 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232194AbjDCJsx (ORCPT ); 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Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by AS8PR04MB8070.eurprd04.prod.outlook.com (2603:10a6:20b:3f2::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6254.33; Mon, 3 Apr 2023 09:48:10 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::b999:f2c6:a8cc:7b4]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::b999:f2c6:a8cc:7b4%4]) with mapi id 15.20.6254.033; Mon, 3 Apr 2023 09:48:10 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Peng Fan Subject: [PATCH V3 3/7] clk: imx: fracn-gppll: support integer pll Date: Mon, 3 Apr 2023 17:52:56 +0800 Message-Id: <20230403095300.3386988-4-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230403095300.3386988-1-peng.fan@oss.nxp.com> References: <20230403095300.3386988-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI2P153CA0034.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::17) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|AS8PR04MB8070:EE_ X-MS-Office365-Filtering-Correlation-Id: ef74d386-f89f-437b-7af5-08db342888bd X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: nK69PV4Df3/Oxilr8TbApTFq6EOAKEL5xFrdx1iEXOkc0fD4ws6PDQGDi+tEpWtGDp72vdR7ZprQFPaylDO2T5xpcqmR0tP1TJIz4te/rdex16rGa7FIE0g7GZM0ldS3m9TzjUqhSOPdgRnX9h0iDBfTIxBAlIbifShAZgRvUfJoj4BIybwnDLjnfqWHzVKnrpGngqmAxFsZszLX/cG4xYW2T/YRdUu0rjeau36XsRjD2W0J59R10o81trF5wcUcC9OXLKMjiAyEsbU+Z64bXOrR2P4uvPxTJRS7KGI5/+YAOhwX2iVb5K95vVRQe05j0y1Z3dx6yfzGuCIb3SBY/xGYjQqMyV0bRbpKuSQC71w2hIlLbIVPGP7P0x4nBFR8uG+YpmwzVMce2Wr9dBzVuXOKZAXz4DeA/w+VuZ2b8bYRCwLJsmUJ+V8c8w8cA0RJBVErd5e3+3z4lUPUnSRS03pBfyY0wSiKZ4PAgOxg2JgHh0v7+CwMl90oLiT4pRFCnmvr8tjbQ0lmFJNv5c1ddaKF2olL1wKc7hvUNrB+jPM8puGD2cGjGF+uEw5XC82+HVKHR8glv43MpCI1R1C/kUF1J9QZi56tGwBSyJaJBiC89wt6cGh5Tbn2FUqqe8FwsA6tUn4Mi1ILA5b+AK9t5xdBpJfK0vae9RlePx4khpny3A8ago/tLgbGnO5TM7R3r3ajjg9V5xFSMI6K6NdyG9DwO9NatMQcMBtczeIgqc+orRs4Vk51kUHg6FKBNwYf1bsf5tMFuTvmj3T+LeGVjbM2MzmOaxKT5iuMLBSgjnTghUDKz5lMk4mbycJHq+Eg+XZJXNBxCS5FWDKSfybKK+8ghNYEBBJjwiPVKUx13xG3RkYN6U61e+cELfiD/rFAe5UM+TFcySxw9ODOv2GO9Tk7AvjuTZHlPp9Mlp48+blrpdWLYzlyNFn6UpW0BiaM4kwb875XEOJtOYQrBtNuPX6jET9Jv0FSdkZuDoGmHxHKwwrxUFn3c40pwHqdfRpNVhPSkHBPgHYaImdtIWYuj11Yk7nGKtEaPZ2z3Y9MKhiTKcRYR5YmgVHJ8jAydVle3oFdbTdoLhik+ytKDRKtLGJ1Rqd6lA5wySjjim7HvnK/Ldk3vzkntvHGQLpYxfJsqG9x37/94GLapEnQw1ZIGocokNVjq8CWu7X/G/U8XkUbbZbiV3e5xbc+pL0GOdJON1E4Dm6J1F91mhq8wjHcslM6YnJOTN6pIJFIpf/LfJjcSkXt8yNIujFxuDUYfmTfnjWgnyQdtzbh1QB0NTikaMONcO/yUpRWTImGtRC+FytvEr0y7gDcdLAY+7U9m6R+z41ycLe+PgWgOuFzqMd0maPVpufe88pxs+k9/6CgdQB7Y4gQUe+UTDcuyaLKYFvVwuAAjk5cBGEe7aNjIpSwGsw5Yzsuk2tgrPK35uh/o5l36+EfuiZvmo5rqZiD9hsZ5HJ72uZ1Ck57RcaioCD1Y7LdK8aLriiDMCsNBsdhXxiFyJTdflCx2cOge7eGKK+1NSsf1zZo5I1vV1AsMXqSpeErDjWev8sv8zBtOkdCzMEhU/dq7IRsA2DpsLPWKpkr X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ef74d386-f89f-437b-7af5-08db342888bd X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Apr 2023 09:48:10.5918 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: Tsgq/MXwcvf9cf0wtwxRWHZms/cTEmRT2j7nmXRf0dmVSpL7X1n0potFyD12cHqb2ZGD5RTgATdLi0NADHndFQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR04MB8070 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org From: Peng Fan The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces INTEGER support. When the PLL is INTEGER pll, there is no mfn, mfd, the calculation is as below: Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI] Fclko_odiv = Fvco_clk / DIV[ODIV] In this patch, we reuse the FRAC pll logic with some condition check to simplify the driver Signed-off-by: Peng Fan Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 68 +++++++++++++++++++++++++++---- drivers/clk/imx/clk.h | 7 ++++ 2 files changed, 68 insertions(+), 7 deletions(-) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index f6674110a88e..e2633ad94640 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -53,11 +53,22 @@ .odiv = (_odiv), \ } +#define PLL_FRACN_GP_INTEGER(_rate, _mfi, _rdiv, _odiv) \ + { \ + .rate = (_rate), \ + .mfi = (_mfi), \ + .mfn = 0, \ + .mfd = 0, \ + .rdiv = (_rdiv), \ + .odiv = (_odiv), \ + } + struct clk_fracn_gppll { struct clk_hw hw; void __iomem *base; const struct imx_fracn_gppll_rate_table *rate_table; int rate_count; + u32 flags; }; /* @@ -83,6 +94,24 @@ struct imx_fracn_gppll_clk imx_fracn_gppll = { }; EXPORT_SYMBOL_GPL(imx_fracn_gppll); +/* + * Fvco = (Fref / rdiv) * MFI + * Fout = Fvco / odiv + * The (Fref / rdiv) should be in range 20MHz to 40MHz + * The Fvco should be in range 2.5Ghz to 5Ghz + */ +static const struct imx_fracn_gppll_rate_table int_tbl[] = { + PLL_FRACN_GP_INTEGER(1700000000U, 141, 1, 2), + PLL_FRACN_GP_INTEGER(1400000000U, 175, 1, 3), + PLL_FRACN_GP_INTEGER(900000000U, 150, 1, 4), +}; + +struct imx_fracn_gppll_clk imx_fracn_gppll_integer = { + .rate_table = int_tbl, + .rate_count = ARRAY_SIZE(int_tbl), +}; +EXPORT_SYMBOL_GPL(imx_fracn_gppll_integer); + static inline struct clk_fracn_gppll *to_clk_fracn_gppll(struct clk_hw *hw) { return container_of(hw, struct clk_fracn_gppll, hw); @@ -169,9 +198,15 @@ static unsigned long clk_fracn_gppll_recalc_rate(struct clk_hw *hw, unsigned lon break; } - /* Fvco = Fref * (MFI + MFN / MFD) */ - fvco = fvco * mfi * mfd + fvco * mfn; - do_div(fvco, mfd * rdiv * odiv); + if (pll->flags & CLK_FRACN_GPPLL_INTEGER) { + /* Fvco = (Fref / rdiv) * MFI */ + fvco = fvco * mfi; + do_div(fvco, rdiv * odiv); + } else { + /* Fvco = (Fref / rdiv) * (MFI + MFN / MFD) */ + fvco = fvco * mfi * mfd + fvco * mfn; + do_div(fvco, mfd * rdiv * odiv); + } return (unsigned long)fvco; } @@ -215,8 +250,10 @@ static int clk_fracn_gppll_set_rate(struct clk_hw *hw, unsigned long drate, pll_div = FIELD_PREP(PLL_RDIV_MASK, rate->rdiv) | rate->odiv | FIELD_PREP(PLL_MFI_MASK, rate->mfi); writel_relaxed(pll_div, pll->base + PLL_DIV); - writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR); - writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR); + if (pll->flags & CLK_FRACN_GPPLL_FRACN) { + writel_relaxed(rate->mfd, pll->base + PLL_DENOMINATOR); + writel_relaxed(FIELD_PREP(PLL_MFN_MASK, rate->mfn), pll->base + PLL_NUMERATOR); + } /* Wait for 5us according to fracn mode pll doc */ udelay(5); @@ -300,8 +337,10 @@ static const struct clk_ops clk_fracn_gppll_ops = { .set_rate = clk_fracn_gppll_set_rate, }; -struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, - const struct imx_fracn_gppll_clk *pll_clk) +static struct clk_hw *_imx_clk_fracn_gppll(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk, + u32 pll_flags) { struct clk_fracn_gppll *pll; struct clk_hw *hw; @@ -322,6 +361,7 @@ struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, vo pll->hw.init = &init; pll->rate_table = pll_clk->rate_table; pll->rate_count = pll_clk->rate_count; + pll->flags = pll_flags; hw = &pll->hw; @@ -334,4 +374,18 @@ struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, vo return hw; } + +struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk) +{ + return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN); +} EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll); + +struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk) +{ + return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER); +} +EXPORT_SYMBOL_GPL(imx_clk_fracn_gppll_integer); diff --git a/drivers/clk/imx/clk.h b/drivers/clk/imx/clk.h index 055bc9197fb4..cb4e4c4b8278 100644 --- a/drivers/clk/imx/clk.h +++ b/drivers/clk/imx/clk.h @@ -73,6 +73,9 @@ extern struct imx_pll14xx_clk imx_1416x_pll; extern struct imx_pll14xx_clk imx_1443x_pll; extern struct imx_pll14xx_clk imx_1443x_dram_pll; +#define CLK_FRACN_GPPLL_INTEGER BIT(0) +#define CLK_FRACN_GPPLL_FRACN BIT(1) + /* NOTE: Rate table should be kept sorted in descending order. */ struct imx_fracn_gppll_rate_table { unsigned int rate; @@ -91,8 +94,12 @@ struct imx_fracn_gppll_clk { struct clk_hw *imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk); +struct clk_hw *imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, + void __iomem *base, + const struct imx_fracn_gppll_clk *pll_clk); extern struct imx_fracn_gppll_clk imx_fracn_gppll; +extern struct imx_fracn_gppll_clk imx_fracn_gppll_integer; #define imx_clk_cpu(name, parent_name, div, mux, pll, step) \ to_clk(imx_clk_hw_cpu(name, parent_name, div, mux, pll, step)) From patchwork Mon Apr 3 09:52:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13197962 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 16F56C76196 for ; Mon, 3 Apr 2023 09:49:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232176AbjDCJtm (ORCPT ); Mon, 3 Apr 2023 05:49:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51498 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232022AbjDCJtH (ORCPT ); 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Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by AS8PR04MB8070.eurprd04.prod.outlook.com (2603:10a6:20b:3f2::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6254.33; Mon, 3 Apr 2023 09:48:16 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::b999:f2c6:a8cc:7b4]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::b999:f2c6:a8cc:7b4%4]) with mapi id 15.20.6254.033; Mon, 3 Apr 2023 09:48:16 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jacky Bai , Ye Li , Peng Fan Subject: [PATCH V3 4/7] clk: imx: fracn-gppll: Add 300MHz freq support for imx9 Date: Mon, 3 Apr 2023 17:52:57 +0800 Message-Id: <20230403095300.3386988-5-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230403095300.3386988-1-peng.fan@oss.nxp.com> References: <20230403095300.3386988-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI2P153CA0034.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::17) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|AS8PR04MB8070:EE_ X-MS-Office365-Filtering-Correlation-Id: 0a84755b-ba4a-4710-c2dc-08db34288c3b X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Reviewed-by: Ye Li Signed-off-by: Jacky Bai Signed-off-by: Peng Fan Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-fracn-gppll.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-fracn-gppll.c b/drivers/clk/imx/clk-fracn-gppll.c index e2633ad94640..c54f9999da04 100644 --- a/drivers/clk/imx/clk-fracn-gppll.c +++ b/drivers/clk/imx/clk-fracn-gppll.c @@ -85,7 +85,8 @@ static const struct imx_fracn_gppll_rate_table fracn_tbl[] = { PLL_FRACN_GP(484000000U, 121, 0, 1, 0, 6), PLL_FRACN_GP(445333333U, 167, 0, 1, 0, 9), PLL_FRACN_GP(400000000U, 200, 0, 1, 0, 12), - PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10) + PLL_FRACN_GP(393216000U, 163, 84, 100, 0, 10), + PLL_FRACN_GP(300000000U, 150, 0, 1, 0, 12) }; struct imx_fracn_gppll_clk imx_fracn_gppll = { From patchwork Mon Apr 3 09:52:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13197963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1780AC76196 for ; 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To i.MX93, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and LPCG (clock gating) to gate clocks to peripherals. As below: anatop->ccm->lpcg->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for LPCG and CCM, auxiliary core normally only use LPCG hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Reviewed-by: Ye Li Signed-off-by: Peng Fan Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-composite-93.c | 8 +++++++- drivers/clk/imx/clk-imx93.c | 2 ++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-composite-93.c b/drivers/clk/imx/clk-composite-93.c index 74a66b0203e4..81164bdcd6cc 100644 --- a/drivers/clk/imx/clk-composite-93.c +++ b/drivers/clk/imx/clk-composite-93.c @@ -222,7 +222,7 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, mux_hw, &clk_mux_ro_ops, div_hw, &clk_divider_ro_ops, NULL, NULL, flags); - } else { + } else if (!mcore_booted) { gate = kzalloc(sizeof(*gate), GFP_KERNEL); if (!gate) goto fail; @@ -238,6 +238,12 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p &imx93_clk_composite_divider_ops, gate_hw, &imx93_clk_composite_gate_ops, flags | CLK_SET_RATE_NO_REPARENT); + } else { + hw = clk_hw_register_composite(NULL, name, parent_names, num_parents, + mux_hw, &imx93_clk_composite_mux_ops, div_hw, + &imx93_clk_composite_divider_ops, NULL, + &imx93_clk_composite_gate_ops, + flags | CLK_SET_RATE_NO_REPARENT); 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Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by AS8PR04MB8070.eurprd04.prod.outlook.com (2603:10a6:20b:3f2::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6254.33; Mon, 3 Apr 2023 09:48:27 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::b999:f2c6:a8cc:7b4]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::b999:f2c6:a8cc:7b4%4]) with mapi id 15.20.6254.033; Mon, 3 Apr 2023 09:48:27 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Peng Fan Subject: [PATCH V3 6/7] dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK Date: Mon, 3 Apr 2023 17:52:59 +0800 Message-Id: <20230403095300.3386988-7-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20230403095300.3386988-1-peng.fan@oss.nxp.com> References: <20230403095300.3386988-1-peng.fan@oss.nxp.com> X-ClientProxiedBy: SI2P153CA0034.APCP153.PROD.OUTLOOK.COM (2603:1096:4:190::17) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|AS8PR04MB8070:EE_ X-MS-Office365-Filtering-Correlation-Id: 02b26729-60f0-4f40-7872-08db342892b7 X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Signed-off-by: Peng Fan Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/imx93-clock.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/imx93-clock.h b/include/dt-bindings/clock/imx93-clock.h index 8e02859d8ce2..35a1f62053a5 100644 --- a/include/dt-bindings/clock/imx93-clock.h +++ b/include/dt-bindings/clock/imx93-clock.h @@ -199,6 +199,10 @@ #define IMX93_CLK_MU1_B_GATE 194 #define IMX93_CLK_MU2_A_GATE 195 #define IMX93_CLK_MU2_B_GATE 196 -#define IMX93_CLK_END 197 +#define IMX93_CLK_NIC_AXI 197 +#define IMX93_CLK_ARM_PLL 198 +#define IMX93_CLK_A55_SEL 199 +#define IMX93_CLK_A55_CORE 200 +#define IMX93_CLK_END 201 #endif From patchwork Mon Apr 3 09:53:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Peng Fan (OSS)" X-Patchwork-Id: 13197965 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ECE12C76196 for ; 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Add NIC CLK to reflect the clk status Signed-off-by: Peng Fan Reviewed-by: Abel Vesa --- drivers/clk/imx/clk-imx93.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/drivers/clk/imx/clk-imx93.c b/drivers/clk/imx/clk-imx93.c index de1ed1d8ba54..07b4a043e449 100644 --- a/drivers/clk/imx/clk-imx93.c +++ b/drivers/clk/imx/clk-imx93.c @@ -33,6 +33,7 @@ static u32 share_count_sai2; static u32 share_count_sai3; static u32 share_count_mub; +static const char * const a55_core_sels[] = {"a55_alt", "arm_pll"}; static const char *parent_names[MAX_SEL][4] = { {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "video_pll"}, {"osc_24m", "sys_pll_pfd0_div2", "sys_pll_pfd1_div2", "sys_pll_pfd2_div2"}, @@ -55,7 +56,7 @@ static const struct imx93_clk_root { /* a55/m33/bus critical clk for system run */ { IMX93_CLK_A55_PERIPH, "a55_periph_root", 0x0000, FAST_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_A55_MTR_BUS, "a55_mtr_bus_root", 0x0080, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, - { IMX93_CLK_A55, "a55_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, + { IMX93_CLK_A55, "a55_alt_root", 0x0100, FAST_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_M33, "m33_root", 0x0180, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_BUS_WAKEUP, "bus_wakeup_root", 0x0280, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, { IMX93_CLK_BUS_AON, "bus_aon_root", 0x0300, LOW_SPEED_IO_SEL, CLK_IS_CRITICAL }, @@ -117,6 +118,7 @@ static const struct imx93_clk_root { { IMX93_CLK_HSIO_USB_TEST_60M, "hsio_usb_test_60m_root", 0x1f00, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_80M, "hsio_acscan_80m_root", 0x1f80, LOW_SPEED_IO_SEL, }, { IMX93_CLK_HSIO_ACSCAN_480M, "hsio_acscan_480m_root", 0x2000, MISC_SEL, }, + { IMX93_CLK_NIC_AXI, "nic_axi_root", 0x2080, FAST_SEL, CLK_IS_CRITICAL, }, { IMX93_CLK_ML_APB, "ml_apb_root", 0x2180, LOW_SPEED_IO_SEL, }, { IMX93_CLK_ML, "ml_root", 0x2200, FAST_SEL, }, { IMX93_CLK_MEDIA_AXI, "media_axi_root", 0x2280, FAST_SEL, }, @@ -153,7 +155,7 @@ static const struct imx93_clk_ccgr { unsigned long flags; u32 *shared_count; } ccgr_array[] = { - { IMX93_CLK_A55_GATE, "a55", "a55_root", 0x8000, }, + { IMX93_CLK_A55_GATE, "a55_alt", "a55_alt_root", 0x8000, }, /* M33 critical clk for system run */ { IMX93_CLK_CM33_GATE, "cm33", "m33_root", 0x8040, CLK_IS_CRITICAL }, { IMX93_CLK_ADC1_GATE, "adc1", "adc_root", 0x82c0, }, @@ -291,6 +293,9 @@ static int imx93_clocks_probe(struct platform_device *pdev) if (WARN_ON(!anatop_base)) return -ENOMEM; + clks[IMX93_CLK_ARM_PLL] = imx_clk_fracn_gppll_integer("arm_pll", "osc_24m", + anatop_base + 0x1000, + &imx_fracn_gppll_integer); clks[IMX93_CLK_AUDIO_PLL] = imx_clk_fracn_gppll("audio_pll", "osc_24m", anatop_base + 0x1200, &imx_fracn_gppll); clks[IMX93_CLK_VIDEO_PLL] = imx_clk_fracn_gppll("video_pll", "osc_24m", anatop_base + 0x1400, @@ -318,6 +323,14 @@ static int imx93_clocks_probe(struct platform_device *pdev) ccgr->shared_count); } + clks[IMX93_CLK_A55_SEL] = imx_clk_hw_mux2("a55_sel", base + 0x4820, 0, 1, a55_core_sels, + ARRAY_SIZE(a55_core_sels)); + clks[IMX93_CLK_A55_CORE] = imx_clk_hw_cpu("a55_core", "a55_sel", + clks[IMX93_CLK_A55_SEL]->clk, + clks[IMX93_CLK_A55_SEL]->clk, + clks[IMX93_CLK_ARM_PLL]->clk, + clks[IMX93_CLK_A55_GATE]->clk); + imx_check_clk_hws(clks, IMX93_CLK_END); ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_hw_data);