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[176.184.52.81]) by smtp.gmail.com with ESMTPSA id f16-20020adffcd0000000b002d5a8d8442asm14561130wrs.37.2023.04.05.03.08.56 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:08:59 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 1/2] target/arm: Remove KVM AArch32 CPU definitions Date: Wed, 5 Apr 2023 12:08:47 +0200 Message-Id: <20230405100848.76145-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405100848.76145-1-philmd@linaro.org> References: <20230405100848.76145-1-philmd@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Missed in commit 80485d88f9 ("target/arm: Restrict v7A TCG cpus to TCG accel"). Signed-off-by: Philippe Mathieu-Daudé --- target/arm/kvm-consts.h | 9 +++------ target/arm/cpu_tcg.c | 2 -- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/target/arm/kvm-consts.h b/target/arm/kvm-consts.h index 09967ec5e6..7c6adc14f6 100644 --- a/target/arm/kvm-consts.h +++ b/target/arm/kvm-consts.h @@ -124,13 +124,10 @@ MISMATCH_CHECK(QEMU_PSCI_RET_INTERNAL_FAILURE, PSCI_RET_INTERNAL_FAILURE); MISMATCH_CHECK(QEMU_PSCI_RET_NOT_PRESENT, PSCI_RET_NOT_PRESENT); MISMATCH_CHECK(QEMU_PSCI_RET_DISABLED, PSCI_RET_DISABLED); -/* Note that KVM uses overlapping values for AArch32 and AArch64 - * target CPU numbers. AArch32 targets: +/* + * Note that KVM uses overlapping values for AArch32 and AArch64 + * target CPU numbers. AArch64 targets: */ -#define QEMU_KVM_ARM_TARGET_CORTEX_A15 0 -#define QEMU_KVM_ARM_TARGET_CORTEX_A7 1 - -/* AArch64 targets: */ #define QEMU_KVM_ARM_TARGET_AEM_V8 0 #define QEMU_KVM_ARM_TARGET_FOUNDATION_V8 1 #define QEMU_KVM_ARM_TARGET_CORTEX_A57 2 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index df0c45e523..1911d7ec47 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -546,7 +546,6 @@ static void cortex_a7_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A7; cpu->midr = 0x410fc075; cpu->reset_fpsid = 0x41023075; cpu->isar.mvfr0 = 0x10110222; @@ -595,7 +594,6 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL2); set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; /* r4p0 cpu, not requiring expensive tlb flush errata */ cpu->midr = 0x414fc0f0; cpu->revidr = 0x0; From patchwork Wed Apr 5 10:08:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 13201536 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFE1FC7619A for ; Wed, 5 Apr 2023 10:09:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237745AbjDEKJM (ORCPT ); Wed, 5 Apr 2023 06:09:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237537AbjDEKJJ (ORCPT ); Wed, 5 Apr 2023 06:09:09 -0400 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [IPv6:2a00:1450:4864:20::334]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9230E4ECD for ; Wed, 5 Apr 2023 03:09:08 -0700 (PDT) Received: by mail-wm1-x334.google.com with SMTP id l15-20020a05600c4f0f00b003ef6d684102so18073538wmq.3 for ; Wed, 05 Apr 2023 03:09:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1680689347; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hOIUAejMDgPGNri6CTMX+NYmgz2rO96F3gJmXNOLJxs=; b=S/sJ8y4f2rUl+i71e+mCuGZuZfY5fREdNc1TFr/aEXiGuikTme64GMgqYOa7eqvixO sNf4U91Oj8cWhbCz7saOEF1jx3ZzoabpA11OvpGepX7sFWjMI2K2iaCYA5Fb4cTqW4qv HoQvYT2zAkq2AlgE8ycDb+ODBHfZ/BCzFs9ybHjyfKeXsodw2D/l0JLrY1+diUnYMK0E tXVNnQT0t9UN3DtYNnVA9xztmGer2h8JkgXwvU5dkPdsfscXL8aUv9mc9gBJdYD4Nbx/ 4iwShUAj28BK3KLQ6kcThPbwc066mniDVXLh3YMBP3tos1Egxks3TfoEQ8SlpiFstZX7 RYdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680689347; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hOIUAejMDgPGNri6CTMX+NYmgz2rO96F3gJmXNOLJxs=; b=ip1+J/f87jQdOnMZcr2E24irfcnxkvplc39f0woS7vLijgfZn4qAdP6KCDG6Ky4/AU IfjiTb5Ejy2156Z6Oyd+l2XLJIC2Ih5bJ1gi/irGdNpfFaGkq01Acr5vU95rYD3vxOYI Xmxu0dDxNvqK6fUvz0lJvwMepSrN0IMpvhIsOemyyj/KdHZqkpQ/jworTUteR53ovKZ6 CKz98e60uXAYTQn4quK7ZjUb4wRXJHl04IwLq7gAa9Ui9t/G3oBmVVmYiNrgnU6KeYAC ZG32GQWIU0N0eIaTyWHw4p+o4qJDMK+0IPcAbmEDMdv14/nAW5ihLmN/JNgufJRP2/R/ fFRA== X-Gm-Message-State: AAQBX9cq6W0x10vRRxer6PWQnSG8xUUlUcqKMl7dPOV+gLwN0wb+kn1x wyoUuW+K88hUvzTiLDJ9AQ1dSg== X-Google-Smtp-Source: AKy350ZwPv7srv1WoSO/MmSOa2UJdjZu3e7HsfWH/ffyjG4++YTRkUBAfgBBRDMhjS3YahEj4GkMfQ== X-Received: by 2002:a05:600c:25a:b0:3ed:237f:3da with SMTP id 26-20020a05600c025a00b003ed237f03damr4592489wmj.22.1680689347060; Wed, 05 Apr 2023 03:09:07 -0700 (PDT) Received: from localhost.localdomain (4ab54-h01-176-184-52-81.dsl.sta.abo.bbox.fr. [176.184.52.81]) by smtp.gmail.com with ESMTPSA id m19-20020a7bce13000000b003ee1acdb036sm1700160wmc.17.2023.04.05.03.09.04 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 05 Apr 2023 03:09:06 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 2/2] hw/arm/virt: Restrict Cortex-A7 check to TCG Date: Wed, 5 Apr 2023 12:08:48 +0200 Message-Id: <20230405100848.76145-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230405100848.76145-1-philmd@linaro.org> References: <20230405100848.76145-1-philmd@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org The Cortex-A7 core is only available when TCG is enabled (see commit 80485d88f9 "target/arm: Restrict v7A TCG cpus to TCG accel"). Signed-off-by: Philippe Mathieu-Daudé --- hw/arm/virt.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ac626b3bef..1fe39c6683 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,7 +204,9 @@ static const int a15irqmap[] = { }; static const char *valid_cpus[] = { +#ifdef CONFIG_TCG ARM_CPU_TYPE_NAME("cortex-a7"), +#endif ARM_CPU_TYPE_NAME("cortex-a15"), ARM_CPU_TYPE_NAME("cortex-a35"), ARM_CPU_TYPE_NAME("cortex-a53"),