From patchwork Fri Apr 7 10:27:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13204646 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C328FC77B6E for ; Fri, 7 Apr 2023 10:27:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240593AbjDGK1g (ORCPT ); Fri, 7 Apr 2023 06:27:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240605AbjDGK1d (ORCPT ); Fri, 7 Apr 2023 06:27:33 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E99297ED3 for ; Fri, 7 Apr 2023 03:27:28 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id 77EAA5C02F7; Fri, 7 Apr 2023 06:27:26 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Fri, 07 Apr 2023 06:27:26 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1680863246; x= 1680949646; bh=mKBYAYmQOUcy8YuQxwCRtwb9d+L7Jo6sbgjNnR0YTZE=; b=M D5r8RgHvNjtPZq522FPxbLhsof/JX3EscUiMN8d6OxYI258Kq6PKy8ww3yIfQTS/ JpKGDZIatm/8dPjFu1tn0fDdIThwaBPI1gef77CN7aSXG9kmHlPiJleKzg5Xlhc1 l4EspZfa4NdZWfhDm9ojfnLfzaBpIbLcgO29JQmCeXBrxysBa40Q852STs9f/cih 21A8XissNc7CL7BUQfu1vx01rkr7ZeUDuaXoUq8AIVVkIcQDWeIz9RcfDuMl8mgG F2ew1mLcqQNa2SsxG7Fb/MHbS8QT8h1IN/nGDbAKJ9IosikaKq+qcQgRWq7mw031 JdcagZK7HIHETP4R2uNUg== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1680863246; x= 1680949646; bh=mKBYAYmQOUcy8YuQxwCRtwb9d+L7Jo6sbgjNnR0YTZE=; b=g vHS1dqbA7jsV59EpGH9JZgX/5+fuclc2/zEjmNXiRH8KTc12X125RdinUqI0VbTm pD1U+IvFVVzp3PvRVQjEKmYj8AjeUQOGK9tvxRu7aqQeEDF6WqIEPWEYIctHnhKY am5nGD04jaMDUWn+LaK7My5OIACSXU/42VHg8ALbiyTu7qGmDyIG51tI9VPEFH2D dykWjl42D8ijgk15FyMEGyJLffAOss5YV4cY7KMTVcjpCxgRukQ+lOCAbjZLNU2m h8891y7FwwrQTs9QOHX6oA65GiJEHJruJOS0tjK/bB8KEtr5cuWpw6Zc5WMFyN5h LJonQBM1q1Rwv8K9UM4HA== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdejhedgvdelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfeeludefheegvdeuvd dvgeekgfdvtdettdelieeihfegtedugeekhfdvhfejfedtnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 7 Apr 2023 06:27:25 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 1/5] MIPS: Move various toolchain ASE check to Kconfig Date: Fri, 7 Apr 2023 11:27:17 +0100 Message-Id: <20230407102721.14814-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230407102721.14814-1-jiaxun.yang@flygoat.com> References: <20230407102721.14814-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Use Kconfig to perform Kconfig toolchain feature check, so we will be able to have toolchain feature availablility information in Kconfig to guard relevant options. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 27 +++++++++++++++++++++++++++ arch/mips/Makefile | 29 +++-------------------------- arch/mips/crypto/crc32-mips.c | 4 ++-- arch/mips/include/asm/asmmacro.h | 8 ++++---- arch/mips/include/asm/ginvt.h | 2 +- arch/mips/include/asm/mipsregs.h | 10 +++++----- arch/mips/include/asm/msa.h | 4 ++-- 7 files changed, 44 insertions(+), 40 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 770d098b11bf..c52401c155a4 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -3157,6 +3157,12 @@ config MIPS32_N32 If unsure, say N. +config CC_HAS_SMARTMIPS + def_bool $(cc-option,-mmicromips) + +config CC_HAS_MICROMIPS + def_bool $(cc-option,-mmicromips) + config CC_HAS_MNO_BRANCH_LIKELY def_bool y depends on $(cc-option,-mno-branch-likely) @@ -3165,6 +3171,27 @@ config CC_HAS_MNO_BRANCH_LIKELY config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH def_bool y if CC_IS_CLANG +config AS_HAS_MSA + def_bool $(cc-option,-Wa$(comma)-mmsa) + +config AS_HAS_VIRT + def_bool $(cc-option,-Wa$(comma)-mvirt) + +# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which +# only warns +config AS_HAS_XPA + def_bool $(cc-option,-Wa$(comma)-mxpa) if !CPU_MICROMIPS + def_bool $(cc-option,-mmicromips -Wa$(comma)-fatal-warnings -Wa$(comma)-mxpa) if CPU_MICROMIPS + +config AS_HAS_CRC + def_bool $(cc-option,-Wa$(comma)-mcrc) + +config AS_HAS_DSP + def_bool $(cc-option,-Wa$(comma)-mdsp) + +config AS_HAS_GINV + def_bool $(cc-option,-Wa$(comma)-mginv) + menu "Power management options" config ARCH_HIBERNATION_POSSIBLE diff --git a/arch/mips/Makefile b/arch/mips/Makefile index a7a4ee66a9d3..3aa0f9d4ceb6 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -233,32 +233,9 @@ cflags-$(CONFIG_CPU_LOONGSON64) += $(call as-option,-Wa$(comma)-mno-fix-loongson # Pass -Wa,--no-warn to disable all assembler warnings until the kernel code has # been fixed properly. mips-cflags := $(cflags-y) -ifeq ($(CONFIG_CPU_HAS_SMARTMIPS),y) -smartmips-ase := $(call cc-option-yn,$(mips-cflags) -msmartmips) -cflags-$(smartmips-ase) += -msmartmips -Wa,--no-warn -endif -ifeq ($(CONFIG_CPU_MICROMIPS),y) -micromips-ase := $(call cc-option-yn,$(mips-cflags) -mmicromips) -cflags-$(micromips-ase) += -mmicromips -endif -ifeq ($(CONFIG_CPU_HAS_MSA),y) -toolchain-msa := $(call cc-option-yn,$(mips-cflags) -mhard-float -mfp64 -Wa$(comma)-mmsa) -cflags-$(toolchain-msa) += -DTOOLCHAIN_SUPPORTS_MSA -endif -toolchain-virt := $(call cc-option-yn,$(mips-cflags) -mvirt) -cflags-$(toolchain-virt) += -DTOOLCHAIN_SUPPORTS_VIRT -# For -mmicromips, use -Wa,-fatal-warnings to catch unsupported -mxpa which -# only warns -xpa-cflags-y := $(mips-cflags) -xpa-cflags-$(micromips-ase) += -mmicromips -Wa$(comma)-fatal-warnings -toolchain-xpa := $(call cc-option-yn,$(xpa-cflags-y) -mxpa) -cflags-$(toolchain-xpa) += -DTOOLCHAIN_SUPPORTS_XPA -toolchain-crc := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mcrc) -cflags-$(toolchain-crc) += -DTOOLCHAIN_SUPPORTS_CRC -toolchain-dsp := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mdsp) -cflags-$(toolchain-dsp) += -DTOOLCHAIN_SUPPORTS_DSP -toolchain-ginv := $(call cc-option-yn,$(mips-cflags) -Wa$(comma)-mginv) -cflags-$(toolchain-ginv) += -DTOOLCHAIN_SUPPORTS_GINV + +cflags-$(CONFIG_CPU_HAS_SMARTMIPS) += -msmartmips -Wa,--no-warn +cflags-$(CONFIG_CPU_MICROMIPS) += -mmicromips # # Firmware support diff --git a/arch/mips/crypto/crc32-mips.c b/arch/mips/crypto/crc32-mips.c index 3e4f5ba104f8..54bbcfae06d5 100644 --- a/arch/mips/crypto/crc32-mips.c +++ b/arch/mips/crypto/crc32-mips.c @@ -27,7 +27,7 @@ enum crc_type { crc32c, }; -#ifndef TOOLCHAIN_SUPPORTS_CRC +#ifndef CONFIG_AS_HAS_CRC #define _ASM_SET_CRC(OP, SZ, TYPE) \ _ASM_MACRO_3R(OP, rt, rs, rt2, \ ".ifnc \\rt, \\rt2\n\t" \ @@ -38,7 +38,7 @@ _ASM_MACRO_3R(OP, rt, rs, rt2, \ _ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) | \ ((SZ) << 14) | ((TYPE) << 3))) #define _ASM_UNSET_CRC(op, SZ, TYPE) ".purgem " #op "\n\t" -#else /* !TOOLCHAIN_SUPPORTS_CRC */ +#else /* !CONFIG_AS_HAS_CRC */ #define _ASM_SET_CRC(op, SZ, TYPE) ".set\tcrc\n\t" #define _ASM_UNSET_CRC(op, SZ, TYPE) #endif diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 067a635d3bc8..74c2dedc55b4 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -239,7 +239,7 @@ .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) .endm -#ifdef TOOLCHAIN_SUPPORTS_MSA +#ifdef CONFIG_AS_HAS_MSA .macro _cfcmsa rd, cs .set push .set mips32r2 @@ -507,7 +507,7 @@ .endm #endif -#ifdef TOOLCHAIN_SUPPORTS_MSA +#ifdef CONFIG_AS_HAS_MSA #define FPR_BASE_OFFS THREAD_FPR0 #define FPR_BASE $1 #else @@ -518,7 +518,7 @@ .macro msa_save_all thread .set push .set noat -#ifdef TOOLCHAIN_SUPPORTS_MSA +#ifdef CONFIG_AS_HAS_MSA PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS #endif st_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE @@ -565,7 +565,7 @@ .set hardfloat lw $1, THREAD_MSA_CSR(\thread) _ctcmsa MSA_CSR, $1 -#ifdef TOOLCHAIN_SUPPORTS_MSA +#ifdef CONFIG_AS_HAS_MSA PTR_ADDU FPR_BASE, \thread, FPR_BASE_OFFS #endif ld_d 0, THREAD_FPR0 - FPR_BASE_OFFS, FPR_BASE diff --git a/arch/mips/include/asm/ginvt.h b/arch/mips/include/asm/ginvt.h index 87b2974ffc53..20244a622552 100644 --- a/arch/mips/include/asm/ginvt.h +++ b/arch/mips/include/asm/ginvt.h @@ -10,7 +10,7 @@ enum ginvt_type { GINVT_MMID, }; -#ifdef TOOLCHAIN_SUPPORTS_GINV +#ifdef CONFIG_AS_HAS_GINV # define _ASM_SET_GINV ".set ginv\n" # define _ASM_UNSET_GINV #else diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 2d53704d9f24..8f0ebc399338 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1604,7 +1604,7 @@ do { \ local_irq_restore(__flags); \ } while (0) -#ifndef TOOLCHAIN_SUPPORTS_XPA +#ifndef CONFIG_AS_HAS_XPA #define _ASM_SET_MFHC0 \ _ASM_MACRO_2R_1S(mfhc0, rt, rs, sel, \ _ASM_INSN_IF_MIPS(0x40400000 | __rt << 16 | __rs << 11 | \\sel) \ @@ -1615,7 +1615,7 @@ do { \ _ASM_INSN_IF_MIPS(0x40c00000 | __rt << 16 | __rd << 11 | \\sel) \ _ASM_INSN32_IF_MM(0x000002f4 | __rt << 21 | __rd << 16 | \\sel << 11)) #define _ASM_UNSET_MTHC0 ".purgem mthc0\n\t" -#else /* !TOOLCHAIN_SUPPORTS_XPA */ +#else /* !CONFIG_AS_HAS_XPA */ #define _ASM_SET_MFHC0 ".set\txpa\n\t" #define _ASM_SET_MTHC0 ".set\txpa\n\t" #define _ASM_UNSET_MFHC0 @@ -2040,7 +2040,7 @@ do { \ * Macros to access the guest system control coprocessor */ -#ifndef TOOLCHAIN_SUPPORTS_VIRT +#ifndef CONFIG_AS_HAS_VIRT #define _ASM_SET_MFGC0 \ _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel, \ _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) \ @@ -2077,7 +2077,7 @@ do { \ #define __tlbginvf() \ _ASM_INSN_IF_MIPS(0x4200000c) \ _ASM_INSN32_IF_MM(0x0000517c) -#else /* !TOOLCHAIN_SUPPORTS_VIRT */ +#else /* !CONFIG_AS_HAS_VIRT */ #define _ASM_SET_VIRT ".set\tvirt\n\t" #define _ASM_SET_MFGC0 _ASM_SET_VIRT #define _ASM_SET_DMFGC0 _ASM_SET_VIRT @@ -2395,7 +2395,7 @@ do { \ : : "r" (val)); \ } while (0) -#ifdef TOOLCHAIN_SUPPORTS_DSP +#ifdef CONFIG_AS_HAS_DSP #define rddsp(mask) \ ({ \ unsigned int __dspctl; \ diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h index 236a49ee2e3e..a9ca57e3f780 100644 --- a/arch/mips/include/asm/msa.h +++ b/arch/mips/include/asm/msa.h @@ -156,7 +156,7 @@ static inline void init_msa_upper(void) _init_msa_upper(); } -#ifndef TOOLCHAIN_SUPPORTS_MSA +#ifndef CONFIG_AS_HAS_MSA /* * Define assembler macros using .word for the c[ft]cmsa instructions in order * to allow compilation with toolchains that do not support MSA. Once all @@ -173,7 +173,7 @@ static inline void init_msa_upper(void) _ASM_INSN_IF_MIPS(0x783e0019 | __rs << 11 | __cd << 6) \ _ASM_INSN32_IF_MM(0x583e0016 | __rs << 11 | __cd << 6)) #define _ASM_UNSET_CTCMSA ".purgem ctcmsa\n\t" -#else /* TOOLCHAIN_SUPPORTS_MSA */ +#else /* CONFIG_AS_HAS_MSA */ #define _ASM_SET_CFCMSA \ ".set\tfp=64\n\t" \ ".set\tmsa\n\t" From patchwork Fri Apr 7 10:27:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13204645 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDF9BC76196 for ; Fri, 7 Apr 2023 10:27:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240619AbjDGK1f (ORCPT ); Fri, 7 Apr 2023 06:27:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59260 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231521AbjDGK1d (ORCPT ); Fri, 7 Apr 2023 06:27:33 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EC489A5D3 for ; Fri, 7 Apr 2023 03:27:28 -0700 (PDT) Received: from compute4.internal (compute4.nyi.internal [10.202.2.44]) by mailout.nyi.internal (Postfix) with ESMTP id CC9275C02FC; Fri, 7 Apr 2023 06:27:27 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute4.internal (MEProxy); Fri, 07 Apr 2023 06:27:27 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1680863247; x= 1680949647; bh=6xZQ6d8SXf9ltEs4IqAsx1PbLpqMzk9FVvoeJw0REcQ=; b=E zqif4/FZkXWTY/P0U9EdKDnN0AHHkqa6mlc5aahW4xoxRL+MawJr61BoGwWil84u Tda7JwH++JR3p6xvirfiV9IJMtn82fCHMy0tIMCR8E35KPDVsbgCbmmxt5SAo4ls m03cvZ0ojINNCVpQasDNB4aABXMhCtSjor32JLGh8mFfQCIJKULHRzCvweFsu7ti 482RWnvgxp4+gYZufO7uXBvOJq9NbLmKUHfONqNIZWpw/dHFzu3fN9C8IJmXd03D c0dRHG9a9bNWCxp7hm4EnNYi/2zOUutzWKY0/ZJe9JMyHWFOok8KBpBfOqbs4+fx nTUCDhb1Mz10S2uztsrqw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1680863247; x= 1680949647; bh=6xZQ6d8SXf9ltEs4IqAsx1PbLpqMzk9FVvoeJw0REcQ=; b=L PRrsfPa0K86uHcholAcLGNG0qiquIwC5mQfrunNcbuQbeNvHOzQR2eshp6sNyrIp sJkf1t3VBM5UBPu6niAxqGY1s6yiSx2u1dKLJoQ6hMdFfxdshHw/Pr0EOEVfiksV lYS6dZkBuYbJr+iFJ2IgyNSmDf817TtTvy9clHsm5Z44DtrolJ2+UjlM/XsdAJjq z0Alj6ydBgp/SOoBWJP1CEEgEAN9j4NNkezMy1IFJMSqhQD7sEosICP5yFrQz5eX hgqG/RQ2V++LHTBZY+9ogzIH5WXE6c/ZqrGSggFtGIKop9qhOcMgK/H7W6Yu3uUc eSTOUHC5n/YrYxjvU5M6Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdejhedgvdelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfeeludefheegvdeuvd dvgeekgfdvtdettdelieeihfegtedugeekhfdvhfejfedtnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 7 Apr 2023 06:27:26 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 2/5] MIPS: Add toolchain feature dependency for microMIPS smartMIPS Date: Fri, 7 Apr 2023 11:27:18 +0100 Message-Id: <20230407102721.14814-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230407102721.14814-1-jiaxun.yang@flygoat.com> References: <20230407102721.14814-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org microMIPS smartMIPS kernel can only be compiled if they are supported by toolchain. Signed-off-by: Jiaxun Yang Reviewed-by: Nick Desaulniers --- arch/mips/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index c52401c155a4..9e9de2b62f28 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2360,7 +2360,7 @@ config CPU_NEEDS_NO_SMARTMIPS_OR_MICROMIPS Select this if you want neither microMIPS nor SmartMIPS support config CPU_HAS_SMARTMIPS - depends on SYS_SUPPORTS_SMARTMIPS + depends on SYS_SUPPORTS_SMARTMIPS && CC_HAS_SMARTMIPS bool "SmartMIPS" help SmartMIPS is a extension of the MIPS32 architecture aimed at @@ -2372,7 +2372,7 @@ config CPU_HAS_SMARTMIPS here. config CPU_MICROMIPS - depends on 32BIT && SYS_SUPPORTS_MICROMIPS && !CPU_MIPSR6 + depends on 32BIT && SYS_SUPPORTS_MICROMIPS && CC_HAS_MICROMIPS && !CPU_MIPSR6 bool "microMIPS" help When this option is enabled the kernel will be built using the From patchwork Fri Apr 7 10:27:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13204647 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5760BC77B6F for ; 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Fri, 7 Apr 2023 06:27:27 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 3/5] MIPS: Detect toolchain support of workarounds in Kconfig Date: Fri, 7 Apr 2023 11:27:19 +0100 Message-Id: <20230407102721.14814-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230407102721.14814-1-jiaxun.yang@flygoat.com> References: <20230407102721.14814-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org LLVM toolchain does not support most of workarounds, detect those supports in Kconfig so we can hide unsupported workarounds to user. Signed-off-by: Jiaxun Yang Reviewed-by: Nick Desaulniers --- arch/mips/Kconfig | 28 +++++++++++++++++++++++++--- arch/mips/Makefile | 6 +++--- arch/mips/cavium-octeon/Kconfig | 1 + 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9e9de2b62f28..d896af492da6 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -371,9 +371,9 @@ config MACH_DECSTATION select CEVT_R4K if CPU_R4X00 select CSRC_IOASIC select CSRC_R4K if CPU_R4X00 - select CPU_DADDI_WORKAROUNDS if 64BIT - select CPU_R4000_WORKAROUNDS if 64BIT - select CPU_R4400_WORKAROUNDS if 64BIT + imply CPU_DADDI_WORKAROUNDS + imply CPU_R4000_WORKAROUNDS + imply CPU_R4400_WORKAROUNDS select DMA_NONCOHERENT select NO_IOPORT_MAP select IRQ_MIPS_CPU @@ -1723,6 +1723,7 @@ config CPU_JUMP_WORKAROUNDS config CPU_LOONGSON2F_WORKAROUNDS bool "Loongson 2F Workarounds" default y + depends on AS_HAS_NOP_WORKAROUNDS && AS_HAS_JUMP_WORKAROUNDS select CPU_NOP_WORKAROUNDS select CPU_JUMP_WORKAROUNDS help @@ -2456,6 +2457,7 @@ config CPU_HAS_SYNC # "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5 config CPU_DADDI_WORKAROUNDS bool + depends on CPU_R4X00_BUGS64 && CC_HAS_DADDI_WORKAROUNDS # Work around certain R4000 CPU errata (as implemented by GCC): # @@ -2477,6 +2479,7 @@ config CPU_DADDI_WORKAROUNDS # erratum #52 config CPU_R4000_WORKAROUNDS bool + depends on CPU_R4X00_BUGS64 && CC_HAS_R4000_WORKAROUNDS select CPU_R4400_WORKAROUNDS # Work around certain R4400 CPU errata (as implemented by GCC): @@ -2487,6 +2490,7 @@ config CPU_R4000_WORKAROUNDS # "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4 config CPU_R4400_WORKAROUNDS bool + depends on CPU_R4X00_BUGS64 && CC_HAS_R4400_WORKAROUNDS config CPU_R4X00_BUGS64 bool @@ -3167,6 +3171,15 @@ config CC_HAS_MNO_BRANCH_LIKELY def_bool y depends on $(cc-option,-mno-branch-likely) +config CC_HAS_R4000_WORKAROUNDS + def_bool $(cc-option,-mfix-r4000) + +config CC_HAS_R4400_WORKAROUNDS + def_bool $(cc-option,-mfix-r4400) + +config CC_HAS_DADDI_WORKAROUNDS + def_bool $(cc-option,-mno-daddi) + # https://github.com/llvm/llvm-project/issues/61045 config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH def_bool y if CC_IS_CLANG @@ -3192,6 +3205,15 @@ config AS_HAS_DSP config AS_HAS_GINV def_bool $(cc-option,-Wa$(comma)-mginv) +config AS_HAS_CN63XXP1_WORKAROUNDS + def_bool $(cc-option,-Wa$(comma)-mfix-cn63xxp1) + +config AS_HAS_NOP_WORKAROUNDS + def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-nop) + +config AS_HAS_JUMP_WORKAROUNDS + def_bool $(cc-option,-Wa$(comma)-mfix-loongson2f-jump) + menu "Power management options" config ARCH_HIBERNATION_POSSIBLE diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 3aa0f9d4ceb6..344fe5f00f7b 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -193,9 +193,9 @@ cflags-$(CONFIG_CC_IS_CLANG) += -march=mips64r2 endif cflags-$(CONFIG_CPU_LOONGSON64) += $(call cc-option,-mno-loongson-mmi) -cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += $(call cc-option,-mfix-r4000,) -cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += $(call cc-option,-mfix-r4400,) -cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += $(call cc-option,-mno-daddi,) +cflags-$(CONFIG_CPU_R4000_WORKAROUNDS) += -mfix-r4000 +cflags-$(CONFIG_CPU_R4400_WORKAROUNDS) += -mfix-r4400 +cflags-$(CONFIG_CPU_DADDI_WORKAROUNDS) += -mno-daddi ifdef CONFIG_CPU_LOONGSON2F_WORKAROUNDS cflags-$(CONFIG_CPU_NOP_WORKAROUNDS) += -Wa,-mfix-loongson2f-nop cflags-$(CONFIG_CPU_JUMP_WORKAROUNDS) += -Wa,-mfix-loongson2f-jump diff --git a/arch/mips/cavium-octeon/Kconfig b/arch/mips/cavium-octeon/Kconfig index 450e979ef5d9..38c9dc89cd5f 100644 --- a/arch/mips/cavium-octeon/Kconfig +++ b/arch/mips/cavium-octeon/Kconfig @@ -4,6 +4,7 @@ if CPU_CAVIUM_OCTEON config CAVIUM_CN63XXP1 bool "Enable CN63XXP1 errata workarounds" default "n" + depends on AS_HAS_CN63XXP1_WORKAROUNDS help The CN63XXP1 chip requires build time workarounds to function reliably, select this option to enable them. These From patchwork Fri Apr 7 10:27:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13204648 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE478C76196 for ; Fri, 7 Apr 2023 10:27:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240612AbjDGK1k (ORCPT ); Fri, 7 Apr 2023 06:27:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59300 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232920AbjDGK1e (ORCPT ); Fri, 7 Apr 2023 06:27:34 -0400 Received: from out2-smtp.messagingengine.com (out2-smtp.messagingengine.com [66.111.4.26]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 439C8A5E8 for ; Fri, 7 Apr 2023 03:27:31 -0700 (PDT) Received: from compute2.internal (compute2.nyi.internal [10.202.2.46]) by mailout.nyi.internal (Postfix) with ESMTP id 6DC215C02F9; Fri, 7 Apr 2023 06:27:30 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute2.internal (MEProxy); Fri, 07 Apr 2023 06:27:30 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1680863250; x= 1680949650; bh=aLVbYlG34KPVa/4L/3BosMypUfUvY6Vppxlepog/hIQ=; b=q vUqrek4jrhtk/d0d7sesS0v/EFPnlKX8TI3NBKJaP3ZRUQDeN3VOpga4E4UUzNlT Iu0PhR+q5gSlh/yjDK4lQ9LJIS5PdFz51aU92WcPPRcG2dSq/srb524aP6RuE7Ok 2vdmtF7cXaANcJcy/6J3jyY8PMSNLdTVfPp3N7Aq6qNY57I5hnSbsIdkeUYtK96t WCkSwpTCtpeKBkxHXPw6QPIHRMLQhvYeudypO624XiQJ3WYEl/ue7ubCwKa0lmR3 Tfov+Sob4Z+wIevz5RvrPEGnVbYlY928h/pPdqJxtpQFaccI/NbghuY43jPUHFrL 3fIZpNe8Oj1XbL8gbZwgQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1680863250; x= 1680949650; bh=aLVbYlG34KPVa/4L/3BosMypUfUvY6Vppxlepog/hIQ=; b=F yU7MITTL3GD295ghGR8ze4OES4E8IMWYyux9Xk6flRgP9r4+uKVNat2QICQgQFFk 6k5qFPufBDLv/vNY23L/KzsU97XOkPx0DnnSdAWj/UcyTYc2+6SheHz2lVhOyLOV 5K0aTHwHQ/iGFMJjw++MUDAgYwFYMSm0Y9eLPqmDXrihelC4yDch5oy67XS0Mwhq mzCqbPLUTT40uo/xnwjiJslPnY0ulvRCG5ht8f84SErlaHlhGcTJruz3rL7owGMO BS+HrrgLnAnoccvNzLiSNbX4kkNJJBzifzTNoN7nYnTDdq53OIJYG197WrfnlD/O HM7ZRoDUZWiK3PjrM+b1g== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdejhedgvdelucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfeeludefheegvdeuvd dvgeekgfdvtdettdelieeihfegtedugeekhfdvhfejfedtnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 7 Apr 2023 06:27:29 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 4/5] MIPS: Detect toolchain support of o32 ABI with 64 bit CPU Date: Fri, 7 Apr 2023 11:27:20 +0100 Message-Id: <20230407102721.14814-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230407102721.14814-1-jiaxun.yang@flygoat.com> References: <20230407102721.14814-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org LLVM is not happy with using o32 ABI on 64 bit CPU, thus build 32 bit kernel is unsupported. Detect this in Kconfig to prevent user select 32 bit kernel with unsupported toolchain. Reported-by: Nathan Chancellor Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index d896af492da6..5e399a5ac3b3 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2016,6 +2016,7 @@ choice config 32BIT bool "32-bit kernel" depends on CPU_SUPPORTS_32BIT_KERNEL && SYS_SUPPORTS_32BIT_KERNEL + depends on CC_HAS_O32_ABI select TRAD_SIGNALS help Select this option if you want to build a 32-bit kernel. @@ -3136,7 +3137,7 @@ config COMPAT config MIPS32_O32 bool "Kernel support for o32 binaries" - depends on 64BIT + depends on 64BIT && CC_HAS_O32_ABI select ARCH_WANT_OLD_COMPAT_IPC select COMPAT select MIPS32_COMPAT @@ -3184,6 +3185,10 @@ config CC_HAS_DADDI_WORKAROUNDS config CC_HAS_BROKEN_INLINE_COMPAT_BRANCH def_bool y if CC_IS_CLANG +config CC_HAS_O32_ABI + def_bool y + depends on !CPU_SUPPORTS_64BIT_KERNEL || $(cc-option,-march=mips3 -mabi=32) + config AS_HAS_MSA def_bool $(cc-option,-Wa$(comma)-mmsa) From patchwork Fri Apr 7 10:27:21 2023 Content-Type: text/plain; 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Fri, 7 Apr 2023 06:27:30 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 5/5] MIPS: Fallback CPU -march CFLAG to ISA level if unsupported Date: Fri, 7 Apr 2023 11:27:21 +0100 Message-Id: <20230407102721.14814-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230407102721.14814-1-jiaxun.yang@flygoat.com> References: <20230407102721.14814-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org LLVM does not implement some of -march option. However those march does not provide any special functionality in most cases, they just serves as compiler's tuning target. Fallback -march CFLAG to ISA level if unsupported by toolchain so we can get those kernel to build with LLVM. Reported-by: Nathan Chancellor Signed-off-by: Jiaxun Yang --- arch/mips/Makefile | 30 +++++++++++++++++------------- 1 file changed, 17 insertions(+), 13 deletions(-) diff --git a/arch/mips/Makefile b/arch/mips/Makefile index 344fe5f00f7b..eab6abeaa45c 100644 --- a/arch/mips/Makefile +++ b/arch/mips/Makefile @@ -148,10 +148,10 @@ cflags-y += $(call cc-option,-Wa$(comma)-mno-fix-loongson3-llsc,) # # CPU-dependent compiler/assembler options for optimization. # -cflags-$(CONFIG_CPU_R3000) += -march=r3000 -cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap -cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap -cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap +cflags-$(CONFIG_CPU_R3000) += $(call cc-option,-march=r3000,-march=mips1) +cflags-$(CONFIG_CPU_R4300) += $(call cc-option,-march=r4300,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_R4X00) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_TX49XX) += $(call cc-option,-march=r4600,-march=mips3) -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS32_R5) += -march=mips32r5 -Wa,--trap -modd-spreg @@ -160,19 +160,21 @@ cflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R5) += -march=mips64r5 -Wa,--trap cflags-$(CONFIG_CPU_MIPS64_R6) += -march=mips64r6 -Wa,--trap -cflags-$(CONFIG_CPU_P5600) += -march=p5600 -Wa,--trap -modd-spreg -cflags-$(CONFIG_CPU_R5000) += -march=r5000 -Wa,--trap -cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=r5000) \ +cflags-$(CONFIG_CPU_P5600) += $(call cc-option,-march=p5600,-march=mips32r5) \ + -Wa,--trap -modd-spreg +cflags-$(CONFIG_CPU_R5000) += $(call cc-option,-march=r5000,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=r5000) \ +cflags-$(CONFIG_CPU_R5500) += $(call cc-option,-march=r5500,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=r5000) \ +cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=mips4) \ -Wa,--trap -cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=r5000) \ +cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=mips4) \ + -Wa,--trap +cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx) cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d) -cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=r8000) \ +cflags-$(CONFIG_CPU_R10000) += $(call cc-option,-march=r10000,-march=mips4) \ -Wa,--trap cflags-$(CONFIG_CPU_CAVIUM_OCTEON) += $(call cc-option,-march=octeon) -Wa,--trap ifeq (,$(findstring march=octeon, $(cflags-$(CONFIG_CPU_CAVIUM_OCTEON)))) @@ -181,8 +183,10 @@ endif cflags-$(CONFIG_CAVIUM_CN63XXP1) += -Wa,-mfix-cn63xxp1 cflags-$(CONFIG_CPU_BMIPS) += -march=mips32 -Wa,-mips32 -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2E) += -march=loongson2e -Wa,--trap -cflags-$(CONFIG_CPU_LOONGSON2F) += -march=loongson2f -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2E) += \ + $(call cc-option,-march=loongson2e,-march=mips3) -Wa,--trap +cflags-$(CONFIG_CPU_LOONGSON2F) += \ + $(call cc-option,-march=loongson2f,-march=mips3) -Wa,--trap # Some -march= flags enable MMI instructions, and GCC complains about that # support being enabled alongside -msoft-float. Thus explicitly disable MMI. cflags-$(CONFIG_CPU_LOONGSON2EF) += $(call cc-option,-mno-loongson-mmi)