From patchwork Sat Apr 8 03:47:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13205586 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 319E9C7619A for ; Sat, 8 Apr 2023 03:51:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=op53fY3h3zA3HXDEuISZy4q8c7EdmKctxC5x8104Sv8=; b=0lPOkHFuK1OpspUwUyUwYLqYrs IdMsnDSol54taGmvv62R7+HWIIZT+avv9Y00T/RidB+oiTOzDK1XBjqFvGPDA8hJDie8b/rEjpFrT 4E11sA1pR29tVUdrU3Kv4uXWlQ9gn/Sdg+cUoRaUsugtv6uZMY5HdeWpvk1LkDOQRXAVn+4vD87xw mOulYAh2jL4pifhLB33MLSUsILnuj4ngppSW3osf6KxKh4fuvws17Azr+3PXSR19xWjQr7edRS1Jg BApkGYmN6bzcPcg1loy6ptVnb0V6ttcC2u5+S8fhDFQSENQT6W1q9cwNeQ+Ja73djGq4FUqR+1Mr/ 7V41cfnA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pkzab-00BfqI-1a; Sat, 08 Apr 2023 03:50:09 +0000 Received: from mail-yw1-x114a.google.com ([2607:f8b0:4864:20::114a]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pkzaX-00Bfo1-0m for linux-arm-kernel@lists.infradead.org; Sat, 08 Apr 2023 03:50:06 +0000 Received: by mail-yw1-x114a.google.com with SMTP id 00721157ae682-54ee3b24196so4122087b3.12 for ; Fri, 07 Apr 2023 20:50:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680925801; x=1683517801; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=+eQXKVk5bYBI9kU8FS6e9Eu8uo6AIYsLflVePzrnFLQ=; b=SvK9ArDgnmx3fnPqMxJtEL2EA8PQv5DaUsFb6ZhMPOQepiwwC73rxTSDunhfEkk/hU lIrPhL/eSC9EoyNsh2z9zTlSbXOc8aC1/gI0pXPrSjcY/WGhzGHiOZVJXXMH0Ne4Zm3Q woXlPoIZ/UBXaFlpUwYfR2e16fwzEEUkotPHhtuzo6vYP7RviWYk1/hG+eBoul5Cvqiw uw4a0Jx5+5Uzsbt2ouA3tcov2AMkRU42V3r4BS4uKeoppaj3o8Kh0J8mEY+kWv7f7a26 R0PWrAw6cB0T32t0JvK7/BT50X9Yzgu6qCZ7KGQ+eiL0FwPr39lUs0epEeITVdvkS8Th 69ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680925801; x=1683517801; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=+eQXKVk5bYBI9kU8FS6e9Eu8uo6AIYsLflVePzrnFLQ=; b=UfiLFnjQolX40InO953O5/WzOdDeICvepA/9S1S8QlR3lFYEVejfxDya1KTgaTtPCr mLpFVvwrNvjRvfoyXaOy2tYs9krcvddkO2XbFgRny6jdRC3Dh5Cnu9xktkItarPxLzDa Zr9aOvrceTVKFCPH24K0gngJymdzhyf2hw8J1T/NDH+I51NvXHQm0GEdBZYb+htQBGDa 4gmvXarSk/Qo/snm0yJcklgH8Y+9nBkqRtBqbQhp1Kpe4YQWF7RN6mG+T3HG+teJbYwV DY0l5Ogey3pKyAxKBgUdVWonO5bBsJyoRsBe1u8/lNUMdzbHikVWI5qA1htqirD51hXO L4fg== X-Gm-Message-State: AAQBX9dCvewm4rNIozDyeftqfyomXMhCBmMpT5R+j40CPzHmWVikl8+l iubsdNGWbyDZ7vv2IHzi9jHbbWi393k= X-Google-Smtp-Source: AKy350aQRt6i1U1RtZLFdPCYuwN2ajZD+RcM1fazysdk8uRYX0B7k4CJYjFtfCXeA2/8+WqTdrbecudjLxI= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a25:cfcf:0:b0:b8b:f1ac:9c6c with SMTP id f198-20020a25cfcf000000b00b8bf1ac9c6cmr3106735ybg.3.1680925801503; Fri, 07 Apr 2023 20:50:01 -0700 (PDT) Date: Fri, 7 Apr 2023 20:47:58 -0700 In-Reply-To: <20230408034759.2369068-1-reijiw@google.com> Mime-Version: 1.0 References: <20230408034759.2369068-1-reijiw@google.com> X-Mailer: git-send-email 2.40.0.577.gac1e443424-goog Message-ID: <20230408034759.2369068-2-reijiw@google.com> Subject: [PATCH v2 1/2] KVM: arm64: PMU: Restore the host's PMUSERENR_EL0 From: Reiji Watanabe To: Marc Zyngier , Mark Rutland , Oliver Upton , Will Deacon , Catalin Marinas , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Rob Herring , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230407_205005_276154_1BA417DA X-CRM114-Status: GOOD ( 12.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Restore the host's PMUSERENR_EL0 value instead of clearing it, before returning back to userspace, as the host's EL0 might have a direct access to PMU registers (some bits of PMUSERENR_EL0 for might not be zero for the host EL0). Fixes: 83a7a4d643d3 ("arm64: perf: Enable PMU counter userspace access for perf event") Signed-off-by: Reiji Watanabe --- arch/arm64/kvm/hyp/include/hyp/switch.h | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h index 07d37ff88a3f..6718731729fd 100644 --- a/arch/arm64/kvm/hyp/include/hyp/switch.h +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h @@ -81,7 +81,12 @@ static inline void __activate_traps_common(struct kvm_vcpu *vcpu) * EL1 instead of being trapped to EL2. */ if (kvm_arm_support_pmu_v3()) { + struct kvm_cpu_context *hctxt; + write_sysreg(0, pmselr_el0); + + hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; + ctxt_sys_reg(hctxt, PMUSERENR_EL0) = read_sysreg(pmuserenr_el0); write_sysreg(ARMV8_PMU_USERENR_MASK, pmuserenr_el0); } @@ -105,8 +110,12 @@ static inline void __deactivate_traps_common(struct kvm_vcpu *vcpu) write_sysreg(vcpu->arch.mdcr_el2_host, mdcr_el2); write_sysreg(0, hstr_el2); - if (kvm_arm_support_pmu_v3()) - write_sysreg(0, pmuserenr_el0); + if (kvm_arm_support_pmu_v3()) { + struct kvm_cpu_context *hctxt; + + hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; + write_sysreg(ctxt_sys_reg(hctxt, PMUSERENR_EL0), pmuserenr_el0); + } if (cpus_have_final_cap(ARM64_SME)) { sysreg_clear_set_s(SYS_HFGRTR_EL2, 0, From patchwork Sat Apr 8 03:47:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reiji Watanabe X-Patchwork-Id: 13205585 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99365C77B61 for ; Sat, 8 Apr 2023 03:50:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:Cc:To:From:Subject:Message-ID: References:Mime-Version:In-Reply-To:Date:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=1a7ocT+igCrnqKYCgB4dXTW8uPFvCyEsxT8lcmp4urw=; b=nWY29DyqTNv7PXCbzvfcRMSfoR z0613F1MCMNbDmfQbUa1nRVd49859OKrvfLkYEGes0HbTkL3RmurjQsj2cJ9keCywfhR+nTWndDfM omppIaPhgznyWyozM8EYNEWec7wx7F58YVmnImSug/uBJMBdCJ/eJrT3RjeYVUqI8fa1N5fR8/+zm zd8TuTuupLuPb4C24MZUgTB018CtpNW1QGSYm7OkJk6QVtGyJYS+kL4p9TykpJAyDiTbkUnQmszcK qcn/sSqeo2j2wIFz9FHruBo3M2D9vS8VcWhlYTH7bqaHQ07f9QkNqjTO4YqLCeSpQPg0UbyC6Emw1 nXM/Ctqw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pkzaY-00Bfp4-12; Sat, 08 Apr 2023 03:50:06 +0000 Received: from mail-yw1-x1149.google.com ([2607:f8b0:4864:20::1149]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pkzaW-00BfoN-0m for linux-arm-kernel@lists.infradead.org; Sat, 08 Apr 2023 03:50:05 +0000 Received: by mail-yw1-x1149.google.com with SMTP id 00721157ae682-54c119a5c44so62571947b3.2 for ; Fri, 07 Apr 2023 20:50:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20210112; t=1680925803; x=1683517803; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=DVyCnj9MsgT2gsR7e3u087HLDuT+lFbQ8wpGn1PCyY8=; b=bMzztl++BoxzD0jfOIJzKDjn9QXopp4FEjBZBoErtKInqA2ibekx4/1zj1l0CBGXmH N5YQX4LCLiwT1vid3je3dWedfXjTq8I4Bbhqnq3M0RDVclxySyIs0R4NlPYi+RMnMmwh XlDTggjdF5V7SThMmLtIB7Qfxi09ZWSlb3j6tAtiKIKPuicshrUbzHR/Xwr40rUq1ZEo 4YcxfXewagN2HeAwOVEuvWDkKQvshKe9/YBgyZtlCX/mSqAafCQVgDgoopU9v15NPBza TiCQiruWJkYyQCmU5QmRKUjiyAe1/wIcUcVAQZXjBBTv/H0vCPjuPxIP7SsPDMiSvCfg mV3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680925803; x=1683517803; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=DVyCnj9MsgT2gsR7e3u087HLDuT+lFbQ8wpGn1PCyY8=; b=Pn/oR5paG8Oa3WCigK76KbX1FHFTZSg8X3XifAXJI8i3NXJv7BCLG0gnLtWqlNsA8q R+NW9Mx/bQZBue9cX7B1g5tgoQvQ2RTGbV0W7oOQWoa5qw2sFyhIxV9Ewu6Ka1nnxGam 8bg728WZlmfWWW+aIMzSvmw9GNWBusNjXWhsXe0hGGuJzBfe8w41SOakeevu+aCfwjVz FvmmaUqA5nrC7+QD2qLKyJWwf2KgmoQbSe5E3mz6Avnip7wDt2SUnxSdxs5npH4JXWtf ZIT9SerkK18zrGAPd7Msx7gkMMKkupDJMS9XfJUW7m6uIWGZ9uA0o+vkdAzGZVUAWOQD SvNQ== X-Gm-Message-State: AAQBX9ek2dolG4Pz9g5n/D1EJhAxtVvh7/Frd8dA/QYf4FWSr2qfekgS bnS7V0I2OD/8rC/E3Qg7K0Fabp9f2Fw= X-Google-Smtp-Source: AKy350Y+PbYF40vl+ixnb0m4xqErgoFnHFSj2RsUTGKQeqQhI/G2CUtp/kJ7sXp2+MA0ejuWfd9siouXqzg= X-Received: from reijiw-west4.c.googlers.com ([fda3:e722:ac3:cc00:20:ed76:c0a8:aa1]) (user=reijiw job=sendgmr) by 2002:a25:740f:0:b0:b09:6f3d:ea1f with SMTP id p15-20020a25740f000000b00b096f3dea1fmr3081666ybc.4.1680925803168; Fri, 07 Apr 2023 20:50:03 -0700 (PDT) Date: Fri, 7 Apr 2023 20:47:59 -0700 In-Reply-To: <20230408034759.2369068-1-reijiw@google.com> Mime-Version: 1.0 References: <20230408034759.2369068-1-reijiw@google.com> X-Mailer: git-send-email 2.40.0.577.gac1e443424-goog Message-ID: <20230408034759.2369068-3-reijiw@google.com> Subject: [PATCH v2 2/2] KVM: arm64: PMU: Don't overwrite PMUSERENR with vcpu loaded From: Reiji Watanabe To: Marc Zyngier , Mark Rutland , Oliver Upton , Will Deacon , Catalin Marinas , kvmarm@lists.linux.dev Cc: kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, James Morse , Alexandru Elisei , Zenghui Yu , Suzuki K Poulose , Paolo Bonzini , Ricardo Koller , Jing Zhang , Raghavendra Rao Anata , Shaoqin Huang , Rob Herring , Reiji Watanabe X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230407_205004_284312_F2FF33B4 X-CRM114-Status: GOOD ( 20.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, with VHE, KVM sets ER, CR, SW and EN bits of PMUSERENR_EL0 to 1 on vcpu_load(), and saves and restores the register value for the host on vcpu_load() and vcpu_put(). If the value of those bits are cleared on a pCPU with a vCPU loaded (armv8pmu_start() would do that when PMU counters are programmed for the guest), PMU access from the guest EL0 might be trapped to the guest EL1 directly regardless of the current PMUSERENR_EL0 value of the vCPU. Fix this by not letting armv8pmu_start() overwrite PMUSERENR on the pCPU on which a vCPU is loaded, and instead updating the saved shadow register value for the host, so that the value can be restored on vcpu_put() later. Suggested-by: Mark Rutland Suggested-by: Marc Zyngier Fixes: 83a7a4d643d3 ("arm64: perf: Enable PMU counter userspace access for perf event") Signed-off-by: Reiji Watanabe --- arch/arm64/include/asm/kvm_host.h | 5 +++++ arch/arm64/kernel/perf_event.c | 21 ++++++++++++++++++--- arch/arm64/kvm/pmu.c | 20 ++++++++++++++++++++ 3 files changed, 43 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index bcd774d74f34..22db2f885c17 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1028,9 +1028,14 @@ void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); #ifdef CONFIG_KVM void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); void kvm_clr_pmu_events(u32 clr); +bool kvm_set_pmuserenr(u64 val); #else static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} static inline void kvm_clr_pmu_events(u32 clr) {} +static inline bool kvm_set_pmuserenr(u64 val) +{ + return false; +} #endif void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index dde06c0f97f3..0fffe4c56c28 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -741,9 +741,25 @@ static inline u32 armv8pmu_getreset_flags(void) return value; } +static void update_pmuserenr(u64 val) +{ + lockdep_assert_irqs_disabled(); + + /* + * The current pmuserenr value might be the value for the guest. + * If that's the case, have KVM keep tracking of the register value + * for the host EL0 so that KVM can restore it before returning to + * the host EL0. Otherwise, update the register now. + */ + if (kvm_set_pmuserenr(val)) + return; + + write_sysreg(val, pmuserenr_el0); +} + static void armv8pmu_disable_user_access(void) { - write_sysreg(0, pmuserenr_el0); + update_pmuserenr(0); } static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) @@ -759,8 +775,7 @@ static void armv8pmu_enable_user_access(struct arm_pmu *cpu_pmu) armv8pmu_write_evcntr(i, 0); } - write_sysreg(0, pmuserenr_el0); - write_sysreg(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR, pmuserenr_el0); + update_pmuserenr(ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_CR); } static void armv8pmu_enable_event(struct perf_event *event) diff --git a/arch/arm64/kvm/pmu.c b/arch/arm64/kvm/pmu.c index 7887133d15f0..40bb2cb13317 100644 --- a/arch/arm64/kvm/pmu.c +++ b/arch/arm64/kvm/pmu.c @@ -209,3 +209,23 @@ void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) kvm_vcpu_pmu_enable_el0(events_host); kvm_vcpu_pmu_disable_el0(events_guest); } + +/* + * With VHE, keep track of the PMUSERENR_EL0 value for the host EL0 on + * the pCPU where vCPU is loaded, since PMUSERENR_EL0 is switched to + * the value for the guest on vcpu_load(). The value for the host EL0 + * will be restored on vcpu_put(), before returning to the EL0. + * + * Return true if KVM takes care of the register. Otherwise return false. + */ +bool kvm_set_pmuserenr(u64 val) +{ + struct kvm_cpu_context *hctxt; + + if (!kvm_arm_support_pmu_v3() || !has_vhe() || !kvm_get_running_vcpu()) + return false; + + hctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; + ctxt_sys_reg(hctxt, PMUSERENR_EL0) = val; + return true; +}