From patchwork Sat Apr 8 16:04:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13205773 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59345C77B6C for ; Sat, 8 Apr 2023 16:04:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230095AbjDHQE4 (ORCPT ); Sat, 8 Apr 2023 12:04:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229658AbjDHQEx (ORCPT ); Sat, 8 Apr 2023 12:04:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 453C4D500 for ; Sat, 8 Apr 2023 09:04:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C272760B43 for ; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1C61EC433D2; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680969891; bh=ccwv9tH1t6Cn5/tuDW4QfW8z+r1vALUHZQx9EhTTIF4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oqs///SlMfArkEyC7hr6aTV8TJuqjLcFggwo97O8Ze51BhcFzmrhJCZXui0e/SPj9 A/vdBI1C4QhwdATZG09RcfGnQ3q2OfY4wiPofj5fOX65u14vhZ9TsXmYKJNbFvMOy9 YSfVPD0fk8ovzbPISxbEu8A4fczBJO8UfShQYxKGwSwHzVy8jEt+aoUbhlGzI1R0rD rlLHgHH7yNOUvFPBCHSkJLnNGjF3cDV56iOeQRjsR8TdPznHk/ck5H4UYm4MuSY0xL 4jY+15aPavHH0jbtdzyf2yEk/GOv7lVw2ftv3UAjXO+tfniuJf7kFIpca/wvdHhgl6 Pofce64LZwJNQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1plB3Y-006wc5-UL; Sat, 08 Apr 2023 17:04:48 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon Subject: [PATCH v2 1/5] KVM: arm64: nvhe: Synchronise with page table walker on vcpu run Date: Sat, 8 Apr 2023 17:04:23 +0100 Message-Id: <20230408160427.10672-2-maz@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408160427.10672-1-maz@kernel.org> References: <20230408160427.10672-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org When taking an exception between the EL1&0 translation regime and the EL2 translation regime, the page table walker is allowed to complete the walks started from EL0 or EL1 while running at EL2. It means that altering the system registers that define the EL1&0 translation regime is fraught with danger *unless* we wait for the completion of such walk with a DSB (R_LFHQG and subsequent statements in the ARM ARM). We already did the right thing for other external agents (SPE, TRBE), but not the PTW. Rework the existing SPE/TRBE synchronisation to include the PTW, and add the missing DSB on guest exit. Signed-off-by: Marc Zyngier Reviewed-by: Oliver Upton --- arch/arm64/kvm/hyp/nvhe/debug-sr.c | 2 -- arch/arm64/kvm/hyp/nvhe/switch.c | 18 ++++++++++++++++++ 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/hyp/nvhe/debug-sr.c b/arch/arm64/kvm/hyp/nvhe/debug-sr.c index 2673bde62fad..d756b939f296 100644 --- a/arch/arm64/kvm/hyp/nvhe/debug-sr.c +++ b/arch/arm64/kvm/hyp/nvhe/debug-sr.c @@ -37,7 +37,6 @@ static void __debug_save_spe(u64 *pmscr_el1) /* Now drain all buffered data to memory */ psb_csync(); - dsb(nsh); } static void __debug_restore_spe(u64 pmscr_el1) @@ -69,7 +68,6 @@ static void __debug_save_trace(u64 *trfcr_el1) isb(); /* Drain the trace buffer to memory */ tsb_csync(); - dsb(nsh); } static void __debug_restore_trace(u64 trfcr_el1) diff --git a/arch/arm64/kvm/hyp/nvhe/switch.c b/arch/arm64/kvm/hyp/nvhe/switch.c index c2cb46ca4fb6..71fa16a0dc77 100644 --- a/arch/arm64/kvm/hyp/nvhe/switch.c +++ b/arch/arm64/kvm/hyp/nvhe/switch.c @@ -272,6 +272,17 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) */ __debug_save_host_buffers_nvhe(vcpu); + /* + * We're about to restore some new MMU state. Make sure + * ongoing page-table walks that have started before we + * trapped to EL2 have completed. This also synchronises the + * above disabling of SPE and TRBE. + * + * See DDI0487I.a D8.1.5 "Out-of-context translation regimes", + * rule R_LFHQG and subsequent information statements. + */ + dsb(nsh); + __kvm_adjust_pc(vcpu); /* @@ -306,6 +317,13 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) __timer_disable_traps(vcpu); __hyp_vgic_save_state(vcpu); + /* + * Same thing as before the guest run: we're about to switch + * the MMU context, so let's make sure we don't have any + * ongoing EL1&0 translations. + */ + dsb(nsh); + __deactivate_traps(vcpu); __load_host_stage2(); From patchwork Sat Apr 8 16:04:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13205772 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0368EC7619A for ; Sat, 8 Apr 2023 16:04:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229913AbjDHQEz (ORCPT ); Sat, 8 Apr 2023 12:04:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41598 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229557AbjDHQEx (ORCPT ); Sat, 8 Apr 2023 12:04:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F2DBCA15 for ; Sat, 8 Apr 2023 09:04:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C3EB460B90 for ; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 15A3FC4339C; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680969891; bh=KDMzZnxGApiibVRs6k92CdWB6ULcQmnVKHVOc063tfE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lRvWeQWO7gL2yAXqSzOcY7kFQS9LVysNXSBEXDYA6idP/yUhdlUL/kQflwieh3VUj m83JdMFiVf8j3HLKJcta1Wg7ofnq/zE/rQcGpOA5Znf2LQud0aN5hmUx1EZVWObiiP pZPf2mM0VizVsa+37PusAUbUjDyCJPvrIUIed+GLQJU3Q2uFJirkJv/iVcoYw1/Zeo lM69vVY0IERzvukEJza7VRc76+rrUs+i4OkUbNceJ0wBJYdZ8gIxfhv88gXt4DrhFY 0OF/n8GOeP8BNEbhvDF0Qo2auafZKxiNqndFKeTCkWmTnnyVoYmqUdHrGSAHyavAfJ +MuRXwTcpSLXA== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1plB3Z-006wc5-3z; Sat, 08 Apr 2023 17:04:49 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon Subject: [PATCH v2 2/5] KVM: arm64: nvhe: Synchronise with page table walker on TLBI Date: Sat, 8 Apr 2023 17:04:24 +0100 Message-Id: <20230408160427.10672-3-maz@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408160427.10672-1-maz@kernel.org> References: <20230408160427.10672-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org A TLBI from EL2 impacting EL1 involves messing with the EL1&0 translation regime, and the page table walker may still be performing speculative walks. Piggyback on the existing DSBs to always have a DSB ISH that will synchronise all load/store operations that the PTW may still have. Signed-off-by: Marc Zyngier --- arch/arm64/kvm/hyp/nvhe/tlb.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kvm/hyp/nvhe/tlb.c b/arch/arm64/kvm/hyp/nvhe/tlb.c index d296d617f589..e86dd04d49ff 100644 --- a/arch/arm64/kvm/hyp/nvhe/tlb.c +++ b/arch/arm64/kvm/hyp/nvhe/tlb.c @@ -17,6 +17,23 @@ struct tlb_inv_context { static void __tlb_switch_to_guest(struct kvm_s2_mmu *mmu, struct tlb_inv_context *cxt) { + /* + * We have two requirements: + * + * - ensure that the page table updates are visible to all + * CPUs, for which a dsb(ishst) is what we need + * + * - complete any speculative page table walk started before + * we trapped to EL2 so that we can mess with the MM + * registers out of context, for which dsb(nsh) is enough + * + * The composition of these two barriers is a dsb(ish). This + * might be slightly over the top for non-shareable TLBIs, but + * they are so vanishingly rare that it isn't worth the + * complexity. + */ + dsb(ish); + if (cpus_have_final_cap(ARM64_WORKAROUND_SPECULATIVE_AT)) { u64 val; @@ -60,8 +77,6 @@ void __kvm_tlb_flush_vmid_ipa(struct kvm_s2_mmu *mmu, { struct tlb_inv_context cxt; - dsb(ishst); - /* Switch to requested VMID */ __tlb_switch_to_guest(mmu, &cxt); @@ -113,8 +128,6 @@ void __kvm_tlb_flush_vmid(struct kvm_s2_mmu *mmu) { struct tlb_inv_context cxt; - dsb(ishst); - /* Switch to requested VMID */ __tlb_switch_to_guest(mmu, &cxt); @@ -142,7 +155,8 @@ void __kvm_flush_cpu_context(struct kvm_s2_mmu *mmu) void __kvm_flush_vm_context(void) { - dsb(ishst); + /* Same remark as in __tblb_switch_to_guest() */ + dsb(ish); __tlbi(alle1is); /* From patchwork Sat Apr 8 16:04:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13205774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 18AE8C77B6E for ; Sat, 8 Apr 2023 16:04:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230104AbjDHQE5 (ORCPT ); Sat, 8 Apr 2023 12:04:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229748AbjDHQEx (ORCPT ); Sat, 8 Apr 2023 12:04:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CAF1D51B for ; Sat, 8 Apr 2023 09:04:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E3DC060BC5 for ; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49646C433A1; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680969891; bh=US5LgOkEdpl62fowcQRVYLy7fF93C93CA99kNdbfIwI=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=BCY4S7kWTdXK/2/LcY/9XEjNkufz63Sd0hwrG/JptxZTNYLbu/WqS40lujYVz+ZyM dLRFUiN67+D/4BoIJOTNfc8v6spJksqUO3mHZCNdnjPh81DOSmVUBLZn3PrTccaslR KFneTOaNzZd56mLaPylMgBG/NVMyjgMji6ZXuUz9oIc3jB6HrT7P2o5HLoOWQrLDHT ePL92dtJijcNAXz2QtB/IAqVymYUwSOBJStvNOB6kh7Id3kdPnCWkNF1anUkXWSMHZ zJrCQ2/PJkVjPD+PJBsAH6svMfoTrshwiy6FO4Ba6Peiu5KDylHKemcjIX/WxQVq5/ /ukYx8WpuQJZg== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1plB3Z-006wc5-9n; Sat, 08 Apr 2023 17:04:49 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon Subject: [PATCH v2 3/5] KVM: arm64: pkvm: Document the side effects of kvm_flush_dcache_to_poc() Date: Sat, 8 Apr 2023 17:04:25 +0100 Message-Id: <20230408160427.10672-4-maz@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408160427.10672-1-maz@kernel.org> References: <20230408160427.10672-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We rely on the presence of a DSB at the end of kvm_flush_dcache_to_poc() that, on top of ensuring completion of the cache clean, also covers the speculative page table walk started from EL1. Document this dependency. Signed-off-by: Marc Zyngier Reviewed-by: Oliver Upton --- arch/arm64/kvm/hyp/nvhe/mem_protect.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/kvm/hyp/nvhe/mem_protect.c b/arch/arm64/kvm/hyp/nvhe/mem_protect.c index 552653fa18be..2e9ec4a2a4a3 100644 --- a/arch/arm64/kvm/hyp/nvhe/mem_protect.c +++ b/arch/arm64/kvm/hyp/nvhe/mem_protect.c @@ -297,6 +297,13 @@ int __pkvm_prot_finalize(void) params->vttbr = kvm_get_vttbr(mmu); params->vtcr = host_mmu.arch.vtcr; params->hcr_el2 |= HCR_VM; + + /* + * The CMO below not only cleans the updated params to the + * PoC, but also provides the DSB that ensures ongoing + * page-table walks that have started before we trapped to EL2 + * have completed. + */ kvm_flush_dcache_to_poc(params, sizeof(*params)); write_sysreg(params->hcr_el2, hcr_el2); From patchwork Sat Apr 8 16:04:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13205776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04DB8C77B6C for ; Sat, 8 Apr 2023 16:05:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230140AbjDHQFB (ORCPT ); Sat, 8 Apr 2023 12:05:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41620 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229845AbjDHQEx (ORCPT ); Sat, 8 Apr 2023 12:04:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8AADCFF0F for ; Sat, 8 Apr 2023 09:04:52 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id E6E2760C11 for ; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49675C433A7; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680969891; bh=o/DlzcCv84E0d74WXt/xXFCBSqi2CyUM8zi9WxCI7Us=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=klPdRbLe352Fge1Qc59RuURYq2dt6qvaWC+FY7ocmmamZ0T3D+SCYF0E+cHnPMWXL NQW76nhH62ihWXnx2y7M4Zm+Ek6bByRzQLj758zWzs2Ed7qtTbXXBEQGBT8S11yI+j 8Wd9fC++KB4wfMa6Hm+nhjjJDEue+1i7r5Yf549F5EQhxRHRp6TFcrIM8M2uxUO1tO fc6RCgUxCM8JE3X5wqcDMpmfN5Zd+oCigqe0KL1++Wd8RouWFSvFpJkRcI4ILL+06k OaI+rV/8P8D0O2o7dTY64FFOZZyV8sQbulf+Sad2t/ilMoxrYmLmBVDAFvjaWlw1Mu U3zdoe+5QnJXw== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1plB3Z-006wc5-FR; Sat, 08 Apr 2023 17:04:49 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon Subject: [PATCH v2 4/5] KVM: arm64: vhe: Synchronise with page table walker on MMU update Date: Sat, 8 Apr 2023 17:04:26 +0100 Message-Id: <20230408160427.10672-5-maz@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408160427.10672-1-maz@kernel.org> References: <20230408160427.10672-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Contrary to nVHE, VHE is a lot easier when it comes to dealing with speculative page table walks started at EL1. As we only change EL1&0 translation regime when context-switching, we already benefit from the effect of the DSB that sits in the context switch code. We only need to take care of it in the NV case, where we can flip between between two EL1 contexts (one of them being the virtual EL2) without a context switch. Signed-off-by: Marc Zyngier Reviewed-by: Oliver Upton --- arch/arm64/kvm/hyp/vhe/sysreg-sr.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c index 7b44f6b3b547..b35a178e7e0d 100644 --- a/arch/arm64/kvm/hyp/vhe/sysreg-sr.c +++ b/arch/arm64/kvm/hyp/vhe/sysreg-sr.c @@ -13,6 +13,7 @@ #include #include #include +#include /* * VHE: Host and guest must save mdscr_el1 and sp_el0 (and the PC and @@ -69,6 +70,17 @@ void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu) host_ctxt = &this_cpu_ptr(&kvm_host_data)->host_ctxt; __sysreg_save_user_state(host_ctxt); + /* + * When running a normal EL1 guest, we only load a new vcpu + * after a context switch, which imvolves a DSB, so all + * speculative EL1&0 walks will have already completed. + * If running NV, the vcpu may transition between vEL1 and + * vEL2 without a context switch, so make sure we complete + * those walks before loading a new context. + */ + if (vcpu_has_nv(vcpu)) + dsb(nsh); + /* * Load guest EL1 and user state * From patchwork Sat Apr 8 16:04:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marc Zyngier X-Patchwork-Id: 13205777 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7325C7619A for ; Sat, 8 Apr 2023 16:05:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230139AbjDHQFA (ORCPT ); Sat, 8 Apr 2023 12:05:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229899AbjDHQEy (ORCPT ); Sat, 8 Apr 2023 12:04:54 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A12FFF15 for ; Sat, 8 Apr 2023 09:04:53 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 554DF60C97 for ; Sat, 8 Apr 2023 16:04:52 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7D938C433AC; Sat, 8 Apr 2023 16:04:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1680969891; bh=34/Zlt4htBGJgLYgA2mf1PBt32s5lUf3YI5evv+PwzE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jV+8Kwh1lmVgBvYGcG+iC3fyA5kwntvZUgWIUpSeVIpcdceElV3iV+G9LYPudTIRy +pn5TobDu3KgReOMqXKiQDtiXrwrrd8dmySbRIn0nISnHCfGol9ZKg4wWN6dLPFgej VJydRLx166oCho6nN2S4d252TcUO9v+v6BE6Ax2t9fnt8yYgDYJCgxcLaynT7x5cwu qo6nM5tRALtzxPYYKI4AzH0V7C5QpD1lmRlxcmPkIEo2H4I0G8OLuUpGHlGY1wzLRs JaO7AKKGjvRr7I7MEBIrt1T5yftAoQL47I2Vd+6ssVptEYHn4BOrGeqRWCuHCMQ7KI LQ9JyBNFr1a0Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=valley-girl.lan) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1plB3Z-006wc5-LH; Sat, 08 Apr 2023 17:04:49 +0100 From: Marc Zyngier To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: James Morse , Suzuki K Poulose , Oliver Upton , Zenghui Yu , Will Deacon Subject: [PATCH v2 5/5] KVM: arm64: vhe: Drop extra isb() on guest exit Date: Sat, 8 Apr 2023 17:04:27 +0100 Message-Id: <20230408160427.10672-6-maz@kernel.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230408160427.10672-1-maz@kernel.org> References: <20230408160427.10672-1-maz@kernel.org> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-arm-kernel@lists.infradead.org, james.morse@arm.com, suzuki.poulose@arm.com, oliver.upton@linux.dev, yuzenghui@huawei.com, will@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org __kvm_vcpu_run_vhe() end on VHE with an isb(). However, this function is only reachable via kvm_call_hyp_ret(), which already contains an isb() in order to mimick the behaviour of nVHE and provide a context synchronisation event. We thus have two isb()s back to back, which is one too many. Drop the first one and solely rely on the one in the helper. Signed-off-by: Marc Zyngier Reviewed-by: Oliver Upton --- arch/arm64/kvm/hyp/vhe/switch.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/arch/arm64/kvm/hyp/vhe/switch.c b/arch/arm64/kvm/hyp/vhe/switch.c index cd3f3117bf16..3d868e84c7a0 100644 --- a/arch/arm64/kvm/hyp/vhe/switch.c +++ b/arch/arm64/kvm/hyp/vhe/switch.c @@ -227,11 +227,10 @@ int __kvm_vcpu_run(struct kvm_vcpu *vcpu) /* * When we exit from the guest we change a number of CPU configuration - * parameters, such as traps. Make sure these changes take effect - * before running the host or additional guests. + * parameters, such as traps. We rely on the isb() in kvm_call_hyp*() + * to make sure these changes take effect before running the host or + * additional guests. */ - isb(); - return ret; }