From patchwork Sun Apr 9 10:43:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13205919 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7958BC77B61 for ; Sun, 9 Apr 2023 10:43:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229510AbjDIKnZ (ORCPT ); Sun, 9 Apr 2023 06:43:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229454AbjDIKnY (ORCPT ); Sun, 9 Apr 2023 06:43:24 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B0884483 for ; Sun, 9 Apr 2023 03:43:22 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id BEA4832004ED; Sun, 9 Apr 2023 06:43:20 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Sun, 09 Apr 2023 06:43:21 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1681037000; x= 1681123400; bh=qWe8IvdF8H4iL7FM6XSpQ2R8Ky2u8F7Wy+R83JW6slo=; b=q mMD7CzvRnP2kSYszneyd9I2hjzSU95qJ9yP3JI73EisP1AYhvjN3KeA3SxMzHJHU RMincMhNbhf4jobnP684Jx5PiP3r9vOS87aLKUDk0acAoB6W6PCW4HvbCkqmfkf4 QzLAoO+yOYn8FbtXXYFNvvuzsbH32BIy74oisRTs+F9NrhJ6lqejZedM8PhOE2ke eK8slbNwX0f83FEy2MI6iUFEpqx9R4cFHX+ocoSLcYlweWJHilIZ7nrOzsMrQOfP Kjnh0REyPDfpqJLVw65zmFJzvx7ezFW67ezXrTCupMLY7VNHy3j2eUqjw+9UcWeo W1M/k9bBdHq8qCjdWEuWQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1681037000; x= 1681123400; bh=qWe8IvdF8H4iL7FM6XSpQ2R8Ky2u8F7Wy+R83JW6slo=; b=m KogR8JOoStK1MrGEgFuKeJBe2pwN5QSH75Wcjdc62Hsud7moePEj8zZqXSQkFp6q zZj9tLeI2QSk02zWFmyNI1w7CvBnMR6C778fPSF70pCzDcYhyk8WRGxEYgTAXRNc p6Xn4+AYvRSeZ2mH0UEB11xB1ETvbkynTDAXzboIEbx1pVwF6MvjhIZnL0bDnLYw KPDmJs9mj5RgwiiaGUsrxYW1Ywnlq+kQW5lRlXSuLCazzaE54Tatbv8EdgemMeBj YNy2lLHmu8ie4NgGqZlgRbGxODMT3Gw3tb6MPFHmPCuSxvGpijDPN6oP6Bxu0EyJ FS0skuIsdbYQz0gX/1Y3Q== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdektddgfedvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfffhtdfhfeeuteefhf egkeefkeeitdfghedukeetkedtvdekieegleetkeeutddunecuffhomhgrihhnpehslhgv vghpvghrrdhssgdpvhgvtgdrshgspdhgvghnvgigrdhssgdpfhhpuhdrshgspdhprghrth hirghlrdhssgdptggvgidqohgtthdrshgsnecuvehluhhsthgvrhfuihiivgeptdenucfr rghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhihgohgrthdrtg homh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 9 Apr 2023 06:43:19 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 1/8] MIPS: Replace assembly isa level directives with macros Date: Sun, 9 Apr 2023 11:43:02 +0100 Message-Id: <20230409104309.13887-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230409104309.13887-1-jiaxun.yang@flygoat.com> References: <20230409104309.13887-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org There are tons of .set assembly isa level directives in tree to set current isa level to a higher level to enable some features. However as nowadays MIPS is shuffling around opcodes, a single ISA level setting may result wrong opcode in binary. We had MIPS_ISA_LEVEL macros to determine most appropriate superset of ISA level, just do a tree wide replacement to take advantage of those macros. Mapping: arch=r4000 -> MIPS_ISA_ARCH_LEVEL {mips1, mips3, mips32r2, mips64r2} -> MIPS_ISA_LEVEL {mips32r5, mips64r5} -> Special case for VZ, mips64r5 if target ISA is lower than R5, otherwise MIPS_ISA_LEVEL Signed-off-by: Jiaxun Yang --- arch/mips/alchemy/common/sleeper.S | 6 ++-- arch/mips/include/asm/asmmacro.h | 32 ++++++++++---------- arch/mips/include/asm/futex.h | 8 ++--- arch/mips/include/asm/hazards.h | 2 +- arch/mips/include/asm/io.h | 4 +-- arch/mips/include/asm/mipsmtregs.h | 18 ++++++------ arch/mips/include/asm/mipsregs.h | 47 +++++++++++++++++------------- arch/mips/include/asm/stackframe.h | 2 +- arch/mips/kernel/bmips_vec.S | 4 +-- arch/mips/kernel/csrc-r4k.c | 2 +- arch/mips/kernel/genex.S | 8 ++--- arch/mips/kernel/idle.c | 6 ++-- arch/mips/kernel/r4k_fpu.S | 4 +-- arch/mips/kernel/syscall.c | 2 +- arch/mips/lantiq/clk.c | 2 +- arch/mips/lib/csum_partial.S | 5 ++-- arch/mips/mm/c-r4k.c | 2 +- arch/mips/mm/cex-oct.S | 2 +- arch/mips/mm/sc-ip22.c | 6 ++-- 19 files changed, 85 insertions(+), 77 deletions(-) diff --git a/arch/mips/alchemy/common/sleeper.S b/arch/mips/alchemy/common/sleeper.S index 13586d224314..e19f20223aac 100644 --- a/arch/mips/alchemy/common/sleeper.S +++ b/arch/mips/alchemy/common/sleeper.S @@ -91,7 +91,7 @@ LEAF(alchemy_sleep_au1000) /* cache following instructions, as memory gets put to sleep */ la t0, 1f - .set arch=r4000 + .set MIPS_ISA_ARCH_LEVEL_RAW cache 0x14, 0(t0) cache 0x14, 32(t0) cache 0x14, 64(t0) @@ -117,7 +117,7 @@ LEAF(alchemy_sleep_au1550) /* cache following instructions, as memory gets put to sleep */ la t0, 1f - .set arch=r4000 + .set MIPS_ISA_ARCH_LEVEL_RAW cache 0x14, 0(t0) cache 0x14, 32(t0) cache 0x14, 64(t0) @@ -159,7 +159,7 @@ LEAF(alchemy_sleep_au1300) la t1, 4f subu t2, t1, t0 - .set arch=r4000 + .set MIPS_ISA_ARCH_LEVEL_RAW 1: cache 0x14, 0(t0) subu t2, t2, 32 diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 74c2dedc55b4..2491a6c68390 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -107,7 +107,7 @@ .macro fpu_save_16odd thread .set push - .set mips64r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set hardfloat sdc1 $f1, THREAD_FPR1(\thread) @@ -166,7 +166,7 @@ .macro fpu_restore_16odd thread .set push - .set mips64r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set hardfloat ldc1 $f1, THREAD_FPR1(\thread) @@ -242,7 +242,7 @@ #ifdef CONFIG_AS_HAS_MSA .macro _cfcmsa rd, cs .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa cfcmsa \rd, $\cs @@ -251,7 +251,7 @@ .macro _ctcmsa cd, rs .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa ctcmsa $\cd, \rs @@ -260,7 +260,7 @@ .macro ld_b wd, off, base .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa ld.b $w\wd, \off(\base) @@ -269,7 +269,7 @@ .macro ld_h wd, off, base .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa ld.h $w\wd, \off(\base) @@ -278,7 +278,7 @@ .macro ld_w wd, off, base .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa ld.w $w\wd, \off(\base) @@ -287,7 +287,7 @@ .macro ld_d wd, off, base .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa ld.d $w\wd, \off(\base) @@ -296,7 +296,7 @@ .macro st_b wd, off, base .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa st.b $w\wd, \off(\base) @@ -305,7 +305,7 @@ .macro st_h wd, off, base .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa st.h $w\wd, \off(\base) @@ -314,7 +314,7 @@ .macro st_w wd, off, base .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa st.w $w\wd, \off(\base) @@ -323,7 +323,7 @@ .macro st_d wd, off, base .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa st.d $w\wd, \off(\base) @@ -332,7 +332,7 @@ .macro copy_s_w ws, n .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa copy_s.w $1, $w\ws[\n] @@ -341,7 +341,7 @@ .macro copy_s_d ws, n .set push - .set mips64r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa copy_s.d $1, $w\ws[\n] @@ -350,7 +350,7 @@ .macro insert_w wd, n .set push - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa insert.w $w\wd[\n], $1 @@ -359,7 +359,7 @@ .macro insert_d wd, n .set push - .set mips64r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 .set msa insert.d $w\wd[\n], $1 diff --git a/arch/mips/include/asm/futex.h b/arch/mips/include/asm/futex.h index 05832eb240fa..2107e536a308 100644 --- a/arch/mips/include/asm/futex.h +++ b/arch/mips/include/asm/futex.h @@ -29,11 +29,11 @@ " .set push \n" \ " .set noat \n" \ " .set push \n" \ - " .set arch=r4000 \n" \ + " .set "MIPS_ISA_ARCH_LEVEL" \n" \ "1: ll %1, %4 # __futex_atomic_op \n" \ " .set pop \n" \ " " insn " \n" \ - " .set arch=r4000 \n" \ + " .set "MIPS_ISA_ARCH_LEVEL" \n" \ "2: sc $1, %2 \n" \ " beqzl $1, 1b \n" \ __stringify(__WEAK_LLSC_MB) " \n" \ @@ -144,12 +144,12 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, " .set push \n" " .set noat \n" " .set push \n" - " .set arch=r4000 \n" + " .set "MIPS_ISA_ARCH_LEVEL" \n" "1: ll %1, %3 \n" " bne %1, %z4, 3f \n" " .set pop \n" " move $1, %z5 \n" - " .set arch=r4000 \n" + " .set "MIPS_ISA_ARCH_LEVEL" \n" "2: sc $1, %2 \n" " beqzl $1, 1b \n" __stringify(__WEAK_LLSC_MB) " \n" diff --git a/arch/mips/include/asm/hazards.h b/arch/mips/include/asm/hazards.h index cb16be93b048..ca18c66530e8 100644 --- a/arch/mips/include/asm/hazards.h +++ b/arch/mips/include/asm/hazards.h @@ -144,7 +144,7 @@ do { \ \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips64r2 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " dla %0, 1f \n" \ " jr.hb %0 \n" \ " .set pop \n" \ diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h index cc28d207a061..e2ec7ec3dc20 100644 --- a/arch/mips/include/asm/io.h +++ b/arch/mips/include/asm/io.h @@ -243,7 +243,7 @@ static inline void pfx##write##bwlq(type val, \ local_irq_save(__flags); \ __asm__ __volatile__( \ ".set push" "\t\t# __writeq""\n\t" \ - ".set arch=r4000" "\n\t" \ + ".set "MIPS_ISA_ARCH_LEVEL "\n\t" \ "dsll32 %L0, %L0, 0" "\n\t" \ "dsrl32 %L0, %L0, 0" "\n\t" \ "dsll32 %M0, %M0, 0" "\n\t" \ @@ -277,7 +277,7 @@ static inline type pfx##read##bwlq(const volatile void __iomem *mem) \ local_irq_save(__flags); \ __asm__ __volatile__( \ ".set push" "\t\t# __readq" "\n\t" \ - ".set arch=r4000" "\n\t" \ + ".set "MIPS_ISA_ARCH_LEVEL "\n\t" \ "ld %L0, %1" "\n\t" \ "dsra32 %M0, %L0, 0" "\n\t" \ "sll %L0, %L0, 0" "\n\t" \ diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h index a8d67c2f4f7b..b6dea86b1b82 100644 --- a/arch/mips/include/asm/mipsmtregs.h +++ b/arch/mips/include/asm/mipsmtregs.h @@ -197,7 +197,7 @@ static inline unsigned int dvpe(void) " .set push \n" " .set noreorder \n" " .set noat \n" - " .set mips32r2 \n" + " .set "MIPS_ISA_LEVEL" \n" " .word 0x41610001 # dvpe $1 \n" " move %0, $1 \n" " ehb \n" @@ -215,7 +215,7 @@ static inline void __raw_evpe(void) " .set push \n" " .set noreorder \n" " .set noat \n" - " .set mips32r2 \n" + " .set "MIPS_ISA_LEVEL" \n" " .word 0x41600021 # evpe \n" " ehb \n" " .set pop \n"); @@ -238,7 +238,7 @@ static inline unsigned int dmt(void) __asm__ __volatile__( " .set push \n" - " .set mips32r2 \n" + " .set "MIPS_ISA_LEVEL" \n" " .set noat \n" " .word 0x41610BC1 # dmt $1 \n" " ehb \n" @@ -256,7 +256,7 @@ static inline void __raw_emt(void) __asm__ __volatile__( " .set push \n" " .set noreorder \n" - " .set mips32r2 \n" + " .set "MIPS_ISA_LEVEL" \n" " .word 0x41600be1 # emt \n" " ehb \n" " .set pop"); @@ -277,7 +277,7 @@ static inline void ehb(void) { __asm__ __volatile__( " .set push \n" - " .set mips32r2 \n" + " .set "MIPS_ISA_LEVEL" \n" " ehb \n" " .set pop \n"); } @@ -288,7 +288,7 @@ static inline void ehb(void) \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips32r2 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " .set noat \n" \ " # mftc0 $1, $" #rt ", " #sel " \n" \ " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ @@ -306,7 +306,7 @@ static inline void ehb(void) __asm__ __volatile__( \ " .set push \n" \ " .set noat \n" \ - " .set mips32r2 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " # mftgpr $1," #rt " \n" \ " .word 0x41000820 | (" #rt " << 16) \n" \ " move %0, $1 \n" \ @@ -331,7 +331,7 @@ static inline void ehb(void) do { \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips32r2 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " .set noat \n" \ " move $1, %0 \n" \ " # mttgpr $1, " #rd " \n" \ @@ -344,7 +344,7 @@ do { \ ({ \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips32r2 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " .set noat \n" \ " move $1, %0 \n" \ " # mttc0 %0," #rd ", " #sel " \n" \ diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 8f0ebc399338..9d928b952abf 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1421,7 +1421,7 @@ do { \ else \ __asm__ vol( \ ".set\tpush\n\t" \ - ".set\tmips32\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "mfc0\t%0, " #source ", " #sel "\n\t" \ ".set\tpop\n\t" \ : "=r" (__res)); \ @@ -1435,14 +1435,14 @@ do { \ else if (sel == 0) \ __asm__ vol( \ ".set\tpush\n\t" \ - ".set\tmips3\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "dmfc0\t%0, " #source "\n\t" \ ".set\tpop" \ : "=r" (__res)); \ else \ __asm__ vol( \ ".set\tpush\n\t" \ - ".set\tmips64\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "dmfc0\t%0, " #source ", " #sel "\n\t" \ ".set\tpop" \ : "=r" (__res)); \ @@ -1470,7 +1470,7 @@ do { \ else \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips32\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "mtc0\t%z0, " #register ", " #sel "\n\t" \ ".set\tpop" \ : : "Jr" ((unsigned int)(value))); \ @@ -1483,14 +1483,14 @@ do { \ else if (sel == 0) \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips3\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "dmtc0\t%z0, " #register "\n\t" \ ".set\tpop" \ : : "Jr" (value)); \ else \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "dmtc0\t%z0, " #register ", " #sel "\n\t" \ ".set\tpop" \ : : "Jr" (value)); \ @@ -1545,7 +1545,7 @@ do { \ if (sel == 0) \ __asm__ vol( \ ".set\tpush\n\t" \ - ".set\tmips64\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "dmfc0\t%L0, " #source "\n\t" \ "dsra\t%M0, %L0, 32\n\t" \ "sll\t%L0, %L0, 0\n\t" \ @@ -1554,7 +1554,7 @@ do { \ else \ __asm__ vol( \ ".set\tpush\n\t" \ - ".set\tmips64\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "dmfc0\t%L0, " #source ", " #sel "\n\t" \ "dsra\t%M0, %L0, 32\n\t" \ "sll\t%L0, %L0, 0\n\t" \ @@ -1582,7 +1582,7 @@ do { \ else if (sel == 0) \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "dsll\t%L0, %L0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ "dsll\t%M0, %M0, 32\n\t" \ @@ -1593,7 +1593,7 @@ do { \ else \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64\n\t" \ + ".set\t "MIPS_ISA_LEVEL" \n\t" \ "dsll\t%L0, %L0, 32\n\t" \ "dsrl\t%L0, %L0, 32\n\t" \ "dsll\t%M0, %M0, 32\n\t" \ @@ -1628,7 +1628,7 @@ do { \ \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips32r2 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ _ASM_SET_MFHC0 \ " mfhc0 %0, " #source ", %1 \n" \ _ASM_UNSET_MFHC0 \ @@ -1642,7 +1642,7 @@ do { \ do { \ __asm__ __volatile__( \ " .set push \n" \ - " .set mips32r2 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ _ASM_SET_MTHC0 \ " mthc0 %z0, " #register ", %1 \n" \ _ASM_UNSET_MTHC0 \ @@ -2040,7 +2040,14 @@ do { \ * Macros to access the guest system control coprocessor */ -#ifndef CONFIG_AS_HAS_VIRT +#if MIPS_ISA_REV < 5 +/* VZ ASE should be able to work with Release 2 but LLVM thinks it needs R5 */ +#define MIPS_ISA_LEVEL_VIRT "mips64r5" +#else +#define MIPS_ISA_LEVEL_VIRT MIPS_ISA_LEVEL +#endif + +#ifndef TOOLCHAIN_SUPPORTS_VIRT #define _ASM_SET_MFGC0 \ _ASM_MACRO_2R_1S(mfgc0, rt, rs, sel, \ _ASM_INSN_IF_MIPS(0x40600000 | __rt << 16 | __rs << 11 | \\sel) \ @@ -2099,7 +2106,7 @@ do { \ ({ int __res; \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips32r5\n\t" \ + ".set\t " MIPS_ISA_LEVEL_VIRT " \n\t" \ _ASM_SET_MFGC0 \ "mfgc0\t%0, " #source ", %1\n\t" \ _ASM_UNSET_MFGC0 \ @@ -2113,7 +2120,7 @@ do { \ ({ unsigned long long __res; \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64r5\n\t" \ + ".set\t " MIPS_ISA_LEVEL_VIRT " \n\t" \ _ASM_SET_DMFGC0 \ "dmfgc0\t%0, " #source ", %1\n\t" \ _ASM_UNSET_DMFGC0 \ @@ -2127,7 +2134,7 @@ do { \ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips32r5\n\t" \ + ".set\t " MIPS_ISA_LEVEL_VIRT " \n\t" \ _ASM_SET_MTGC0 \ "mtgc0\t%z0, " #register ", %1\n\t" \ _ASM_UNSET_MTGC0 \ @@ -2140,7 +2147,7 @@ do { \ do { \ __asm__ __volatile__( \ ".set\tpush\n\t" \ - ".set\tmips64r5\n\t" \ + ".set\t " MIPS_ISA_LEVEL_VIRT " \n\t" \ _ASM_SET_DMTGC0 \ "dmtgc0\t%z0, " #register ", %1\n\t" \ _ASM_UNSET_DMTGC0 \ @@ -2376,7 +2383,7 @@ do { \ " .set reorder \n" \ " # gas fails to assemble cfc1 for some archs, \n" \ " # like Octeon. \n" \ - " .set mips1 \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ " .set hardfloat \n" \ " cfc1 %0,"STR(source)" \n" \ " .set pop \n" \ @@ -2748,7 +2755,7 @@ static inline void tlb_read(void) " .set push \n" " .set noreorder \n" " .set noat \n" - " .set mips32r2 \n" + " .set "MIPS_ISA_LEVEL" \n" " .word 0x41610001 # dvpe $1 \n" " move %0, $1 \n" " ehb \n" @@ -2769,7 +2776,7 @@ static inline void tlb_read(void) " .set push \n" " .set noreorder \n" " .set noat \n" - " .set mips32r2 \n" + " .set "MIPS_ISA_LEVEL" \n" " .word 0x41600021 # evpe \n" " ehb \n" " .set pop \n"); diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h index a8705aef47e1..5b3d374f43e0 100644 --- a/arch/mips/include/asm/stackframe.h +++ b/arch/mips/include/asm/stackframe.h @@ -428,7 +428,7 @@ eretnc #else .set push - .set arch=r4000 + .set MIPS_ISA_ARCH_LEVEL_RAW eret .set pop #endif diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S index 921a5fa55da6..f92a4b216da8 100644 --- a/arch/mips/kernel/bmips_vec.S +++ b/arch/mips/kernel/bmips_vec.S @@ -21,7 +21,7 @@ #include .macro BARRIER - .set mips32 + .set MIPS_ISA_LEVEL_RAW _ssnop _ssnop _ssnop @@ -123,7 +123,7 @@ NESTED(bmips_reset_nmi_vec, PT_SIZE, sp) jr k0 RESTORE_ALL - .set arch=r4000 + .set MIPS_ISA_ARCH_LEVEL_RAW eret #ifdef CONFIG_SMP diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c index edc4afc080fa..906fa1a78f7f 100644 --- a/arch/mips/kernel/csrc-r4k.c +++ b/arch/mips/kernel/csrc-r4k.c @@ -35,7 +35,7 @@ static inline unsigned int rdhwr_count(void) __asm__ __volatile__( " .set push\n" - " .set mips32r2\n" + " .set "MIPS_ISA_LEVEL"\n" " rdhwr %0, $2\n" " .set pop\n" : "=r" (count)); diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index b6de8e88c1bd..2268304ae70e 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -50,7 +50,7 @@ NESTED(except_vec3_generic, 0, sp) */ NESTED(except_vec3_r4000, 0, sp) .set push - .set arch=r4000 + .set MIPS_ISA_ARCH_LEVEL_RAW .set noat mfc0 k1, CP0_CAUSE li k0, 31<<2 @@ -403,7 +403,7 @@ NESTED(ejtag_debug_handler, PT_SIZE, sp) ejtag_return: back_to_back_c0_hazard MFC0 k0, CP0_DESAVE - .set mips32 + .set MIPS_ISA_LEVEL_RAW deret .set pop END(ejtag_debug_handler) @@ -503,7 +503,7 @@ NESTED(nmi_handler, PT_SIZE, sp) * We need to specify a selector to access the CP0.Diag1 (GSCause) * register. All GSExc-equipped processors have MIPS32. */ - .set mips32 + .set MIPS_ISA_LEVEL_RAW mfc0 a1, CP0_DIAGNOSTIC1 .set pop TRACE_IRQS_ON @@ -665,7 +665,7 @@ isrdhwr: xori k1, _THREAD_MASK LONG_L v1, TI_TP_VALUE(k1) .set push - .set arch=r4000 + .set MIPS_ISA_ARCH_LEVEL_RAW eret .set pop #endif diff --git a/arch/mips/kernel/idle.c b/arch/mips/kernel/idle.c index 5abc8b7340f8..541470be5ec6 100644 --- a/arch/mips/kernel/idle.c +++ b/arch/mips/kernel/idle.c @@ -54,7 +54,7 @@ void __cpuidle r4k_wait_irqoff(void) if (!need_resched()) __asm__( " .set push \n" - " .set arch=r4000 \n" + " .set "MIPS_ISA_ARCH_LEVEL"\n" " wait \n" " .set pop \n"); } @@ -68,7 +68,7 @@ static void __cpuidle rm7k_wait_irqoff(void) if (!need_resched()) __asm__( " .set push \n" - " .set arch=r4000 \n" + " .set "MIPS_ISA_ARCH_LEVEL" \n" " .set noat \n" " mfc0 $1, $12 \n" " sync \n" @@ -89,7 +89,7 @@ static void __cpuidle au1k_wait(void) __asm__( " .set push \n" - " .set arch=r4000 \n" + " .set "MIPS_ISA_ARCH_LEVEL" \n" " cache 0x14, 0(%0) \n" " cache 0x14, 32(%0) \n" " sync \n" diff --git a/arch/mips/kernel/r4k_fpu.S b/arch/mips/kernel/r4k_fpu.S index 4e8c98517d9d..ec508ff455f2 100644 --- a/arch/mips/kernel/r4k_fpu.S +++ b/arch/mips/kernel/r4k_fpu.S @@ -107,7 +107,7 @@ LEAF(_save_fp_context) .set push .set hardfloat #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 mfc0 t0, CP0_STATUS sll t0, t0, 5 @@ -175,7 +175,7 @@ LEAF(_restore_fp_context) .set push .set hardfloat #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) - .set mips32r2 + .set MIPS_ISA_LEVEL_RAW .set fp=64 mfc0 t0, CP0_STATUS sll t0, t0, 5 diff --git a/arch/mips/kernel/syscall.c b/arch/mips/kernel/syscall.c index ae93a607ddf7..7f2be5912997 100644 --- a/arch/mips/kernel/syscall.c +++ b/arch/mips/kernel/syscall.c @@ -109,7 +109,7 @@ static inline int mips_atomic_set(unsigned long addr, unsigned long new) if (cpu_has_llsc && IS_ENABLED(CONFIG_WAR_R10000_LLSC)) { __asm__ __volatile__ ( " .set push \n" - " .set arch=r4000 \n" + " .set "MIPS_ISA_ARCH_LEVEL" \n" " li %[err], 0 \n" "1: ll %[old], (%[addr]) \n" " move %[tmp], %[new] \n" diff --git a/arch/mips/lantiq/clk.c b/arch/mips/lantiq/clk.c index 2d5a0bcb0cec..81e3329fc5de 100644 --- a/arch/mips/lantiq/clk.c +++ b/arch/mips/lantiq/clk.c @@ -177,7 +177,7 @@ static inline u32 get_counter_resolution(void) __asm__ __volatile__( ".set push\n" - ".set mips32r2\n" + ".set "MIPS_ISA_LEVEL"\n" "rdhwr %0, $3\n" ".set pop\n" : "=&r" (res) diff --git a/arch/mips/lib/csum_partial.S b/arch/mips/lib/csum_partial.S index 7767137c3e49..4b1060c3494b 100644 --- a/arch/mips/lib/csum_partial.S +++ b/arch/mips/lib/csum_partial.S @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -282,7 +283,7 @@ EXPORT_SYMBOL(csum_partial) #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ defined(CONFIG_CPU_LOONGSON64) .set push - .set arch=mips32r2 + .set MIPS_ISA_LEVEL_RAW wsbh v1, sum movn sum, v1, t7 .set pop @@ -707,7 +708,7 @@ EXPORT_SYMBOL(csum_partial) #if defined(CONFIG_CPU_MIPSR2) || defined(CONFIG_CPU_MIPSR5) || \ defined(CONFIG_CPU_LOONGSON64) .set push - .set arch=mips32r2 + .set MIPS_ISA_LEVEL_RAW wsbh v1, sum movn sum, v1, odd .set pop diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 4b6554b48923..420440cc40b1 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -918,7 +918,7 @@ static inline void rm7k_erratum31(void) __asm__ __volatile__ ( ".set push\n\t" ".set noreorder\n\t" - ".set mips3\n\t" + ".set "MIPS_ISA_LEVEL"\n\t" "cache\t%1, 0(%0)\n\t" "cache\t%1, 0x1000(%0)\n\t" "cache\t%1, 0x2000(%0)\n\t" diff --git a/arch/mips/mm/cex-oct.S b/arch/mips/mm/cex-oct.S index 9029092aa740..bb9f6b960786 100644 --- a/arch/mips/mm/cex-oct.S +++ b/arch/mips/mm/cex-oct.S @@ -19,7 +19,7 @@ LEAF(except_vec2_octeon) .set push - .set mips64r2 + .set MIPS_ISA_LEVEL_RAW .set noreorder .set noat diff --git a/arch/mips/mm/sc-ip22.c b/arch/mips/mm/sc-ip22.c index d7238687d790..9a0c29946c2d 100644 --- a/arch/mips/mm/sc-ip22.c +++ b/arch/mips/mm/sc-ip22.c @@ -33,7 +33,7 @@ static inline void indy_sc_wipe(unsigned long first, unsigned long last) __asm__ __volatile__( " .set push # indy_sc_wipe \n" " .set noreorder \n" - " .set mips3 \n" + " .set "MIPS_ISA_LEVEL" \n" " .set noat \n" " mfc0 %2, $12 \n" " li $1, 0x80 # Go 64 bit \n" @@ -108,7 +108,7 @@ static void indy_sc_enable(void) __asm__ __volatile__( ".set\tpush\n\t" ".set\tnoreorder\n\t" - ".set\tmips3\n\t" + ".set\t"MIPS_ISA_LEVEL"\n\t" "mfc0\t%2, $12\n\t" "nop; nop; nop; nop;\n\t" "li\t%1, 0x80\n\t" @@ -138,7 +138,7 @@ static void indy_sc_disable(void) __asm__ __volatile__( ".set\tpush\n\t" ".set\tnoreorder\n\t" - ".set\tmips3\n\t" + ".set\t"MIPS_ISA_LEVEL"\n\t" "li\t%0, 0x1\n\t" "dsll\t%0, 31\n\t" "lui\t%1, 0x9000\n\t" From patchwork Sun Apr 9 10:43:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13205920 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 504A3C77B73 for ; Sun, 9 Apr 2023 10:43:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229462AbjDIKn0 (ORCPT ); Sun, 9 Apr 2023 06:43:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47220 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229502AbjDIKnZ (ORCPT ); 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Sun, 9 Apr 2023 06:43:21 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 2/8] MIPS: Set ISA level for MSA control reg helpers Date: Sun, 9 Apr 2023 11:43:03 +0100 Message-Id: <20230409104309.13887-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230409104309.13887-1-jiaxun.yang@flygoat.com> References: <20230409104309.13887-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org MSA instructions requires at least Release 2 to be available. Setting ISA level here to make GAS happy when building kernel for earlier CPUs. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/msa.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/mips/include/asm/msa.h b/arch/mips/include/asm/msa.h index a9ca57e3f780..e13e538a7889 100644 --- a/arch/mips/include/asm/msa.h +++ b/arch/mips/include/asm/msa.h @@ -175,10 +175,12 @@ static inline void init_msa_upper(void) #define _ASM_UNSET_CTCMSA ".purgem ctcmsa\n\t" #else /* CONFIG_AS_HAS_MSA */ #define _ASM_SET_CFCMSA \ + ".set\t"MIPS_ISA_LEVEL"\n\t" \ ".set\tfp=64\n\t" \ ".set\tmsa\n\t" #define _ASM_UNSET_CFCMSA #define _ASM_SET_CTCMSA \ + ".set\t"MIPS_ISA_LEVEL"\n\t" \ ".set\tfp=64\n\t" \ ".set\tmsa\n\t" #define _ASM_UNSET_CTCMSA From patchwork Sun Apr 9 10:43:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13205921 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40144C77B70 for ; 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Sun, 9 Apr 2023 06:43:24 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 3/8] MIPS: loongson2ef: Add missing break in cs5536_isa Date: Sun, 9 Apr 2023 11:43:04 +0100 Message-Id: <20230409104309.13887-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230409104309.13887-1-jiaxun.yang@flygoat.com> References: <20230409104309.13887-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Fixes build error: arch/mips/loongson2ef/common/cs5536/cs5536_isa.c:217:2: error: unannotated fall-through between switch labels [-Werror,-Wimplicit-fallthrough] default: ^ arch/mips/loongson2ef/common/cs5536/cs5536_isa.c:217:2: note: insert 'break;' to avoid fall-through default: ^ break; Signed-off-by: Jiaxun Yang --- arch/mips/loongson2ef/common/cs5536/cs5536_isa.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c b/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c index 5ad38f86ee62..d60dd9992377 100644 --- a/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c +++ b/arch/mips/loongson2ef/common/cs5536/cs5536_isa.c @@ -213,7 +213,7 @@ void pci_isa_write_reg(int reg, u32 value) lo |= 0x00000063; _wrmsr(SB_MSR_REG(SB_ERROR), hi, lo); } - + break; default: /* ALL OTHER PCI CONFIG SPACE HEADER IS NOT IMPLEMENTED. */ break; From patchwork Sun Apr 9 10:43:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13205922 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A575C77B70 for ; Sun, 9 Apr 2023 10:43:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229524AbjDIKna (ORCPT ); Sun, 9 Apr 2023 06:43:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229502AbjDIKn3 (ORCPT ); Sun, 9 Apr 2023 06:43:29 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33A51469B for ; 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Sun, 9 Apr 2023 06:43:26 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 4/8] MIPS: asmmacro: Restore fp macro after undef Date: Sun, 9 Apr 2023 11:43:05 +0100 Message-Id: <20230409104309.13887-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230409104309.13887-1-jiaxun.yang@flygoat.com> References: <20230409104309.13887-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org fp macro is used by several place to reference frame pointer. Restore macro at end of file with {push,pop}_macro pragma to avoid break other assembly files. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/asmmacro.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index 2491a6c68390..de9688911cae 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -20,6 +20,7 @@ #endif /* preprocessor replaces the fp in ".set fp=64" with $30 otherwise */ +#pragma push_macro("fp") #undef fp /* @@ -655,4 +656,6 @@ .set pop .endm +#pragma pop_macro("fp") + #endif /* _ASM_ASMMACRO_H */ From patchwork Sun Apr 9 10:43:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13205923 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D69EBC77B71 for ; Sun, 9 Apr 2023 10:43:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229502AbjDIKnd (ORCPT ); Sun, 9 Apr 2023 06:43:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229458AbjDIKnc (ORCPT ); Sun, 9 Apr 2023 06:43:32 -0400 Received: from wout4-smtp.messagingengine.com (wout4-smtp.messagingengine.com [64.147.123.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B2C746BF for ; Sun, 9 Apr 2023 03:43:31 -0700 (PDT) Received: from compute5.internal (compute5.nyi.internal [10.202.2.45]) by mailout.west.internal (Postfix) with ESMTP id AF47732004ED; Sun, 9 Apr 2023 06:43:30 -0400 (EDT) Received: from mailfrontend1 ([10.202.2.162]) by compute5.internal (MEProxy); Sun, 09 Apr 2023 06:43:31 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=flygoat.com; h= cc:cc:content-transfer-encoding:content-type:date:date:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to; s=fm3; t=1681037010; x= 1681123410; bh=GICeuC5Na6dEOkT9RFxmFTSwUiB6wXXr5dWatVKt1SI=; b=h br0bEp5gHuzlgLbCg4djDpSISTNjkyhcxX2+dZ2xm34muiZdLJEz7RrIf4Yz/t+1 yWtXWTx6ilIf4sOsXKIVzzjxB4Gk5A6KNbxv22WAj1tKRKYsocvnYLTVyP+BPccd RnXy3kbk7Zb/YErIikN8asz6auUOwuH2aJdShelMPk8sOaDu3rnYorp/XFtLn7HM j2+LiJFYTOuxrNk5gVRFKXhYOQktnkj6nU2EsdaIqKSoxo/NjTFpzy2t5IjS04rf gF6tNI/GfNFQxVgUIaxl62PZQaB9o/o9PP6/rR0GBXqiLuwjdG7xgvm3kx2aNtb1 vAsDp9Ph7wohMAe354gVA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-transfer-encoding :content-type:date:date:feedback-id:feedback-id:from:from :in-reply-to:in-reply-to:message-id:mime-version:references :reply-to:sender:subject:subject:to:to:x-me-proxy:x-me-proxy :x-me-sender:x-me-sender:x-sasl-enc; s=fm2; t=1681037010; x= 1681123410; bh=GICeuC5Na6dEOkT9RFxmFTSwUiB6wXXr5dWatVKt1SI=; b=m 5wA77IC1LBNrO3z3FmlKzyw1EkseskgKySrLlYrlE326Q7eoZq/4buVPyMx4RSG/ 1R7lMMohuR7m4kUtJwuU1UxR2+D9ksiXqhoKqR6VzRmJ3eE4I36Aparbl/LbaQSW JS8Mhh+G1LoS713TG/1sOKUbR0afcPi/d5xffZxPADgEHW/7YkbLxVbDQzVpAZhJ CGveBOhASSmJpUTBRV9I3FjULk5pNWsbgoPZeG/COB2Zc/2jpjanIFbnMj0EqzpD zagRwZGMOVkLCAt3PD2L1JrgN4tcRABeYpr893auYAwK8hsgRUx9oehblqGtVNRe H2FZ84YEzMnamhuzVooZQ== X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvhedrvdektddgfedvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucenucfjughrpefhvfevufffkffojghfggfgsedtke ertdertddtnecuhfhrohhmpeflihgrgihunhcujggrnhhguceojhhirgiguhhnrdihrghn ghesfhhlhihgohgrthdrtghomheqnecuggftrfgrthhtvghrnhepfeeludefheegvdeuvd dvgeekgfdvtdettdelieeihfegtedugeekhfdvhfejfedtnecuvehluhhsthgvrhfuihii vgeptdenucfrrghrrghmpehmrghilhhfrhhomhepjhhirgiguhhnrdihrghnghesfhhlhi hgohgrthdrtghomh X-ME-Proxy: Feedback-ID: ifd894703:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sun, 9 Apr 2023 06:43:29 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 5/8] MIPS: mipsregs: Parse fp and sp register by name in parse_r Date: Sun, 9 Apr 2023 11:43:06 +0100 Message-Id: <20230409104309.13887-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230409104309.13887-1-jiaxun.yang@flygoat.com> References: <20230409104309.13887-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org parse_r helper is used to parse register number from oprand, it only handles oprand which use number to refer register before. However compiler may use $gp and $sp to reference register 29 and 30. Handle this situation by adding relevant match name. Fixes compilation error: {standard input}: Assembler messages: {standard input}:1937: Error: Unable to parse register name $fp Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mipsregs.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 9d928b952abf..7d2c1c90fa10 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1277,11 +1277,13 @@ static inline int mm_insn_16bit(u16 insn) */ /* Match an individual register number and assign to \var */ -#define _IFC_REG(n) \ - ".ifc \\r, $" #n "\n\t" \ +#define _IFC_REG_NAME(name, n) \ + ".ifc \\r, $" #name "\n\t" \ "\\var = " #n "\n\t" \ ".endif\n\t" +#define _IFC_REG(n) _IFC_REG_NAME(n, n) + #define _ASM_SET_PARSE_R \ ".macro parse_r var r\n\t" \ "\\var = -1\n\t" \ @@ -1293,6 +1295,7 @@ static inline int mm_insn_16bit(u16 insn) _IFC_REG(20) _IFC_REG(21) _IFC_REG(22) _IFC_REG(23) \ _IFC_REG(24) _IFC_REG(25) _IFC_REG(26) _IFC_REG(27) \ _IFC_REG(28) _IFC_REG(29) _IFC_REG(30) _IFC_REG(31) \ + _IFC_REG_NAME(sp, 29) _IFC_REG_NAME(fp, 30) \ ".iflt \\var\n\t" \ ".error \"Unable to parse register name \\r\"\n\t" \ ".endif\n\t" \ From patchwork Sun Apr 9 10:43:07 2023 Content-Type: text/plain; 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Sun, 9 Apr 2023 06:43:31 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 6/8] MIPS: c-r4k: Use cache_op function for rm7k_erratum31 Date: Sun, 9 Apr 2023 11:43:07 +0100 Message-Id: <20230409104309.13887-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230409104309.13887-1-jiaxun.yang@flygoat.com> References: <20230409104309.13887-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org LLVM assembler is not happy with offset that may overflow immediate field. Use cache_op function instead of inline assembly to fix build error: arch/mips/mm/c-r4k.c:922:23: error: instruction requires a CPU feature not currently enabled "cache\t%1, 0(%0)\n\t" Signed-off-by: Jiaxun Yang --- arch/mips/mm/c-r4k.c | 33 ++++++++++++++------------------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 420440cc40b1..89603d033180 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -915,25 +915,20 @@ static inline void rm7k_erratum31(void) write_c0_taghi(0); for (addr = INDEX_BASE; addr <= INDEX_BASE + 4096; addr += ic_lsize) { - __asm__ __volatile__ ( - ".set push\n\t" - ".set noreorder\n\t" - ".set "MIPS_ISA_LEVEL"\n\t" - "cache\t%1, 0(%0)\n\t" - "cache\t%1, 0x1000(%0)\n\t" - "cache\t%1, 0x2000(%0)\n\t" - "cache\t%1, 0x3000(%0)\n\t" - "cache\t%2, 0(%0)\n\t" - "cache\t%2, 0x1000(%0)\n\t" - "cache\t%2, 0x2000(%0)\n\t" - "cache\t%2, 0x3000(%0)\n\t" - "cache\t%1, 0(%0)\n\t" - "cache\t%1, 0x1000(%0)\n\t" - "cache\t%1, 0x2000(%0)\n\t" - "cache\t%1, 0x3000(%0)\n\t" - ".set pop\n" - : - : "r" (addr), "i" (Index_Store_Tag_I), "i" (Fill_I)); + cache_op(Index_Store_Tag_I, addr); + cache_op(Index_Store_Tag_I, addr + 0x1000); + cache_op(Index_Store_Tag_I, addr + 0x2000); + cache_op(Index_Store_Tag_I, addr + 0x3000); + + cache_op(Fill_I, addr); + cache_op(Fill_I, addr + 0x1000); + cache_op(Fill_I, addr + 0x2000); + cache_op(Fill_I, addr + 0x3000); + + cache_op(Index_Store_Tag_I, addr); + cache_op(Index_Store_Tag_I, addr + 0x1000); + cache_op(Index_Store_Tag_I, addr + 0x2000); + cache_op(Index_Store_Tag_I, addr + 0x3000); } } From patchwork Sun Apr 9 10:43:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 13205925 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BDFE4C77B61 for ; Sun, 9 Apr 2023 10:43:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229458AbjDIKni (ORCPT ); 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Sun, 9 Apr 2023 06:43:33 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 7/8] MIPS: octeon_switch: Remove duplicated labels Date: Sun, 9 Apr 2023 11:43:08 +0100 Message-Id: <20230409104309.13887-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230409104309.13887-1-jiaxun.yang@flygoat.com> References: <20230409104309.13887-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org EXPORT macro already have labels defined by itself. Remove duplicated labels outside to silent assembler warnings. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/octeon_switch.S | 6 ------ 1 file changed, 6 deletions(-) diff --git a/arch/mips/kernel/octeon_switch.S b/arch/mips/kernel/octeon_switch.S index 896080b445c2..9b7c8ab6f08c 100644 --- a/arch/mips/kernel/octeon_switch.S +++ b/arch/mips/kernel/octeon_switch.S @@ -428,7 +428,6 @@ done_restore: jr ra nop .space 30 * 4, 0 -octeon_mult_save_end: EXPORT(octeon_mult_save_end) END(octeon_mult_save) @@ -448,7 +447,6 @@ octeon_mult_save_end: sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */ jr ra sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */ -octeon_mult_save2_end: EXPORT(octeon_mult_save2_end) END(octeon_mult_save2) @@ -480,7 +478,6 @@ octeon_mult_save2_end: sd $10, PT_MPL+(4*8)(sp) /* store MPL4 */ jr ra sd $11, PT_MPL+(5*8)(sp) /* store MPL5 */ -octeon_mult_save3_end: EXPORT(octeon_mult_save3_end) END(octeon_mult_save3) .set pop @@ -498,7 +495,6 @@ octeon_mult_save3_end: jr ra nop .space 30 * 4, 0 -octeon_mult_restore_end: EXPORT(octeon_mult_restore_end) END(octeon_mult_restore) @@ -517,7 +513,6 @@ octeon_mult_restore_end: mtp1 v0 /* P1 */ jr ra mtp0 v1 /* P0 */ -octeon_mult_restore2_end: EXPORT(octeon_mult_restore2_end) END(octeon_mult_restore2) @@ -548,7 +543,6 @@ octeon_mult_restore2_end: .word 0x714b000b /* mtp2 $10, $11 restore P2 and P5 */ -octeon_mult_restore3_end: EXPORT(octeon_mult_restore3_end) END(octeon_mult_restore3) .set pop From patchwork Sun Apr 9 10:43:09 2023 Content-Type: text/plain; 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Sun, 9 Apr 2023 06:43:35 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: llvm@lists.linux.dev, tsbogend@alpha.franken.de, ndesaulniers@google.com, nathan@kernel.org, Jiaxun Yang Subject: [PATCH 8/8] MIPS: Implement microMIPS MT ASE helpers Date: Sun, 9 Apr 2023 11:43:09 +0100 Message-Id: <20230409104309.13887-9-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.39.2 (Apple Git-143) In-Reply-To: <20230409104309.13887-1-jiaxun.yang@flygoat.com> References: <20230409104309.13887-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org Implement various microMIPS MT ASE helpers accroading to: MIPS® Architecture for Programmers Volume IV-f: The MIPS® MT Module for the microMIPS32™ Architecture Fixes build error: {standard input}:2616: Error: branch to a symbol in another ISA mode Boot tested on M5150 with microMIPS enabled on M5150. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/asmmacro.h | 22 ++- arch/mips/include/asm/mipsmtregs.h | 256 +++++++++++++++++------------ arch/mips/include/asm/mipsregs.h | 9 + 3 files changed, 177 insertions(+), 110 deletions(-) diff --git a/arch/mips/include/asm/asmmacro.h b/arch/mips/include/asm/asmmacro.h index de9688911cae..e56bdda483f5 100644 --- a/arch/mips/include/asm/asmmacro.h +++ b/arch/mips/include/asm/asmmacro.h @@ -217,27 +217,33 @@ * Temporary until all gas have MT ASE support */ .macro DMT reg=0 - .word 0x41600bc1 | (\reg << 16) + insn_if_mips 0x41600bc1 | (\reg << 16) + insn32_if_mm 0x0000057C | (\reg << 21) .endm .macro EMT reg=0 - .word 0x41600be1 | (\reg << 16) + insn_if_mips 0x41600be1 | (\reg << 16) + insn32_if_mm 0x0000257C | (\reg << 21) .endm .macro DVPE reg=0 - .word 0x41600001 | (\reg << 16) + insn_if_mips 0x41600001 | (\reg << 16) + insn32_if_mm 0x0000157C | (\reg << 21) .endm .macro EVPE reg=0 - .word 0x41600021 | (\reg << 16) + insn_if_mips 0x41600021 | (\reg << 16) + insn32_if_mm 0x0000357C | (\reg << 21) .endm - .macro MFTR rt=0, rd=0, u=0, sel=0 - .word 0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) + .macro MFTR rs=0, rt=0, u=0, sel=0 + insn_if_mips 0x41000000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel) + insn32_if_mm 0x0000000E | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4) .endm - .macro MTTR rt=0, rd=0, u=0, sel=0 - .word 0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel) + .macro MTTR rt=0, rs=0, u=0, sel=0 + insn_if_mips 0x41800000 | (\rt << 16) | (\rs << 11) | (\u << 5) | (\sel) + insn32_if_mm 0x00000006 | (\rt << 21) | (\rs << 16) | (\u << 10) | (\sel << 4) .endm #ifdef CONFIG_AS_HAS_MSA diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h index b6dea86b1b82..30e86861c206 100644 --- a/arch/mips/include/asm/mipsmtregs.h +++ b/arch/mips/include/asm/mipsmtregs.h @@ -189,19 +189,24 @@ static inline unsigned core_nvpes(void) return ((conf0 & MVPCONF0_PVPE) >> MVPCONF0_PVPE_SHIFT) + 1; } +#define _ASM_SET_DVPE \ + _ASM_MACRO_1R(dvpe, rt, \ + _ASM_INSN_IF_MIPS(0x41600001 | __rt << 16) \ + _ASM_INSN32_IF_MM(0x0000157C | __rt << 21)) +#define _ASM_UNSET_DVPE ".purgem dvpe\n\t" + static inline unsigned int dvpe(void) { int res = 0; __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set "MIPS_ISA_LEVEL" \n" - " .word 0x41610001 # dvpe $1 \n" - " move %0, $1 \n" - " ehb \n" - " .set pop \n" + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + _ASM_SET_DVPE + " dvpe %0 \n" + " ehb \n" + _ASM_UNSET_DVPE + " .set pop \n" : "=r" (res)); instruction_hazard(); @@ -209,16 +214,22 @@ static inline unsigned int dvpe(void) return res; } +#define _ASM_SET_EVPE \ + _ASM_MACRO_1R(evpe, rt, \ + _ASM_INSN_IF_MIPS(0x41600021 | __rt << 16) \ + _ASM_INSN32_IF_MM(0x0000357C | __rt << 21)) +#define _ASM_UNSET_EVPE ".purgem evpe\n\t" + static inline void __raw_evpe(void) { __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set noat \n" - " .set "MIPS_ISA_LEVEL" \n" - " .word 0x41600021 # evpe \n" - " ehb \n" - " .set pop \n"); + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + _ASM_SET_EVPE + " evpe $0 \n" + " ehb \n" + _ASM_UNSET_EVPE + " .set pop \n"); } /* Enable virtual processor execution if previous suggested it should be. @@ -232,18 +243,24 @@ static inline void evpe(int previous) __raw_evpe(); } +#define _ASM_SET_DMT \ + _ASM_MACRO_1R(dmt, rt, \ + _ASM_INSN_IF_MIPS(0x41600bc1 | __rt << 16) \ + _ASM_INSN32_IF_MM(0x0000057C | __rt << 21)) +#define _ASM_UNSET_DMT ".purgem dmt\n\t" + static inline unsigned int dmt(void) { int res; __asm__ __volatile__( - " .set push \n" - " .set "MIPS_ISA_LEVEL" \n" - " .set noat \n" - " .word 0x41610BC1 # dmt $1 \n" - " ehb \n" - " move %0, $1 \n" - " .set pop \n" + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + _ASM_SET_DMT + " dmt %0 \n" + " ehb \n" + _ASM_UNSET_DMT + " .set pop \n" : "=r" (res)); instruction_hazard(); @@ -251,14 +268,21 @@ static inline unsigned int dmt(void) return res; } +#define _ASM_SET_EMT \ + _ASM_MACRO_1R(emt, rt, \ + _ASM_INSN_IF_MIPS(0x41600be1 | __rt << 16) \ + _ASM_INSN32_IF_MM(0x0000257C | __rt << 21)) +#define _ASM_UNSET_EMT ".purgem emt\n\t" + static inline void __raw_emt(void) { __asm__ __volatile__( - " .set push \n" - " .set noreorder \n" - " .set "MIPS_ISA_LEVEL" \n" - " .word 0x41600be1 # emt \n" - " ehb \n" + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + _ASM_SET_EMT + " emt $0 \n" + _ASM_UNSET_EMT + " ehb \n" " .set pop"); } @@ -276,41 +300,55 @@ static inline void emt(int previous) static inline void ehb(void) { __asm__ __volatile__( - " .set push \n" - " .set "MIPS_ISA_LEVEL" \n" - " ehb \n" - " .set pop \n"); + " .set push \n" + " .set "MIPS_ISA_LEVEL" \n" + " ehb \n" + " .set pop \n"); } -#define mftc0(rt,sel) \ +#define _ASM_SET_MFTC0 \ + _ASM_MACRO_2R_1S(mftc0, rs, rt, sel, \ + _ASM_INSN_IF_MIPS(0x41000000 | __rt << 16 | \ + __rs << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x0000000E | __rt << 21 | \ + __rs << 16 | \\sel << 4)) +#define _ASM_UNSET_MFTC0 ".purgem mftc0\n\t" + +#define mftc0(rt, sel) \ ({ \ - unsigned long __res; \ + unsigned long __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set "MIPS_ISA_LEVEL" \n" \ - " .set noat \n" \ - " # mftc0 $1, $" #rt ", " #sel " \n" \ - " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ + _ASM_SET_MFTC0 \ + " mftc0 $1, " #rt ", " #sel " \n" \ + _ASM_UNSET_MFTC0 \ + " .set pop \n" \ : "=r" (__res)); \ \ __res; \ }) +#define _ASM_SET_MFTGPR \ + _ASM_MACRO_2R(mftgpr, rs, rt, \ + _ASM_INSN_IF_MIPS(0x41000020 | __rt << 16 | \ + __rs << 11) \ + _ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \ + __rs << 16)) +#define _ASM_UNSET_MFTGPR ".purgem mftgpr\n\t" + #define mftgpr(rt) \ ({ \ unsigned long __res; \ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set noat \n" \ - " .set "MIPS_ISA_LEVEL" \n" \ - " # mftgpr $1," #rt " \n" \ - " .word 0x41000820 | (" #rt " << 16) \n" \ - " move %0, $1 \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ + _ASM_SET_MFTGPR \ + " mftgpr %0," #rt " \n" \ + _ASM_UNSET_MFTGPR \ + " .set pop \n" \ : "=r" (__res)); \ \ __res; \ @@ -321,35 +359,49 @@ static inline void ehb(void) unsigned long __res; \ \ __asm__ __volatile__( \ - " mftr %0, " #rt ", " #u ", " #sel " \n" \ + " mftr %0, " #rt ", " #u ", " #sel " \n" \ : "=r" (__res)); \ \ __res; \ }) -#define mttgpr(rd,v) \ +#define _ASM_SET_MTTGPR \ + _ASM_MACRO_2R(mttgpr, rt, rs, \ + _ASM_INSN_IF_MIPS(0x41800020 | __rt << 16 | \ + __rs << 11) \ + _ASM_INSN32_IF_MM(0x00000406 | __rt << 21 | \ + __rs << 16)) +#define _ASM_UNSET_MTTGPR ".purgem mttgpr\n\t" + +#define mttgpr(rs, v) \ do { \ __asm__ __volatile__( \ - " .set push \n" \ - " .set "MIPS_ISA_LEVEL" \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mttgpr $1, " #rd " \n" \ - " .word 0x41810020 | (" #rd " << 11) \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ + _ASM_SET_MTTGPR \ + " mttgpr %0, " #rs " \n" \ + _ASM_UNSET_MTTGPR \ + " .set pop \n" \ : : "r" (v)); \ } while (0) -#define mttc0(rd, sel, v) \ +#define _ASM_SET_MTTC0 \ + _ASM_MACRO_2R_1S(mttc0, rt, rs, sel, \ + _ASM_INSN_IF_MIPS(0x41800000 | __rt << 16 | \ + __rs << 11 | \\sel) \ + _ASM_INSN32_IF_MM(0x0000040E | __rt << 21 | \ + __rs << 16 | \\sel << 4)) +#define _ASM_UNSET_MTTC0 ".purgem mttc0\n\t" + +#define mttc0(rs, sel, v) \ ({ \ __asm__ __volatile__( \ - " .set push \n" \ - " .set "MIPS_ISA_LEVEL" \n" \ - " .set noat \n" \ - " move $1, %0 \n" \ - " # mttc0 %0," #rd ", " #sel " \n" \ - " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \ - " .set pop \n" \ + " .set push \n" \ + " .set "MIPS_ISA_LEVEL" \n" \ + _ASM_SET_MTTC0 \ + " mttc0 %0," #rs ", " #sel " \n" \ + _ASM_UNSET_MTTC0 \ + " .set pop \n" \ : \ : "r" (v)); \ }) @@ -371,49 +423,49 @@ do { \ /* you *must* set the target tc (settc) before trying to use these */ -#define read_vpe_c0_vpecontrol() mftc0(1, 1) -#define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) -#define read_vpe_c0_vpeconf0() mftc0(1, 2) -#define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) -#define read_vpe_c0_vpeconf1() mftc0(1, 3) -#define write_vpe_c0_vpeconf1(val) mttc0(1, 3, val) -#define read_vpe_c0_count() mftc0(9, 0) -#define write_vpe_c0_count(val) mttc0(9, 0, val) -#define read_vpe_c0_status() mftc0(12, 0) -#define write_vpe_c0_status(val) mttc0(12, 0, val) -#define read_vpe_c0_cause() mftc0(13, 0) -#define write_vpe_c0_cause(val) mttc0(13, 0, val) -#define read_vpe_c0_config() mftc0(16, 0) -#define write_vpe_c0_config(val) mttc0(16, 0, val) -#define read_vpe_c0_config1() mftc0(16, 1) -#define write_vpe_c0_config1(val) mttc0(16, 1, val) -#define read_vpe_c0_config7() mftc0(16, 7) -#define write_vpe_c0_config7(val) mttc0(16, 7, val) -#define read_vpe_c0_ebase() mftc0(15, 1) -#define write_vpe_c0_ebase(val) mttc0(15, 1, val) -#define write_vpe_c0_compare(val) mttc0(11, 0, val) -#define read_vpe_c0_badvaddr() mftc0(8, 0) -#define read_vpe_c0_epc() mftc0(14, 0) -#define write_vpe_c0_epc(val) mttc0(14, 0, val) +#define read_vpe_c0_vpecontrol() mftc0($1, 1) +#define write_vpe_c0_vpecontrol(val) mttc0($1, 1, val) +#define read_vpe_c0_vpeconf0() mftc0($1, 2) +#define write_vpe_c0_vpeconf0(val) mttc0($1, 2, val) +#define read_vpe_c0_vpeconf1() mftc0($1, 3) +#define write_vpe_c0_vpeconf1(val) mttc0($1, 3, val) +#define read_vpe_c0_count() mftc0($9, 0) +#define write_vpe_c0_count(val) mttc0($9, 0, val) +#define read_vpe_c0_status() mftc0($12, 0) +#define write_vpe_c0_status(val) mttc0($12, 0, val) +#define read_vpe_c0_cause() mftc0($13, 0) +#define write_vpe_c0_cause(val) mttc0($13, 0, val) +#define read_vpe_c0_config() mftc0($16, 0) +#define write_vpe_c0_config(val) mttc0($16, 0, val) +#define read_vpe_c0_config1() mftc0($16, 1) +#define write_vpe_c0_config1(val) mttc0($16, 1, val) +#define read_vpe_c0_config7() mftc0($16, 7) +#define write_vpe_c0_config7(val) mttc0($16, 7, val) +#define read_vpe_c0_ebase() mftc0($15, 1) +#define write_vpe_c0_ebase(val) mttc0($15, 1, val) +#define write_vpe_c0_compare(val) mttc0($11, 0, val) +#define read_vpe_c0_badvaddr() mftc0($8, 0) +#define read_vpe_c0_epc() mftc0($14, 0) +#define write_vpe_c0_epc(val) mttc0($14, 0, val) /* TC */ -#define read_tc_c0_tcstatus() mftc0(2, 1) -#define write_tc_c0_tcstatus(val) mttc0(2, 1, val) -#define read_tc_c0_tcbind() mftc0(2, 2) -#define write_tc_c0_tcbind(val) mttc0(2, 2, val) -#define read_tc_c0_tcrestart() mftc0(2, 3) -#define write_tc_c0_tcrestart(val) mttc0(2, 3, val) -#define read_tc_c0_tchalt() mftc0(2, 4) -#define write_tc_c0_tchalt(val) mttc0(2, 4, val) -#define read_tc_c0_tccontext() mftc0(2, 5) -#define write_tc_c0_tccontext(val) mttc0(2, 5, val) +#define read_tc_c0_tcstatus() mftc0($2, 1) +#define write_tc_c0_tcstatus(val) mttc0($2, 1, val) +#define read_tc_c0_tcbind() mftc0($2, 2) +#define write_tc_c0_tcbind(val) mttc0($2, 2, val) +#define read_tc_c0_tcrestart() mftc0($2, 3) +#define write_tc_c0_tcrestart(val) mttc0($2, 3, val) +#define read_tc_c0_tchalt() mftc0($2, 4) +#define write_tc_c0_tchalt(val) mttc0($2, 4, val) +#define read_tc_c0_tccontext() mftc0($2, 5) +#define write_tc_c0_tccontext(val) mttc0($2, 5, val) /* GPR */ -#define read_tc_gpr_sp() mftgpr(29) -#define write_tc_gpr_sp(val) mttgpr(29, val) -#define read_tc_gpr_gp() mftgpr(28) -#define write_tc_gpr_gp(val) mttgpr(28, val) +#define read_tc_gpr_sp() mftgpr($29) +#define write_tc_gpr_sp(val) mttgpr($29, val) +#define read_tc_gpr_gp() mftgpr($28) +#define write_tc_gpr_gp(val) mttgpr($28, val) __BUILD_SET_C0(mvpcontrol) diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h index 7d2c1c90fa10..b30d5e1672c4 100644 --- a/arch/mips/include/asm/mipsregs.h +++ b/arch/mips/include/asm/mipsregs.h @@ -1310,6 +1310,15 @@ static inline int mm_insn_16bit(u16 insn) * the ENC encodings. */ +/* Instructions with 1 register operand */ +#define _ASM_MACRO_1R(OP, R1, ENC) \ + ".macro " #OP " " #R1 "\n\t" \ + _ASM_SET_PARSE_R \ + "parse_r __" #R1 ", \\" #R1 "\n\t" \ + ENC \ + _ASM_UNSET_PARSE_R \ + ".endm\n\t" + /* Instructions with 1 register operand & 1 immediate operand */ #define _ASM_MACRO_1R1I(OP, R1, I2, ENC) \ ".macro " #OP " " #R1 ", " #I2 "\n\t" \