From patchwork Mon Apr 10 10:50:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206268 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 223B0C76196 for ; Mon, 10 Apr 2023 10:51:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229684AbjDJKvV (ORCPT ); Mon, 10 Apr 2023 06:51:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229678AbjDJKvU (ORCPT ); Mon, 10 Apr 2023 06:51:20 -0400 Received: from mail-pf1-x432.google.com (mail-pf1-x432.google.com [IPv6:2607:f8b0:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6E9663581; Mon, 10 Apr 2023 03:51:19 -0700 (PDT) Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-634b28df952so422918b3a.2; Mon, 10 Apr 2023 03:51:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681123879; x=1683715879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AS0Uc7+GRHk2JAOMs6kTtR/AvHmqVodtFBcgwhyXJLQ=; b=RURMy3bjBcxyE2TmYmZ5bRcBHne+dHqOxQTKUR1E19Cpgp1TLjrlTGF0hBxgV+Q1JU V/V9RIo35bvieRPNjTgT/q780TYHA59+nD+8RujekbGqJQ7NWpcMCZ9Uql7hjiW5Dr1x ALtP2Hm6ic9Solciaee0S0EVyENMLbvuqHBoRlOQuGzw7KWJCp6MFlr1ZFcfqM6T3+P3 qeyeuV32TCjZWc+S9OT6mOlDMq7UXAPj957EQkQsC/+IaKy7fjWdgelN/BUoMql6D+yd Bu3zQpRHL2xatzOTf5cpRMzLmuiTrJfeWRIC8rNNC0EGGSiMrN8Lp8h8ciQGhtkXqGNS UzNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681123879; x=1683715879; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AS0Uc7+GRHk2JAOMs6kTtR/AvHmqVodtFBcgwhyXJLQ=; b=Ciovr9WG/wgqOFKMhkg6WMLx9mBOsliOEptGrG5iSi0WTubuj4vKxCSaEWuT5+h8q0 Uv+J8SW3H7pKB68B2TBZNOISeDA4RzGyOnWH8Qy6ReJe+ZcLBalOwg10n3KAOQqcSt+V dbOLIkEBk/bjkSuKmcFDi42EaVVVaVl62U3mm3a+DWpq+0Es8/89FxzOgvl2gnx0/AJE 4eg3M/jjH1XqBhWthgtQj0cJlpyEzHPKG/WXII1r4frzSPaoTsm9YZ8z19ABhXis5K3h dIvVenFj64Fm9PFMVQlC/3uB3SzAdCPMBu1t7BDCu8DKGMVSPOFPBIg5od23cTpLf7qE 8H4g== X-Gm-Message-State: AAQBX9c+2kP7Mq2n45YFW/HdOaCs2dTNAlCknEylvkGq73Ynmt4CAWdp K9x9aT86WLc9mHA9WKJGDWsX0E+LnmvoTw== X-Google-Smtp-Source: AKy350bfCmd8FxzV7MO7p5Q79iCjrX6Z3ftpMmg6ChociNbnfVy7tFPfE5yqHrmTCLVgSU4kMAW5UQ== X-Received: by 2002:aa7:9697:0:b0:5a0:c4b6:edd6 with SMTP id f23-20020aa79697000000b005a0c4b6edd6mr11197859pfk.0.1681123878752; Mon, 10 Apr 2023 03:51:18 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h4-20020a056a00170400b0062e032b61a6sm7783252pfc.91.2023.04.10.03.51.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 03:51:18 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 01/10] KVM: x86/pmu: Expose reprogram_counters() in pmu.h Date: Mon, 10 Apr 2023 18:50:47 +0800 Message-Id: <20230410105056.60973-2-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu The optimization stands on its own, whereas the code movement is justified only by the incoming AMD PMU v2 support. No functional change intended. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/pmu.h | 12 ++++++++++++ arch/x86/kvm/vmx/pmu_intel.c | 12 ------------ 2 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 5c7bbf03b599..986563aeeef8 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -201,6 +201,18 @@ static inline void kvm_pmu_request_counter_reprogram(struct kvm_pmc *pmc) kvm_make_request(KVM_REQ_PMU, pmc->vcpu); } +static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff) +{ + int bit; + + if (!diff) + return; + + for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) + set_bit(bit, pmu->reprogram_pmi); + kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 741efe2c497b..1f9c3e916a21 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -73,18 +73,6 @@ static struct kvm_pmc *intel_pmc_idx_to_pmc(struct kvm_pmu *pmu, int pmc_idx) } } -static void reprogram_counters(struct kvm_pmu *pmu, u64 diff) -{ - int bit; - - if (!diff) - return; - - for_each_set_bit(bit, (unsigned long *)&diff, X86_PMC_IDX_MAX) - set_bit(bit, pmu->reprogram_pmi); - kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); -} - static bool intel_hw_event_available(struct kvm_pmc *pmc) { struct kvm_pmu *pmu = pmc_to_pmu(pmc); From patchwork Mon Apr 10 10:50:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206269 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F1977C77B61 for ; Mon, 10 Apr 2023 10:51:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229699AbjDJKvZ (ORCPT ); Mon, 10 Apr 2023 06:51:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40558 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229682AbjDJKvV (ORCPT ); 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Mon, 10 Apr 2023 03:51:20 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 02/10] KVM: x86/pmu: Return #GP if user sets the GLOBAL_STATUS reserved bits Date: Mon, 10 Apr 2023 18:50:48 +0800 Message-Id: <20230410105056.60973-3-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Return #GP if KVM user space attempts to set a reserved bit for guest. If the user space sets reserved bits when restoring the MSR_CORE_ PERF_GLOBAL_STATUS register, these bits will be accidentally returned when the guest runs a read access to this register, and cannot be cleared up inside the guest, which makes the guest's PMI handler very confused. Note, reusing global_ovf_ctrl_mask as global_status_mask will be broken if KVM supports higher versions of Intel arch pmu. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/pmu_intel.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 1f9c3e916a21..343b3182b7f4 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -399,7 +399,11 @@ static int intel_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) reprogram_fixed_counters(pmu, data); break; case MSR_CORE_PERF_GLOBAL_STATUS: - if (!msr_info->host_initiated) + /* + * Caution, the assumption here is that some of the bits (such as + * ASCI, CTR_FREEZE, and LBR_FREEZE) are not yet supported by KVM. + */ + if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask)) return 1; /* RO MSR */ pmu->global_status = data; From patchwork Mon Apr 10 10:50:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206270 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DA65C77B61 for ; Mon, 10 Apr 2023 10:51:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229730AbjDJKv2 (ORCPT ); Mon, 10 Apr 2023 06:51:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40744 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229707AbjDJKv0 (ORCPT ); Mon, 10 Apr 2023 06:51:26 -0400 Received: from mail-pj1-x1030.google.com (mail-pj1-x1030.google.com [IPv6:2607:f8b0:4864:20::1030]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A69044236; Mon, 10 Apr 2023 03:51:23 -0700 (PDT) Received: by mail-pj1-x1030.google.com with SMTP id 98e67ed59e1d1-246bc3d38cdso74449a91.1; Mon, 10 Apr 2023 03:51:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681123883; x=1683715883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RWeR6igNoML2gvd7fvpyzsafAnh0P7tkBzGcnQmcT0Q=; b=mAFiJFjZ5RR/d+jCmRdN3sucO+P7ZxYhUzI//njZFWtlb5pxFMhYuDhN7REm1BqPWK FmkiJpM1Vu8uerP8nSrDm0j4kNbjQFLcTT3fgO71j8fpLKMqkw2AZ2WOUWLj+5AbSjYs Msjhue85Kkjtf2mfpci+P1VA5n74HzQeiZDItr6PtgK0++JIrbTi8n1ITEi/YBz/DiqT y0/YENEQtPlQTdDj9LjOIl73KUasapHToshxKfZ/btXqAZk0N0qUcv/4H1RoHbbCFidL fvY/nXHs4y3kIaAt6xMdHoY74i96Mx9hloCvL+pNshs8DHYqMGEQdhGWlsJLxOKpBJcj Iewg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681123883; x=1683715883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RWeR6igNoML2gvd7fvpyzsafAnh0P7tkBzGcnQmcT0Q=; b=2VEyjWgR3DnxV6BbvwFHC3YsKLk/jAjvkJiu6ts288Cddqq+bdxwYm1Bh6UEdW+jym MczbRSyKNl4ahdsSddwf6gW0v5LQaIVnln4W4yiS4ivcv8KSeqtGwumSJD+Ko7c7Acs/ j9aGvsh0z4vxU3Oi29HS/+8i2fpL66iYbTRkCrbRSlOKPRuzR95z15fy7JKATCuaRnYv PXVTGSPxHV4nfaKOwiWgk194yVUJmNZbwoPj37+YeYVq9BfDI0zymgYKEd+z33BMWkxD OvY/vlwhljlukEdkfi+X/KJXkpwMbqXcK4cRoNkzXqA65hXeOraxWCvwQULWT6XUljj8 nF9A== X-Gm-Message-State: AAQBX9fDAhSIPZOphdXZEjrSIX6Oreg9/zGY5Jhwjahm3KWBKGi2/nkD zoQ6hBO0Xpeb1W2dyb1ht5Q= X-Google-Smtp-Source: AKy350ZnV4dOlBVNpvrrEZvXGlK1ArpnwB2TDYOOJ2TM7ATXsS6Wp7qLyHAURUFsPOAUrfT/S43I2w== X-Received: by 2002:aa7:9488:0:b0:637:ecd6:cb0e with SMTP id z8-20020aa79488000000b00637ecd6cb0emr2717323pfk.23.1681123882913; Mon, 10 Apr 2023 03:51:22 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h4-20020a056a00170400b0062e032b61a6sm7783252pfc.91.2023.04.10.03.51.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 03:51:22 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 03/10] KVM: x86/pmu: Make part of the Intel v2 PMU MSRs handling x86 generic Date: Mon, 10 Apr 2023 18:50:49 +0800 Message-Id: <20230410105056.60973-4-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu AMD PerfMonV2 defines three registers similar to part of the Intel v2 PMU registers, including the GLOBAL_CTRL, GLOBAL_STATUS and GLOBAL_OVF_CTRL MSRs. For better code reuse, this specific part of the handling can be extracted to make it generic for X86 as a straight code movement. Specifically, the kvm_pmu_set/get_msr() handlers of GLOBAL_STATUS, GLOBAL_CTRL, GLOBAL_OVF_CTRL defined for Intel are moved to generic pmu.c and the callback function .pmc_is_globally_enabled is removed, which is very helpful to introduce the AMD PerfMonV2 code later. The new eponymous pmc_is_globally_enabled() works well as legacy AMD vPMU version is indexed as 1. Note that the specific *_is_valid_msr will continue to be used to avoid cross-vendor MSR access. Signed-off-by: Like Xu --- arch/x86/include/asm/kvm-x86-pmu-ops.h | 1 - arch/x86/kvm/pmu.c | 61 ++++++++++++++++++++++---- arch/x86/kvm/pmu.h | 17 ++++++- arch/x86/kvm/svm/pmu.c | 9 ---- arch/x86/kvm/vmx/pmu_intel.c | 14 +----- 5 files changed, 70 insertions(+), 32 deletions(-) diff --git a/arch/x86/include/asm/kvm-x86-pmu-ops.h b/arch/x86/include/asm/kvm-x86-pmu-ops.h index c17e3e96fc1d..6c98f4bb4228 100644 --- a/arch/x86/include/asm/kvm-x86-pmu-ops.h +++ b/arch/x86/include/asm/kvm-x86-pmu-ops.h @@ -13,7 +13,6 @@ BUILD_BUG_ON(1) * at the call sites. */ KVM_X86_PMU_OP(hw_event_available) -KVM_X86_PMU_OP(pmc_is_enabled) KVM_X86_PMU_OP(pmc_idx_to_pmc) KVM_X86_PMU_OP(rdpmc_ecx_to_pmc) KVM_X86_PMU_OP(msr_idx_to_pmc) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 597a8f8f90b9..69d0a3ae7b45 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -93,11 +93,6 @@ void kvm_pmu_ops_update(const struct kvm_pmu_ops *pmu_ops) #undef __KVM_X86_PMU_OP } -static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) -{ - return static_call(kvm_x86_pmu_pmc_is_enabled)(pmc); -} - static void kvm_pmi_trigger_fn(struct irq_work *irq_work) { struct kvm_pmu *pmu = container_of(irq_work, struct kvm_pmu, irq_work); @@ -577,13 +572,63 @@ static void kvm_pmu_mark_pmc_in_use(struct kvm_vcpu *vcpu, u32 msr) int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { - return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info); + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + u32 msr = msr_info->index; + + switch (msr) { + case MSR_CORE_PERF_GLOBAL_STATUS: + msr_info->data = pmu->global_status; + break; + case MSR_CORE_PERF_GLOBAL_CTRL: + msr_info->data = pmu->global_ctrl; + break; + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + msr_info->data = 0; + break; + default: + return static_call(kvm_x86_pmu_get_msr)(vcpu, msr_info); + } + + return 0; } int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { - kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); - return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info); + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + u32 msr = msr_info->index; + u64 data = msr_info->data; + u64 diff; + + switch (msr) { + case MSR_CORE_PERF_GLOBAL_STATUS: + if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask)) + return 1; /* RO MSR */ + + pmu->global_status = data; + break; + case MSR_CORE_PERF_GLOBAL_CTRL: + if (!kvm_valid_perf_global_ctrl(pmu, data)) + return 1; + + if (pmu->global_ctrl != data) { + diff = pmu->global_ctrl ^ data; + pmu->global_ctrl = data; + reprogram_counters(pmu, diff); + } + break; + case MSR_CORE_PERF_GLOBAL_OVF_CTRL: + if (data & pmu->global_ovf_ctrl_mask) + return 1; + + if (!msr_info->host_initiated) + pmu->global_status &= ~data; + break; + default: + kvm_pmu_mark_pmc_in_use(vcpu, msr_info->index); + return static_call(kvm_x86_pmu_set_msr)(vcpu, msr_info); + } + + return 0; } /* refresh PMU settings. This function generally is called when underlying diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index 986563aeeef8..dd7c7d4ffe3b 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -20,7 +20,6 @@ struct kvm_pmu_ops { bool (*hw_event_available)(struct kvm_pmc *pmc); - bool (*pmc_is_enabled)(struct kvm_pmc *pmc); struct kvm_pmc *(*pmc_idx_to_pmc)(struct kvm_pmu *pmu, int pmc_idx); struct kvm_pmc *(*rdpmc_ecx_to_pmc)(struct kvm_vcpu *vcpu, unsigned int idx, u64 *mask); @@ -213,6 +212,22 @@ static inline void reprogram_counters(struct kvm_pmu *pmu, u64 diff) kvm_make_request(KVM_REQ_PMU, pmu_to_vcpu(pmu)); } +/* + * Check if a PMC is enabled by comparing it against global_ctrl bits. + * + * If the current version of vPMU doesn't have global_ctrl MSR, + * all vPMCs are enabled (return TRUE). + */ +static inline bool pmc_is_globally_enabled(struct kvm_pmc *pmc) +{ + struct kvm_pmu *pmu = pmc_to_pmu(pmc); + + if (pmu->version < 2) + return true; + + return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); +} + void kvm_pmu_deliver_pmi(struct kvm_vcpu *vcpu); void kvm_pmu_handle_event(struct kvm_vcpu *vcpu); int kvm_pmu_rdpmc(struct kvm_vcpu *vcpu, unsigned pmc, u64 *data); diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 5fa939e411d8..70143275e0a7 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -78,14 +78,6 @@ static bool amd_hw_event_available(struct kvm_pmc *pmc) return true; } -/* check if a PMC is enabled by comparing it against global_ctrl bits. Because - * AMD CPU doesn't have global_ctrl MSR, all PMCs are enabled (return TRUE). - */ -static bool amd_pmc_is_enabled(struct kvm_pmc *pmc) -{ - return true; -} - static bool amd_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -220,7 +212,6 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) struct kvm_pmu_ops amd_pmu_ops __initdata = { .hw_event_available = amd_hw_event_available, - .pmc_is_enabled = amd_pmc_is_enabled, .pmc_idx_to_pmc = amd_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc = amd_rdpmc_ecx_to_pmc, .msr_idx_to_pmc = amd_msr_idx_to_pmc, diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c index 343b3182b7f4..99d07ccb1869 100644 --- a/arch/x86/kvm/vmx/pmu_intel.c +++ b/arch/x86/kvm/vmx/pmu_intel.c @@ -95,17 +95,6 @@ static bool intel_hw_event_available(struct kvm_pmc *pmc) return true; } -/* check if a PMC is enabled by comparing it with globl_ctrl bits. */ -static bool intel_pmc_is_enabled(struct kvm_pmc *pmc) -{ - struct kvm_pmu *pmu = pmc_to_pmu(pmc); - - if (!intel_pmu_has_perf_global_ctrl(pmu)) - return true; - - return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); -} - static bool intel_is_valid_rdpmc_ecx(struct kvm_vcpu *vcpu, unsigned int idx) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -793,7 +782,7 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) pmc = intel_pmc_idx_to_pmc(pmu, bit); if (!pmc || !pmc_speculative_in_use(pmc) || - !intel_pmc_is_enabled(pmc) || !pmc->perf_event) + !pmc_is_globally_enabled(pmc) || !pmc->perf_event) continue; /* @@ -808,7 +797,6 @@ void intel_pmu_cross_mapped_check(struct kvm_pmu *pmu) struct kvm_pmu_ops intel_pmu_ops __initdata = { .hw_event_available = intel_hw_event_available, - .pmc_is_enabled = intel_pmc_is_enabled, .pmc_idx_to_pmc = intel_pmc_idx_to_pmc, .rdpmc_ecx_to_pmc = intel_rdpmc_ecx_to_pmc, .msr_idx_to_pmc = intel_msr_idx_to_pmc, From patchwork Mon Apr 10 10:50:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206271 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF3F6C77B71 for ; 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Mon, 10 Apr 2023 03:51:24 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h4-20020a056a00170400b0062e032b61a6sm7783252pfc.91.2023.04.10.03.51.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 03:51:24 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 04/10] KVM: x86: Explicitly zero cpuid "0xa" leaf when PMU is disabled Date: Mon, 10 Apr 2023 18:50:50 +0800 Message-Id: <20230410105056.60973-5-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Add an explicit !enable_pmu check as relying on kvm_pmu_cap to be zeroed isn't obvious. Although when !enable_pmu, KVM will have zero-padded kvm_pmu_cap to do subsequent CPUID leaf assignments. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/cpuid.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index b736ddb42088..52a7acf2c965 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -970,7 +970,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) union cpuid10_eax eax; union cpuid10_edx edx; - if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { + if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { entry->eax = entry->ebx = entry->ecx = entry->edx = 0; break; } From patchwork Mon Apr 10 10:50:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206272 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22230C77B61 for ; Mon, 10 Apr 2023 10:51:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229733AbjDJKvd (ORCPT ); Mon, 10 Apr 2023 06:51:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40962 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229719AbjDJKv3 (ORCPT ); Mon, 10 Apr 2023 06:51:29 -0400 Received: from mail-pj1-x102b.google.com (mail-pj1-x102b.google.com [IPv6:2607:f8b0:4864:20::102b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24BF65591; Mon, 10 Apr 2023 03:51:27 -0700 (PDT) Received: by mail-pj1-x102b.google.com with SMTP id j8so2214182pjy.4; Mon, 10 Apr 2023 03:51:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681123886; x=1683715886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D3qItoPbhd1cS9wC/WtD5ihRlrUlFhuVlKz/oT0HlAk=; b=Hle8piowxX0J3XV9psl9ZEffGVGw/830cfh4j8jEWWSDjf+8wbg0iu/kbODfn9I3mf vZOgoFcbyGhG1YtybxsbVDbjCK+esSuZYvsBP/MAyqFmm/BSN3REl6qODlbXPFcAWFRF HK9bowYAX1p0s2u/EhhWzYT4ZduBa0OhsO0h4Dj7cZEkyWA+NGF+d4Ulc5dNbQcs95et kwyOsjf5R+YvjVv9L3lJZ4Xehz10C9jdqrpAc2FPPT1Y0FyA9xp3TW1uudGmDKpfkv5K KEi1f9ZY6XpE7FS+zD3PN4jnwX6qExOI/Hid7/SmdHKr0HtjEM7CpOdsmrbkkRPqXwrT pAfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681123886; x=1683715886; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D3qItoPbhd1cS9wC/WtD5ihRlrUlFhuVlKz/oT0HlAk=; b=T9o1IkPVKOdKVsFFOm5KSehqEEqkEqN+Q4xC7U4CeZyyfiP1mzcoLbCnFGAVbaf9+8 CLYll3BbhFv3pp/tCSNht7ukBmhad1/vQfT4PUmTReT1JFFxX4fAgUwKqLfzhPYHelw5 r+W+N9yezortM/mZGpm/b99t9D/LSxfpOXZQdeUB5fEo4IjXXxN09o46VcmqsXwZjIpn lYQ0O8pbJEKyryyTmJ16lX/CZDX6fC9/eTx8gwRHb3A8o7iYTPtHtkFRmR0b1yRabw41 uZ7oD4nGkteznTm4Ys0UiuuazF0/58EN/2TdmGkPtOI1GlO7jf1v0BvSBi9lkeIw1C2b aCfA== X-Gm-Message-State: AAQBX9dz2nqaQeIu1O/WlgJ2qeJiBKpAi5RdPH7C6fIZVVF+FL6cqyeP Q2b45Z3MgGC2oZSY5kTN1yvhbodTC+/YOA== X-Google-Smtp-Source: AKy350bbohQFgi2m1hoUFUcSDjYbtbfgxweMKUYNJ1MsEQFKEzptj+2n3eKbO59XTHe7h3J0eIzyMA== X-Received: by 2002:a05:6a20:1221:b0:e7:c39a:8823 with SMTP id v33-20020a056a20122100b000e7c39a8823mr10787565pzf.12.1681123886452; Mon, 10 Apr 2023 03:51:26 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h4-20020a056a00170400b0062e032b61a6sm7783252pfc.91.2023.04.10.03.51.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 03:51:26 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 05/10] KVM: x86/pmu: Disable vPMU if the minimum num of counters isn't met Date: Mon, 10 Apr 2023 18:50:51 +0800 Message-Id: <20230410105056.60973-6-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu Disable PMU support when running on AMD and perf reports fewer than four general purpose counters. All AMD PMUs must define at least four counters due to AMD's legacy architecture hardcoding the number of counters without providing a way to enumerate the number of counters to software, e.g. from AMD's APM: The legacy architecture defines four performance counters (PerfCtrn) and corresponding event-select registers (PerfEvtSeln). Virtualizing fewer than four counters can lead to guest instability as software expects four counters to be available. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/pmu.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/pmu.h b/arch/x86/kvm/pmu.h index dd7c7d4ffe3b..002b527360f4 100644 --- a/arch/x86/kvm/pmu.h +++ b/arch/x86/kvm/pmu.h @@ -182,6 +182,9 @@ static inline void kvm_init_pmu_capability(const struct kvm_pmu_ops *pmu_ops) enable_pmu = false; } + if (!is_intel && kvm_pmu_cap.num_counters_gp < AMD64_NUM_COUNTERS) + enable_pmu = false; + if (!enable_pmu) { memset(&kvm_pmu_cap, 0, sizeof(kvm_pmu_cap)); return; From patchwork Mon Apr 10 10:50:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206273 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D9A3CC77B61 for ; Mon, 10 Apr 2023 10:51:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229779AbjDJKvy (ORCPT ); Mon, 10 Apr 2023 06:51:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41900 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229785AbjDJKvp (ORCPT ); Mon, 10 Apr 2023 06:51:45 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70BFC61BD; Mon, 10 Apr 2023 03:51:31 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id ke16so4281991plb.6; Mon, 10 Apr 2023 03:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681123888; x=1683715888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=siL/5td9QhsXXhtZYPTjo70/OQWDBNwZqVddnZ8Ql0o=; b=XfthjGDRGhw6nwtA8r2xAWSOgEgP9OSKtiBqgfLNukbgatKKWynjGqSvNx7vLSoj2J KoSR89pzlYfuvBHqw7tSj6DhOdzrUWiJE9Ql14Z6kT6HkY2KisbBJnUfjozl4rxQ6j37 tG+RK0huU4zzK4yNCM1XGoE06l9S4aO9TGDoqGYE3U8EhtGRko+6tF6CAYWh7WlV0wcY 2/qUH/imVQTk+hDka7LbUhgRATu44TrmToPJhXWCDZiobgxp4OlN4q4l4a4VRrhXVHwl Q7Wee3+wfFy/lqP/90uX9KKxvVEtIAFaqJITLo8Vs+PAUxLWJIi0kE9RD5Q3CYU4aFD7 OGmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681123888; x=1683715888; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=siL/5td9QhsXXhtZYPTjo70/OQWDBNwZqVddnZ8Ql0o=; b=phXgEv/2VFum3MYE9Ydz/CCHhypTzpLM8/udOXDcdx8GuI56Co/+jDcppS2mjkUDLu Hcc6wZqrEsVaotAiMFsAnfw2qdTNKD/gHtrVfVieMqScG8gR//NctnNgxKZLB16VDlfz 32vwOIRMCrjchNJ9Nb9knm6tHnNrKVAslpFN/BIFKJh2SOOS0kNH9zFCcrCYJ5ezakim Jr4QqoUFdPsJeakM2h2x8Yb5/XeY/rzJfVvRy5Deh4AuXBnx29ZU7znpnLxXK7v6NtQD 6ooxuLIcYNXo87OqIOwR1oPM5k5Y0u/TOkP81m0V32lfYtKDiKhCRy9IH1pZB2+laDEc k6TA== X-Gm-Message-State: AAQBX9f1oFN1GsMz+ZD3N4k/Cbd65RYurZE3yLqwbdPAW0XR33Cc2Bb5 Xf1wFG5f8q8MxrUXSoXPeh8= X-Google-Smtp-Source: AKy350ZoRXrpnjQNpJQNzEffJxeh8gid6aBA2Kk3d5YCA/5SyNeZwDxMqP14qkAC/wCpL7S6Hyczgw== X-Received: by 2002:a05:6a20:8e19:b0:d9:6660:8746 with SMTP id y25-20020a056a208e1900b000d966608746mr14705391pzj.18.1681123887993; Mon, 10 Apr 2023 03:51:27 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h4-20020a056a00170400b0062e032b61a6sm7783252pfc.91.2023.04.10.03.51.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 03:51:27 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 06/10] KVM: x86/pmu: Forget PERFCTR_CORE if the min num of counters isn't met Date: Mon, 10 Apr 2023 18:50:52 +0800 Message-Id: <20230410105056.60973-7-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu A sanity check on the number of counters enumerated by perf is added. PERFCTR_CORE support is explicitly dropped if the min number isn't met. E.g. if KVM needs 6 counters and perf says there are 4, then something is wrong and enumerating 6 to a guest is only going to cause more issues. Opportunistically, the kvm_cpu_cap_check_and_set() is applied to simplify the host check before setting the PERFCTR_CORE flag. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/svm/svm.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 7584eb85410b..683f1b480fcb 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4928,9 +4928,18 @@ static __init void svm_set_cpu_caps(void) boot_cpu_has(X86_FEATURE_AMD_SSBD)) kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); - /* AMD PMU PERFCTR_CORE CPUID */ - if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE)) - kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE); + if (enable_pmu) { + /* + * Enumerate support for PERFCTR_CORE if and only if KVM has + * access to enough counters to virtualize "core" support, + * otherwise limit vPMU support to the legacy number of counters. + */ + if (kvm_pmu_cap.num_counters_gp < AMD64_NUM_COUNTERS_CORE) + kvm_pmu_cap.num_counters_gp = min(AMD64_NUM_COUNTERS, + kvm_pmu_cap.num_counters_gp); + else + kvm_cpu_cap_check_and_set(X86_FEATURE_PERFCTR_CORE); + } /* CPUID 0x8000001F (SME/SEV features) */ sev_set_cpu_caps(); From patchwork Mon Apr 10 10:50:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206274 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 388D0C76196 for ; Mon, 10 Apr 2023 10:51:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229808AbjDJKv4 (ORCPT ); Mon, 10 Apr 2023 06:51:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41600 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229670AbjDJKvq (ORCPT ); Mon, 10 Apr 2023 06:51:46 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 72BBD4EEF; Mon, 10 Apr 2023 03:51:31 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-24677297572so110641a91.1; Mon, 10 Apr 2023 03:51:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681123889; x=1683715889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cdQCFY7on5P+S/gm8INkvpwBpAxQTaUMH+FZDvUGdXY=; b=ho2riEP7y1sxLHyQL07IlwBlbWd14tnATzi3WcnzbTF2fZGfrEmQR816WFcw/eiaac 5bUOLFVPCMh56byqJvK/O/xajl/T6PGSi9416bagR7CADPOC6Zhv27L7ATGr/xp3ZTVy WUpYf/6U5Jutdbwz5ieBo+TPR8qB5JagpfuFzUTzwb/E5wI61EWXA+iPMAnhL54saXaR muy+/fuB+eMmV7i/CmNOcOQ070rArwKZv7chlMwxuT4FQVDGQwKvw7S/xvCD1Y4mfblT ItWOfHajAmUAM/yBlSfeZ+b/8Slju2WEXkhP0HBwLAfC+HJ8wfqEfbUrbIPsF3Nf9Hxg OF7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681123889; x=1683715889; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cdQCFY7on5P+S/gm8INkvpwBpAxQTaUMH+FZDvUGdXY=; b=VbFXChg8BOtSbPhXgRlgkaNhpotyP0BGo/6Vj649viUezjrDmJtQoKD125Fn2IlwZy x6f01u3xb5dHVT27FvG6riooruNZKDV8pPTN22Dd6bq8v4MpkuwKUxaswX+L0cEHYwTj lKYS4pw944Al2bBxW8yP/oSnS65+6bDcWh+HdNbulDFzcBYtkogq514/rnExZXqHLomN iI9lvuc0uK/D9c1yOXrp78g3o+FxICf8TA7qlUr150gg7xrtQTw/HkQP7nOXauqRGZOU b+ChOROgPV7rZX7UbIZbo6ok1ToPAVkxx9uF2xjJxdWbaiUCkj/T/rPyrbWYR0QyKl1f U/Fw== X-Gm-Message-State: AAQBX9eL01TM+bTLTQMABnP8ApD1f3abnMi5xWUBwzr7Vy9cphnGF1X6 qVb0yefs5rd75McshIoC/dvZTE9Ds5PZ1g== X-Google-Smtp-Source: AKy350Y2H5MnE21z1fJM5d+wBKkUnCfLnEpP37PjlWbxSWNTt1qP3IA1yZs/v2Tywlu2yQgEz5GoKQ== X-Received: by 2002:a62:5255:0:b0:638:7e00:48c4 with SMTP id g82-20020a625255000000b006387e0048c4mr2452892pfb.21.1681123889559; Mon, 10 Apr 2023 03:51:29 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h4-20020a056a00170400b0062e032b61a6sm7783252pfc.91.2023.04.10.03.51.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 03:51:29 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 07/10] KVM: x86/pmu: Constrain the num of guest counters with kvm_pmu_cap Date: Mon, 10 Apr 2023 18:50:53 +0800 Message-Id: <20230410105056.60973-8-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu A sanity check is added to limit the number of AMD guest counters, which help avoid a situation if KVM only has access to 4 counters, but user space sets guest X86_FEATURE_PERFCTR_CORE anyways. Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/svm/pmu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 70143275e0a7..825b9cc26ae5 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -170,6 +170,9 @@ static void amd_pmu_refresh(struct kvm_vcpu *vcpu) else pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS; + pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters, + kvm_pmu_cap.num_counters_gp); + pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1; pmu->reserved_bits = 0xfffffff000280000ull; pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; From patchwork Mon Apr 10 10:50:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206275 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C170CC76196 for ; Mon, 10 Apr 2023 10:52:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229868AbjDJKwJ (ORCPT ); Mon, 10 Apr 2023 06:52:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229771AbjDJKvw (ORCPT ); Mon, 10 Apr 2023 06:51:52 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8194C7ABF; Mon, 10 Apr 2023 03:51:37 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-2467736d1c6so212712a91.2; Mon, 10 Apr 2023 03:51:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; t=1681123891; x=1683715891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=VOg/+c/G3VaaM9K0QFYQTbvifMIEuvnJxkrgp3NNysU=; b=lKs/DvJBKJnaZZgO/n8km6dzrGzOHLTyY8aATpZ69AGrI7fQmaptA7Blcw/eeD3cxr 1yOR10Bgz1IFC9lSbQ0HhGdp6b/5VO4RBGSH996nF6C+pUUUTXtFWn/iViGy2Lw62rZ9 APpYOITBn22lGewetwI4X/mXF7CEpM+T0DHE9yPck8435JJi2eJAoBA2xpRJA3cwyzO3 NOjY3zrz6jogqTCPkf7uvv1sHLIw3MgSwpjSnK5kvnIeBea+PrttIbBcpyAZ36dvu38t iJ7ivNqiv2k6FMaXcvOopYNWffDVtidHH+NlW1xiQo79Rxk8qsEknpnMiQWtoLQrDoqm KSwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1681123891; x=1683715891; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=VOg/+c/G3VaaM9K0QFYQTbvifMIEuvnJxkrgp3NNysU=; b=usHkspA5UQCt7XaqSI3ncNywL38fc3dP0TfC51IolQVbIWqs2W0+j0ZdUwnmxmhU4L imN/hBMxyl1iV9bojXjKV6SEgUI6DCcpS0Sst4MwrY1E58HF/FjhmsSjCsXCtSYnopy8 3BL8osyoMvGZxAxcMUnXujkeLuIu2E2UcVT3el4IZOvzMZ4OB0tKXxumv5m21AAIlPLS GUt41goghqLWbVJpi5u8f2eH9TaA/GajAL7R4YFRa0Zxe20aW2/2buRtCzn2oXp4iYZv 1S1q7cOGzKt4rEFC+lCNYUX0NrBhNFN9KEG44IQ0D0yCloF8C/Q1AabrgO2WaJFsXjcj kCZg== X-Gm-Message-State: AAQBX9cDXwulNMOe0gGI8kbkC7JvdamM5oa4AWUHzp4ueHj6X0+vpgJI MKhTZMeAxQDdgDgLbo8voGA= X-Google-Smtp-Source: AKy350Y0l/Xy0MOOr+Hx+VT4fsOco2CjQkIlByB3RzddbFkqj2dhaZendap8pteVG6M63WaNyxbAcA== X-Received: by 2002:a62:5257:0:b0:635:1d57:bdee with SMTP id g84-20020a625257000000b006351d57bdeemr4572705pfb.11.1681123891125; Mon, 10 Apr 2023 03:51:31 -0700 (PDT) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id h4-20020a056a00170400b0062e032b61a6sm7783252pfc.91.2023.04.10.03.51.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Apr 2023 03:51:30 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH V5 08/10] KVM: x86/cpuid: Add a KVM-only leaf to redirect AMD PerfMonV2 flag Date: Mon, 10 Apr 2023 18:50:54 +0800 Message-Id: <20230410105056.60973-9-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu A KVM-only leaf for AMD's PerfMonV2 feature flag is defined to redirect the kernel's scattered version to its architectural location, e.g. so that KVM can query guest support via guest_cpuid_has(). Suggested-by: Sean Christopherson Signed-off-by: Like Xu --- arch/x86/kvm/reverse_cpuid.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/x86/kvm/reverse_cpuid.h b/arch/x86/kvm/reverse_cpuid.h index a5717282bb9c..56cbdb24400a 100644 --- a/arch/x86/kvm/reverse_cpuid.h +++ b/arch/x86/kvm/reverse_cpuid.h @@ -15,6 +15,7 @@ enum kvm_only_cpuid_leafs { CPUID_12_EAX = NCAPINTS, CPUID_7_1_EDX, CPUID_8000_0007_EDX, + CPUID_8000_0022_EAX, NR_KVM_CPU_CAPS, NKVMCAPINTS = NR_KVM_CPU_CAPS - NCAPINTS, @@ -47,6 +48,9 @@ enum kvm_only_cpuid_leafs { /* CPUID level 0x80000007 (EDX). */ #define KVM_X86_FEATURE_CONSTANT_TSC KVM_X86_FEATURE(CPUID_8000_0007_EDX, 8) +/* CPUID level 0x80000022 (EAX) */ +#define KVM_X86_FEATURE_PERFMON_V2 KVM_X86_FEATURE(CPUID_8000_0022_EAX, 0) + struct cpuid_reg { u32 function; u32 index; @@ -74,6 +78,7 @@ static const struct cpuid_reg reverse_cpuid[] = { [CPUID_7_1_EDX] = { 7, 1, CPUID_EDX}, [CPUID_8000_0007_EDX] = {0x80000007, 0, CPUID_EDX}, [CPUID_8000_0021_EAX] = {0x80000021, 0, CPUID_EAX}, + [CPUID_8000_0022_EAX] = {0x80000022, 0, CPUID_EAX}, }; /* @@ -108,6 +113,8 @@ static __always_inline u32 __feature_translate(int x86_feature) return KVM_X86_FEATURE_SGX_EDECCSSA; else if (x86_feature == X86_FEATURE_CONSTANT_TSC) return KVM_X86_FEATURE_CONSTANT_TSC; + else if (x86_feature == X86_FEATURE_PERFMON_V2) + return KVM_X86_FEATURE_PERFMON_V2; return x86_feature; } From patchwork Mon Apr 10 10:50:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206277 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 23073C77B6F for ; Mon, 10 Apr 2023 10:52:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229847AbjDJKwX (ORCPT ); Mon, 10 Apr 2023 06:52:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41890 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229845AbjDJKwI (ORCPT ); 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Mon, 10 Apr 2023 03:51:33 -0700 (PDT) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson Cc: Paolo Bonzini , kvm@vger.kernel.org, linux-kernel@vger.kernel.org, Sandipan Das Subject: [PATCH V5 09/10] KVM: x86/svm/pmu: Add AMD PerfMonV2 support Date: Mon, 10 Apr 2023 18:50:55 +0800 Message-Id: <20230410105056.60973-10-likexu@tencent.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230410105056.60973-1-likexu@tencent.com> References: <20230410105056.60973-1-likexu@tencent.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org From: Like Xu If AMD Performance Monitoring Version 2 (PerfMonV2) is detected by the guest, it can use a new scheme to manage the Core PMCs using the new global control and status registers. In addition to benefiting from the PerfMonV2 functionality in the same way as the host (higher precision), the guest also can reduce the number of vm-exits by lowering the total number of MSRs accesses. In terms of implementation details, amd_is_valid_msr() is resurrected since three newly added MSRs could not be mapped to one vPMC. The possibility of emulating PerfMonV2 on the mainframe has also been eliminated for reasons of precision. Co-developed-by: Sandipan Das Signed-off-by: Sandipan Das Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 24 +++++++++++++++++- arch/x86/kvm/svm/pmu.c | 55 ++++++++++++++++++++++++++++++++++-------- arch/x86/kvm/x86.c | 10 ++++++++ 3 files changed, 78 insertions(+), 11 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 69d0a3ae7b45..7d2678f06863 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -577,11 +577,18 @@ int kvm_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) switch (msr) { case MSR_CORE_PERF_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: msr_info->data = pmu->global_status; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + /* Based on the observed HW. */ + fallthrough; case MSR_CORE_PERF_GLOBAL_CTRL: msr_info->data = pmu->global_ctrl; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + /* Based on the observed HW. */ + fallthrough; case MSR_CORE_PERF_GLOBAL_OVF_CTRL: msr_info->data = 0; break; @@ -599,13 +606,26 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) u64 data = msr_info->data; u64 diff; + /* + * Note, AMD ignores writes to reserved bits and read-only PMU MSRs, + * whereas Intel generates #GP on attempts to write reserved/RO MSRs. + */ switch (msr) { case MSR_CORE_PERF_GLOBAL_STATUS: if (!msr_info->host_initiated || (data & pmu->global_ovf_ctrl_mask)) return 1; /* RO MSR */ + fallthrough; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + /* Per PPR, Read-only MSR. Writes are ignored. */ + if (!msr_info->host_initiated) + break; pmu->global_status = data; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + /* Based on the observed HW. */ + data &= ~pmu->global_ctrl_mask; + fallthrough; case MSR_CORE_PERF_GLOBAL_CTRL: if (!kvm_valid_perf_global_ctrl(pmu, data)) return 1; @@ -619,7 +639,9 @@ int kvm_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) case MSR_CORE_PERF_GLOBAL_OVF_CTRL: if (data & pmu->global_ovf_ctrl_mask) return 1; - + fallthrough; + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + /* Based on the observed HW. */ if (!msr_info->host_initiated) pmu->global_status &= ~data; break; diff --git a/arch/x86/kvm/svm/pmu.c b/arch/x86/kvm/svm/pmu.c index 825b9cc26ae5..56607a3f6a47 100644 --- a/arch/x86/kvm/svm/pmu.c +++ b/arch/x86/kvm/svm/pmu.c @@ -94,12 +94,6 @@ static struct kvm_pmc *amd_rdpmc_ecx_to_pmc(struct kvm_vcpu *vcpu, return amd_pmc_idx_to_pmc(vcpu_to_pmu(vcpu), idx & ~(3u << 30)); } -static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) -{ - /* All MSRs refer to exactly one PMC, so msr_idx_to_pmc is enough. */ - return false; -} - static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -111,6 +105,29 @@ static struct kvm_pmc *amd_msr_idx_to_pmc(struct kvm_vcpu *vcpu, u32 msr) return pmc; } +static bool amd_is_valid_msr(struct kvm_vcpu *vcpu, u32 msr) +{ + struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + + switch (msr) { + case MSR_K7_EVNTSEL0 ... MSR_K7_PERFCTR3: + return pmu->version > 0; + case MSR_F15H_PERF_CTL0 ... MSR_F15H_PERF_CTR5: + return guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE); + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + return pmu->version > 1; + default: + if (msr > MSR_F15H_PERF_CTR5 && + msr < MSR_F15H_PERF_CTL0 + 2 * pmu->nr_arch_gp_counters) + return pmu->version > 1; + break; + } + + return amd_msr_idx_to_pmc(vcpu, msr); +} + static int amd_pmu_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); @@ -164,23 +181,39 @@ static int amd_pmu_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info) static void amd_pmu_refresh(struct kvm_vcpu *vcpu) { struct kvm_pmu *pmu = vcpu_to_pmu(vcpu); + union cpuid_0x80000022_ebx ebx; - if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) + pmu->version = 1; + if (guest_cpuid_has(vcpu, X86_FEATURE_PERFMON_V2)) { + pmu->version = 2; + /* + * Note, PERFMON_V2 is also in 0x80000022.0x0, i.e. the guest + * CPUID entry is guaranteed to be non-NULL. + */ + BUILD_BUG_ON(x86_feature_cpuid(X86_FEATURE_PERFMON_V2).function != 0x80000022 || + x86_feature_cpuid(X86_FEATURE_PERFMON_V2).index); + ebx.full = kvm_find_cpuid_entry_index(vcpu, 0x80000022, 0)->ebx; + pmu->nr_arch_gp_counters = ebx.split.num_core_pmc; + } else if (guest_cpuid_has(vcpu, X86_FEATURE_PERFCTR_CORE)) { pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS_CORE; - else + } else { pmu->nr_arch_gp_counters = AMD64_NUM_COUNTERS; + } pmu->nr_arch_gp_counters = min_t(unsigned int, pmu->nr_arch_gp_counters, kvm_pmu_cap.num_counters_gp); + if (pmu->version > 1) { + pmu->global_ctrl_mask = ~((1ull << pmu->nr_arch_gp_counters) - 1); + pmu->global_ovf_ctrl_mask = pmu->global_ctrl_mask; + } + pmu->counter_bitmask[KVM_PMC_GP] = ((u64)1 << 48) - 1; pmu->reserved_bits = 0xfffffff000280000ull; pmu->raw_event_mask = AMD64_RAW_EVENT_MASK; - pmu->version = 1; /* not applicable to AMD; but clean them to prevent any fall out */ pmu->counter_bitmask[KVM_PMC_FIXED] = 0; pmu->nr_arch_fixed_counters = 0; - pmu->global_status = 0; bitmap_set(pmu->all_valid_pmc_idx, 0, pmu->nr_arch_gp_counters); } @@ -211,6 +244,8 @@ static void amd_pmu_reset(struct kvm_vcpu *vcpu) pmc_stop_counter(pmc); pmc->counter = pmc->prev_counter = pmc->eventsel = 0; } + + pmu->global_ctrl = pmu->global_status = 0; } struct kvm_pmu_ops amd_pmu_ops __initdata = { diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c index a86ad45a53b8..a389ebd2ded1 100644 --- a/arch/x86/kvm/x86.c +++ b/arch/x86/kvm/x86.c @@ -1468,6 +1468,10 @@ static const u32 msrs_to_save_pmu[] = { MSR_F15H_PERF_CTL3, MSR_F15H_PERF_CTL4, MSR_F15H_PERF_CTL5, MSR_F15H_PERF_CTR0, MSR_F15H_PERF_CTR1, MSR_F15H_PERF_CTR2, MSR_F15H_PERF_CTR3, MSR_F15H_PERF_CTR4, MSR_F15H_PERF_CTR5, + + MSR_AMD64_PERF_CNTR_GLOBAL_CTL, + MSR_AMD64_PERF_CNTR_GLOBAL_STATUS, + MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR, }; static u32 msrs_to_save[ARRAY_SIZE(msrs_to_save_base) + @@ -7110,6 +7114,12 @@ static void kvm_probe_msr_to_save(u32 msr_index) kvm_pmu_cap.num_counters_fixed) return; break; + case MSR_AMD64_PERF_CNTR_GLOBAL_CTL: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: + case MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: + if (!kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) + return; + break; case MSR_IA32_XFD: case MSR_IA32_XFD_ERR: if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) From patchwork Mon Apr 10 10:50:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 13206276 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E5D2C77B61 for ; Mon, 10 Apr 2023 10:52:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229897AbjDJKwV (ORCPT ); Mon, 10 Apr 2023 06:52:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42676 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229847AbjDJKwI (ORCPT ); Mon, 10 Apr 2023 06:52:08 -0400 Received: from mail-pf1-x42c.google.com (mail-pf1-x42c.google.com [IPv6:2607:f8b0:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56DF24C35; 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Bit 0 of EAX indicates support for Performance Monitoring Version 2 (PerfMonV2) features. If found to be set during PMU initialization, the EBX bits of the same CPUID function can be used to determine the number of available PMCs for different PMU types. Expose the relevant bits via KVM_GET_SUPPORTED_CPUID so that guests can make use of the PerfMonV2 features. Co-developed-by: Sandipan Das Signed-off-by: Sandipan Das Signed-off-by: Like Xu --- arch/x86/kvm/cpuid.c | 28 +++++++++++++++++++++++++++- arch/x86/kvm/svm/svm.c | 4 ++++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c index 52a7acf2c965..9b25036ab042 100644 --- a/arch/x86/kvm/cpuid.c +++ b/arch/x86/kvm/cpuid.c @@ -756,6 +756,10 @@ void kvm_set_cpu_caps(void) F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ ); + kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX, + F(PERFMON_V2) + ); + /* * Synthesize "LFENCE is serializing" into the AMD-defined entry in * KVM's supported CPUID if the feature is reported as supported by the @@ -1150,7 +1154,7 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->edx = 0; break; case 0x80000000: - entry->eax = min(entry->eax, 0x80000021); + entry->eax = min(entry->eax, 0x80000022); /* * Serializing LFENCE is reported in a multitude of ways, and * NullSegClearsBase is not reported in CPUID on Zen2; help @@ -1255,6 +1259,28 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) entry->ebx = entry->ecx = entry->edx = 0; cpuid_entry_override(entry, CPUID_8000_0021_EAX); break; + /* AMD Extended Performance Monitoring and Debug */ + case 0x80000022: { + union cpuid_0x80000022_ebx ebx; + + entry->ecx = entry->edx = 0; + if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { + entry->eax = entry->ebx; + break; + } + + cpuid_entry_override(entry, CPUID_8000_0022_EAX); + + if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) + ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; + else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) + ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; + else + ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; + + entry->ebx = ebx.full; + break; + } /*Add support for Centaur's CPUID instruction*/ case 0xC0000000: /*Just support up to 0xC0000004 now*/ diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 683f1b480fcb..dc1a9104c274 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -4939,6 +4939,10 @@ static __init void svm_set_cpu_caps(void) kvm_pmu_cap.num_counters_gp); else kvm_cpu_cap_check_and_set(X86_FEATURE_PERFCTR_CORE); + + if (kvm_pmu_cap.version != 2 || + !kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) + kvm_cpu_cap_clear(X86_FEATURE_PERFMON_V2); } /* CPUID 0x8000001F (SME/SEV features) */