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Tue, 11 Apr 2023 03:03:00 +0000 From: "Peng Fan (OSS)" To: abelvesa@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com Cc: linux-imx@nxp.com, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Shengjiu Wang , Peng Fan Subject: [PATCH V3] clk: imx: imx6sx: spdif clock rate is too high for asrc Date: Tue, 11 Apr 2023 11:08:01 +0800 Message-Id: <20230411030801.2964482-1-peng.fan@oss.nxp.com> X-Mailer: git-send-email 2.37.1 X-ClientProxiedBy: SI1PR02CA0033.apcprd02.prod.outlook.com (2603:1096:4:1f6::14) To DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DU0PR04MB9417:EE_|PAXPR04MB9278:EE_ X-MS-Office365-Filtering-Correlation-Id: 39fb5c0f-c415-40e8-158c-08db3a3941fe X-MS-Exchange-SharedMailbox-RoutingAgent-Processed: True X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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So we need to set spdif clock to a proper rate. which make asrc divider not exceed maximum value, at least one of divider not exceed maximum value. The target is spdif clock rate / output(or input) sample rate less than 1024(which is maximum divider). Fixes: d55135689019 ("ARM: imx: add clock driver for imx6sx") Signed-off-by: Shengjiu Wang Signed-off-by: Peng Fan --- V3: Update Fixes tag V2: Add Fixes tag drivers/clk/imx/clk-imx6sx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c index 7cf86707bc39..3face052527d 100644 --- a/drivers/clk/imx/clk-imx6sx.c +++ b/drivers/clk/imx/clk-imx6sx.c @@ -520,7 +520,7 @@ static void __init imx6sx_clocks_init(struct device_node *ccm_node) clk_set_rate(hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk, 393216000); clk_set_parent(hws[IMX6SX_CLK_SPDIF_SEL]->clk, hws[IMX6SX_CLK_PLL4_AUDIO_DIV]->clk); - clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 98304000); + clk_set_rate(hws[IMX6SX_CLK_SPDIF_PODF]->clk, 24576000); clk_set_parent(hws[IMX6SX_CLK_AUDIO_SEL]->clk, hws[IMX6SX_CLK_PLL3_USB_OTG]->clk); clk_set_rate(hws[IMX6SX_CLK_AUDIO_PODF]->clk, 24000000);