From patchwork Tue Apr 11 06:47:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 13207118 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BDA05C77B6F for ; Tue, 11 Apr 2023 06:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=G0vquwzuMniR6VZibLt3Mao0qM3/AOGDIKoMwUBm7p4=; b=DhBxkDKDrWh0rd F3D5j7aA6bq0Ul8C+WypaAYNI8QODasvHZE1ROwZPwWqdWT9seTIgBCpH4KXVB9m4VUiB/WLIUXia qEIUO/QMYqfL1xDzRvYT8TJMSDq/EXaPti38WUbnEn5K8+rdRZss8tKL/+HF+BLd5NZSLEErALbM6 IlHyu9Myvge4nXpviOYZZdirp5XXsduX/SVhVapp2YrTpBw1V9dcRgFWb6EmDAsrSDryowjc8xaab JVhFtY8UInhC++EFMl7y/ySqc8iIXteHSniD+Bmob/cFa5z3LRIMuFZ1NVi4/yQhjxl5kwQKlgcg4 I9bl6oVWcZhCzdkBLAAg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pm7nt-00Gcbb-2k; Tue, 11 Apr 2023 06:48:33 +0000 Received: from fd01.gateway.ufhost.com ([61.152.239.71]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pm7nr-00GcQP-0X for linux-riscv@lists.infradead.org; Tue, 11 Apr 2023 06:48:32 +0000 Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id BF0FC24DB89; Tue, 11 Apr 2023 14:47:45 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:45 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:44 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 1/7] dt-bindings: power: Constrain properties for JH7110 PMU Date: Mon, 10 Apr 2023 23:47:37 -0700 Message-ID: <20230411064743.273388-2-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230410_234831_376443_C7A6224F X-CRM114-Status: GOOD ( 10.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org When use "starfive,jh7110-pmu-dphy" compatible, do not need the reg and interrupts properties. Signed-off-by: Changhuang Liang --- .../bindings/power/starfive,jh7110-pmu.yaml | 14 ++++++++++++-- include/dt-bindings/power/starfive,jh7110-pmu.h | 3 +++ 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml index 98eb8b4110e7..ffb4406c2e56 100644 --- a/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml +++ b/Documentation/devicetree/bindings/power/starfive,jh7110-pmu.yaml @@ -8,6 +8,7 @@ title: StarFive JH7110 Power Management Unit maintainers: - Walker Chen + - Changhuang Liang description: | StarFive JH7110 SoC includes support for multiple power domains which can be @@ -17,6 +18,7 @@ properties: compatible: enum: - starfive,jh7110-pmu + - starfive,jh7110-pmu-dphy reg: maxItems: 1 @@ -29,10 +31,18 @@ properties: required: - compatible - - reg - - interrupts - "#power-domain-cells" +if: + properties: + compatible: + contains: + const: starfive,jh7110-pmu +then: + required: + - reg + - interrupts + additionalProperties: false examples: diff --git a/include/dt-bindings/power/starfive,jh7110-pmu.h b/include/dt-bindings/power/starfive,jh7110-pmu.h index 132bfe401fc8..0bfd6700c144 100644 --- a/include/dt-bindings/power/starfive,jh7110-pmu.h +++ b/include/dt-bindings/power/starfive,jh7110-pmu.h @@ -14,4 +14,7 @@ #define JH7110_PD_ISP 5 #define JH7110_PD_VENC 6 +#define JH7110_PD_DPHY_TX 0 +#define JH7110_PD_DPHY_RX 1 + #endif From patchwork Tue Apr 11 06:47:38 2023 Content-Type: text/plain; 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Tue, 11 Apr 2023 14:47:46 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:45 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 2/7] soc: starfive: Replace SOC_STARFIVE with ARCH_SATRFIVE Date: Mon, 10 Apr 2023 23:47:38 -0700 Message-ID: <20230411064743.273388-3-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230410_234837_969210_C50040C7 X-CRM114-Status: GOOD ( 10.22 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Using ARCH_FOO symbol is preferred than SOC_FOO. Signed-off-by: Changhuang Liang Reviewed-by: Conor Dooley --- drivers/soc/starfive/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/soc/starfive/Kconfig b/drivers/soc/starfive/Kconfig index bdb96dc4c989..1e9b0c414fec 100644 --- a/drivers/soc/starfive/Kconfig +++ b/drivers/soc/starfive/Kconfig @@ -3,8 +3,8 @@ config JH71XX_PMU bool "Support PMU for StarFive JH71XX Soc" depends on PM - depends on SOC_STARFIVE || COMPILE_TEST - default SOC_STARFIVE + depends on ARCH_STARFIVE || COMPILE_TEST + default ARCH_STARFIVE select PM_GENERIC_DOMAINS help Say 'y' here to enable support power domain support. From patchwork Tue Apr 11 06:47:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 13207120 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CBB89C76196 for ; Tue, 11 Apr 2023 06:48:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ISu0uKGojO7o/oL4saRlzfoeYCDZ4FCwkFrhVXmLl3Y=; b=TkKKnIz2JQT4cQ WyyYts3/13ad+5w0afoHtTeWaEJRUslsLaTOcAqXAtRDGr3oHYkif1vBws1thH/BNh1YdmX4Jdhtf dX5jl6SRVpPWlt3y/30VMaOy5nRMg03H0ZCJwKkPBZOZaZayAtA1Q4P0tXwkJgyrJSZWpu+WJSlMv EFg3PQR9od9oIPRzv2fEBhLxp7JUKtyJGB+ab1r5IOvKcjSlC7PgteqA/tUWyRIpYhW9UaueDvOXW 33ZR6lBVCffRIGZAl5DiRkFFnOVG18mPkl847DyAIqqPiuvhU4el0U8gQNHmQwi1aW+Q/sX/4xKwb sK5HnH81fxwXN4RZS8ig==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pm7nz-00Gcf1-01; Tue, 11 Apr 2023 06:48:39 +0000 Received: from ex01.ufhost.com ([61.152.239.75]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pm7nv-00GcQE-1T for linux-riscv@lists.infradead.org; Tue, 11 Apr 2023 06:48:37 +0000 Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 445FD24E225; Tue, 11 Apr 2023 14:47:47 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:47 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:46 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 3/7] soc: starfive: Modify ioremap to regmap Date: Mon, 10 Apr 2023 23:47:39 -0700 Message-ID: <20230411064743.273388-4-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230410_234835_802070_F3FAACA4 X-CRM114-Status: GOOD ( 15.52 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Modify ioremap to regmap, easy to simplify code. Signed-off-by: Changhuang Liang --- drivers/soc/starfive/jh71xx_pmu.c | 43 +++++++++++++++++-------------- 1 file changed, 23 insertions(+), 20 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c index 7d5f50d71c0d..306218c83691 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -6,13 +6,13 @@ */ #include -#include -#include +#include #include #include #include #include #include +#include #include /* register offset */ @@ -59,7 +59,7 @@ struct jh71xx_pmu_match_data { struct jh71xx_pmu { struct device *dev; const struct jh71xx_pmu_match_data *match_data; - void __iomem *base; + struct regmap *base; struct generic_pm_domain **genpd; struct genpd_onecell_data genpd_data; int irq; @@ -75,11 +75,14 @@ struct jh71xx_pmu_dev { static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on) { struct jh71xx_pmu *pmu = pmd->pmu; + unsigned int val; if (!mask) return -EINVAL; - *is_on = readl(pmu->base + JH71XX_PMU_CURR_POWER_MODE) & mask; + regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val); + + *is_on = val & mask; return 0; } @@ -130,7 +133,7 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) encourage_hi = JH71XX_PMU_SW_ENCOURAGE_DIS_HI; } - writel(mask, pmu->base + mode); + regmap_write(pmu->base, mode, mask); /* * 2.Write SW encourage command sequence to the Software Encourage Reg (offset 0x44) @@ -140,21 +143,21 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) * Then write the lower bits of the command sequence, followed by the upper * bits. The sequence differs between powering on & off a domain. */ - writel(JH71XX_PMU_SW_ENCOURAGE_ON, pmu->base + JH71XX_PMU_SW_ENCOURAGE); - writel(encourage_lo, pmu->base + JH71XX_PMU_SW_ENCOURAGE); - writel(encourage_hi, pmu->base + JH71XX_PMU_SW_ENCOURAGE); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, JH71XX_PMU_SW_ENCOURAGE_ON); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, encourage_lo); + regmap_write(pmu->base, JH71XX_PMU_SW_ENCOURAGE, encourage_hi); spin_unlock_irqrestore(&pmu->lock, flags); /* Wait for the power domain bit to be enabled / disabled */ if (on) { - ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE, - val, val & mask, - 1, JH71XX_PMU_TIMEOUT_US); + ret = regmap_read_poll_timeout_atomic(pmu->base, JH71XX_PMU_CURR_POWER_MODE, + val, val & mask, + 1, JH71XX_PMU_TIMEOUT_US); } else { - ret = readl_poll_timeout_atomic(pmu->base + JH71XX_PMU_CURR_POWER_MODE, - val, !(val & mask), - 1, JH71XX_PMU_TIMEOUT_US); + ret = regmap_read_poll_timeout_atomic(pmu->base, JH71XX_PMU_CURR_POWER_MODE, + val, !(val & mask), + 1, JH71XX_PMU_TIMEOUT_US); } if (ret) { @@ -190,14 +193,14 @@ static void jh71xx_pmu_int_enable(struct jh71xx_pmu *pmu, u32 mask, bool enable) unsigned long flags; spin_lock_irqsave(&pmu->lock, flags); - val = readl(pmu->base + JH71XX_PMU_TIMER_INT_MASK); + regmap_read(pmu->base, JH71XX_PMU_TIMER_INT_MASK, &val); if (enable) val &= ~mask; else val |= mask; - writel(val, pmu->base + JH71XX_PMU_TIMER_INT_MASK); + regmap_write(pmu->base, JH71XX_PMU_TIMER_INT_MASK, val); spin_unlock_irqrestore(&pmu->lock, flags); } @@ -206,7 +209,7 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data) struct jh71xx_pmu *pmu = data; u32 val; - val = readl(pmu->base + JH71XX_PMU_INT_STATUS); + regmap_read(pmu->base, JH71XX_PMU_INT_STATUS, &val); if (val & JH71XX_PMU_INT_SEQ_DONE) dev_dbg(pmu->dev, "sequence done.\n"); @@ -220,8 +223,8 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data) dev_err(pmu->dev, "p-channel fail event.\n"); /* clear interrupts */ - writel(val, pmu->base + JH71XX_PMU_INT_STATUS); - writel(val, pmu->base + JH71XX_PMU_EVENT_STATUS); + regmap_write(pmu->base, JH71XX_PMU_INT_STATUS, val); + regmap_write(pmu->base, JH71XX_PMU_EVENT_STATUS, val); return IRQ_HANDLED; } @@ -271,7 +274,7 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) if (!pmu) return -ENOMEM; - pmu->base = devm_platform_ioremap_resource(pdev, 0); + pmu->base = device_node_to_regmap(np); if (IS_ERR(pmu->base)) return PTR_ERR(pmu->base); From patchwork Tue Apr 11 06:47:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 13207123 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1BFF3C7619A for ; Tue, 11 Apr 2023 06:48:50 +0000 (UTC) DKIM-Signature: v=1; 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Tue, 11 Apr 2023 06:48:40 +0000 Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id F336D24E2B9; Tue, 11 Apr 2023 14:47:47 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:48 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:47 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 4/7] soc: starfive: Add pmu type operation Date: Mon, 10 Apr 2023 23:47:40 -0700 Message-ID: <20230411064743.273388-5-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230410_234839_267367_6383A723 X-CRM114-Status: GOOD ( 15.78 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add pmu type, make a distinction between different PMU. Signed-off-by: Changhuang Liang --- drivers/soc/starfive/jh71xx_pmu.c | 55 ++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 16 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c index 306218c83691..98f6849d61de 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -45,6 +45,12 @@ */ #define JH71XX_PMU_TIMEOUT_US 100 +/* pmu type */ +enum pmu_type { + JH71XX_PMU_GENERAL, + JH71XX_PMU_DPHY, +}; + struct jh71xx_domain_info { const char * const name; unsigned int flags; @@ -54,6 +60,7 @@ struct jh71xx_domain_info { struct jh71xx_pmu_match_data { const struct jh71xx_domain_info *domain_info; int num_domains; + u8 pmu_type; }; struct jh71xx_pmu { @@ -75,19 +82,23 @@ struct jh71xx_pmu_dev { static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_on) { struct jh71xx_pmu *pmu = pmd->pmu; + unsigned int offset = 0; unsigned int val; if (!mask) return -EINVAL; - regmap_read(pmu->base, JH71XX_PMU_CURR_POWER_MODE, &val); + if (pmu->match_data->pmu_type == JH71XX_PMU_GENERAL) + offset = JH71XX_PMU_CURR_POWER_MODE; + + regmap_read(pmu->base, offset, &val); *is_on = val & mask; return 0; } -static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) +static int jh71xx_pmu_general_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) { struct jh71xx_pmu *pmu = pmd->pmu; unsigned long flags; @@ -95,22 +106,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) u32 mode; u32 encourage_lo; u32 encourage_hi; - bool is_on; int ret; - ret = jh71xx_pmu_get_state(pmd, mask, &is_on); - if (ret) { - dev_dbg(pmu->dev, "unable to get current state for %s\n", - pmd->genpd.name); - return ret; - } - - if (is_on == on) { - dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", - pmd->genpd.name, on ? "en" : "dis"); - return 0; - } - spin_lock_irqsave(&pmu->lock, flags); /* @@ -169,6 +166,31 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) return 0; } +static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) +{ + struct jh71xx_pmu *pmu = pmd->pmu; + bool is_on; + int ret = 0; + + ret = jh71xx_pmu_get_state(pmd, mask, &is_on); + if (ret) { + dev_dbg(pmu->dev, "unable to get current state for %s\n", + pmd->genpd.name); + return ret; + } + + if (is_on == on) { + dev_dbg(pmu->dev, "pm domain [%s] is already %sable status.\n", + pmd->genpd.name, on ? "en" : "dis"); + return 0; + } + + if (pmu->match_data->pmu_type == JH71XX_PMU_GENERAL) + ret = jh71xx_pmu_general_set_state(pmd, mask, on); + + return ret; +} + static int jh71xx_pmu_on(struct generic_pm_domain *genpd) { struct jh71xx_pmu_dev *pmd = container_of(genpd, @@ -360,6 +382,7 @@ static const struct jh71xx_domain_info jh7110_power_domains[] = { static const struct jh71xx_pmu_match_data jh7110_pmu = { .num_domains = ARRAY_SIZE(jh7110_power_domains), .domain_info = jh7110_power_domains, + .pmu_type = JH71XX_PMU_GENERAL, }; static const struct of_device_id jh71xx_pmu_of_match[] = { From patchwork Tue Apr 11 06:47:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 13207116 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CE6BBC7619A for ; Tue, 11 Apr 2023 06:48:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=w86jatbMGA5wMtYxkzr++gnQNO7vz00pgL6+8MTeKK0=; b=QsYA48V46y06WV zjOSxHKx/98u4eqe7OVjCWU3I47oMkPOyh9dnuRQ/NaWj6UwTq6uUzmTJVRZ0Fm/I6yYu1ekISv13 P6020FPYcpQgqC/VWIwA/OxVpnzwYcMyDbvh+P8d5wLzinC6Wtls+8IM1/ebhq5VU0dg+UivCUX22 H8ILbf/N8zEitc9oVthLtLc5rLGrcn6VYeFyowfjz+wZPvty8F/x400EcqSgkEI+Y5N5mJLFYX0yU n6CPHFOOGUms5xSUELbyqQO3GrvB5Vw3Zj3b8F7uZ8i+KVvhCFJ4HRm80QE7sbz2iAEoaTUqQNKm3 IhZzty4GeAT7d7BgHcJg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pm7nr-00GcaA-1n; Tue, 11 Apr 2023 06:48:31 +0000 Received: from ex01.ufhost.com ([61.152.239.75]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pm7nn-00GcQA-20 for linux-riscv@lists.infradead.org; Tue, 11 Apr 2023 06:48:29 +0000 Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id A84DE24E226; Tue, 11 Apr 2023 14:47:48 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:48 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:47 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 5/7] soc: starfive: Use call back to parse device tree resources Date: Mon, 10 Apr 2023 23:47:41 -0700 Message-ID: <20230411064743.273388-6-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230410_234827_989457_622B6C2F X-CRM114-Status: GOOD ( 15.98 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Different compatible parse device tree resources work in different ways. Signed-off-by: Changhuang Liang --- drivers/soc/starfive/jh71xx_pmu.c | 54 ++++++++++++++++++++++--------- 1 file changed, 39 insertions(+), 15 deletions(-) diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c index 98f6849d61de..990db6735c48 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -57,10 +57,14 @@ struct jh71xx_domain_info { u8 bit; }; +struct jh71xx_pmu; + struct jh71xx_pmu_match_data { const struct jh71xx_domain_info *domain_info; int num_domains; u8 pmu_type; + int (*pmu_parse_dt)(struct platform_device *pdev, + struct jh71xx_pmu *pmu); }; struct jh71xx_pmu { @@ -251,6 +255,31 @@ static irqreturn_t jh71xx_pmu_interrupt(int irq, void *data) return IRQ_HANDLED; } +static int jh7110_pmu_general_parse_dt(struct platform_device *pdev, + struct jh71xx_pmu *pmu) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + int ret; + + pmu->base = device_node_to_regmap(np); + if (IS_ERR(pmu->base)) + return PTR_ERR(pmu->base); + + pmu->irq = platform_get_irq(pdev, 0); + if (pmu->irq < 0) + return pmu->irq; + + ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, + 0, pdev->name, pmu); + if (ret) + dev_err(dev, "failed to request irq\n"); + + jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true); + + return 0; +} + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) { struct jh71xx_pmu_dev *pmd; @@ -296,23 +325,20 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) if (!pmu) return -ENOMEM; - pmu->base = device_node_to_regmap(np); - if (IS_ERR(pmu->base)) - return PTR_ERR(pmu->base); - - pmu->irq = platform_get_irq(pdev, 0); - if (pmu->irq < 0) - return pmu->irq; - - ret = devm_request_irq(dev, pmu->irq, jh71xx_pmu_interrupt, - 0, pdev->name, pmu); - if (ret) - dev_err(dev, "failed to request irq\n"); + spin_lock_init(&pmu->lock); match_data = of_device_get_match_data(dev); if (!match_data) return -EINVAL; + if (match_data->pmu_parse_dt) { + ret = match_data->pmu_parse_dt(pdev, pmu); + if (ret) { + dev_err(dev, "failed to parse dt\n"); + return ret; + } + } + pmu->genpd = devm_kcalloc(dev, match_data->num_domains, sizeof(struct generic_pm_domain *), GFP_KERNEL); @@ -332,9 +358,6 @@ static int jh71xx_pmu_probe(struct platform_device *pdev) } } - spin_lock_init(&pmu->lock); - jh71xx_pmu_int_enable(pmu, JH71XX_PMU_INT_ALL_MASK & ~JH71XX_PMU_INT_PCH_FAIL, true); - ret = of_genpd_add_provider_onecell(np, &pmu->genpd_data); if (ret) { dev_err(dev, "failed to register genpd driver: %d\n", ret); @@ -383,6 +406,7 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = { .num_domains = ARRAY_SIZE(jh7110_power_domains), .domain_info = jh7110_power_domains, .pmu_type = JH71XX_PMU_GENERAL, + .pmu_parse_dt = jh7110_pmu_general_parse_dt, }; static const struct of_device_id jh71xx_pmu_of_match[] = { From patchwork Tue Apr 11 06:47:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 13207122 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EC882C77B71 for ; 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Tue, 11 Apr 2023 06:48:32 +0000 Received: from ex01.ufhost.com ([61.152.239.75]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pm7no-00GcQB-02 for linux-riscv@lists.infradead.org; Tue, 11 Apr 2023 06:48:30 +0000 Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 6CD7724E293; Tue, 11 Apr 2023 14:47:49 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:49 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:48 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 6/7] soc: starfive: Add dphy pmu support Date: Mon, 10 Apr 2023 23:47:42 -0700 Message-ID: <20230411064743.273388-7-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230410_234828_351660_89849C95 X-CRM114-Status: GOOD ( 16.56 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add dphy pmu to turn on/off the dphy power switch. Signed-off-by: Changhuang Liang --- MAINTAINERS | 1 + drivers/soc/starfive/jh71xx_pmu.c | 65 +++++++++++++++++++++++++++++++ 2 files changed, 66 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 0b2170e1e4ff..4d958f02403e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19944,6 +19944,7 @@ F: include/dt-bindings/reset/starfive?jh71*.h STARFIVE JH71XX PMU CONTROLLER DRIVER M: Walker Chen +M: Changhuang Liang S: Supported F: Documentation/devicetree/bindings/power/starfive* F: drivers/soc/starfive/jh71xx_pmu.c diff --git a/drivers/soc/starfive/jh71xx_pmu.c b/drivers/soc/starfive/jh71xx_pmu.c index 990db6735c48..d4092ca4dccf 100644 --- a/drivers/soc/starfive/jh71xx_pmu.c +++ b/drivers/soc/starfive/jh71xx_pmu.c @@ -24,6 +24,9 @@ #define JH71XX_PMU_EVENT_STATUS 0x88 #define JH71XX_PMU_INT_STATUS 0x8C +/* DPHY pmu register offset */ +#define JH71XX_PMU_DPHY_SWITCH 0x00 + /* sw encourage cfg */ #define JH71XX_PMU_SW_ENCOURAGE_EN_LO 0x05 #define JH71XX_PMU_SW_ENCOURAGE_EN_HI 0x50 @@ -94,6 +97,8 @@ static int jh71xx_pmu_get_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool *is_o if (pmu->match_data->pmu_type == JH71XX_PMU_GENERAL) offset = JH71XX_PMU_CURR_POWER_MODE; + else if (pmu->match_data->pmu_type == JH71XX_PMU_DPHY) + offset = JH71XX_PMU_DPHY_SWITCH; regmap_read(pmu->base, offset, &val); @@ -170,6 +175,23 @@ static int jh71xx_pmu_general_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bo return 0; } +static int jh71xx_pmu_dphy_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) +{ + struct jh71xx_pmu *pmu = pmd->pmu; + unsigned long flags; + + spin_lock_irqsave(&pmu->lock, flags); + + if (on) + regmap_update_bits(pmu->base, JH71XX_PMU_DPHY_SWITCH, mask, mask); + else + regmap_update_bits(pmu->base, JH71XX_PMU_DPHY_SWITCH, mask, 0); + + spin_unlock_irqrestore(&pmu->lock, flags); + + return 0; +} + static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) { struct jh71xx_pmu *pmu = pmd->pmu; @@ -191,6 +213,8 @@ static int jh71xx_pmu_set_state(struct jh71xx_pmu_dev *pmd, u32 mask, bool on) if (pmu->match_data->pmu_type == JH71XX_PMU_GENERAL) ret = jh71xx_pmu_general_set_state(pmd, mask, on); + else if (pmu->match_data->pmu_type == JH71XX_PMU_DPHY) + ret = jh71xx_pmu_dphy_set_state(pmd, mask, on); return ret; } @@ -280,6 +304,25 @@ static int jh7110_pmu_general_parse_dt(struct platform_device *pdev, return 0; } +static int jh7110_pmu_dphy_parse_dt(struct platform_device *pdev, + struct jh71xx_pmu *pmu) +{ + struct device *parent; + struct device *dev = &pdev->dev; + + parent = pdev->dev.parent; + if (!parent) { + dev_err(dev, "No parent for syscon pmu\n"); + return -ENODEV; + } + + pmu->base = syscon_node_to_regmap(parent->of_node); + if (IS_ERR(pmu->base)) + return PTR_ERR(pmu->base); + + return 0; +} + static int jh71xx_pmu_init_domain(struct jh71xx_pmu *pmu, int index) { struct jh71xx_pmu_dev *pmd; @@ -409,10 +452,31 @@ static const struct jh71xx_pmu_match_data jh7110_pmu = { .pmu_parse_dt = jh7110_pmu_general_parse_dt, }; +static const struct jh71xx_domain_info jh7110_dphy_power_domains[] = { + [JH7110_PD_DPHY_TX] = { + .name = "DPHY-TX", + .bit = 30, + }, + [JH7110_PD_DPHY_RX] = { + .name = "DPHY-RX", + .bit = 31, + }, +}; + +static const struct jh71xx_pmu_match_data jh7110_pmu_dphy = { + .num_domains = ARRAY_SIZE(jh7110_dphy_power_domains), + .domain_info = jh7110_dphy_power_domains, + .pmu_type = JH71XX_PMU_DPHY, + .pmu_parse_dt = jh7110_pmu_dphy_parse_dt, +}; + static const struct of_device_id jh71xx_pmu_of_match[] = { { .compatible = "starfive,jh7110-pmu", .data = (void *)&jh7110_pmu, + }, { + .compatible = "starfive,jh7110-pmu-dphy", + .data = (void *)&jh7110_pmu_dphy, }, { /* sentinel */ } @@ -429,5 +493,6 @@ static struct platform_driver jh71xx_pmu_driver = { builtin_platform_driver(jh71xx_pmu_driver); MODULE_AUTHOR("Walker Chen "); +MODULE_AUTHOR("Changhuang Liang "); MODULE_DESCRIPTION("StarFive JH71XX PMU Driver"); MODULE_LICENSE("GPL"); From patchwork Tue Apr 11 06:47:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Changhuang Liang X-Patchwork-Id: 13207117 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1DD25C76196 for ; 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Tue, 11 Apr 2023 06:48:31 +0000 Received: from fd01.gateway.ufhost.com ([61.152.239.71]) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pm7nn-00GcQU-0c for linux-riscv@lists.infradead.org; Tue, 11 Apr 2023 06:48:29 +0000 Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 2915624E2C7; Tue, 11 Apr 2023 14:47:50 +0800 (CST) Received: from EXMBX162.cuchost.com (172.16.6.72) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:50 +0800 Received: from ubuntu.localdomain (113.72.145.176) by EXMBX162.cuchost.com (172.16.6.72) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Tue, 11 Apr 2023 14:47:49 +0800 From: Changhuang Liang To: Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou CC: Walker Chen , Changhuang Liang , , , Subject: [PATCH v1 7/7] riscv: dts: starfive: Add dphy rx pmu node Date: Mon, 10 Apr 2023 23:47:43 -0700 Message-ID: <20230411064743.273388-8-changhuang.liang@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230411064743.273388-1-changhuang.liang@starfivetech.com> References: <20230411064743.273388-1-changhuang.liang@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [113.72.145.176] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX162.cuchost.com (172.16.6.72) X-YovoleRuleAgent: yovoleflag X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230410_234827_404868_31E6AA8C X-CRM114-Status: UNSURE ( 8.05 ) X-CRM114-Notice: Please train this message. X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org Add dphy rx pmu node to configure dphy power. Signed-off-by: Changhuang Liang Reviewed-by: Walker Chen --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index f271c3184d3a..a82374afcc91 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -499,6 +499,11 @@ aoncrg: clock-controller@17000000 { aon_syscon: syscon@17010000 { compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd"; reg = <0x0 0x17010000 0x0 0x1000>; + + pwrc_dphy: power-controller { + compatible = "starfive,jh7110-pmu-dphy"; + #power-domain-cells = <1>; + }; }; aongpio: pinctrl@17020000 {