From patchwork Tue Apr 11 22:29:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13208288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AB908C77B6F for ; Tue, 11 Apr 2023 22:29:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CD74C10E1BD; Tue, 11 Apr 2023 22:29:39 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4EA0710E1BD; Tue, 11 Apr 2023 22:29:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681252177; x=1712788177; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=e16JYrNG13ZK09W8a6cvMfAnKuNMv4L12FVaChTOJe0=; b=h9m2orW1OEZ3joe8KSkyQnjbH+mepwljHKWm/jjmHhBfWpqm8CXCR+xs aiK22SUDzo6NnZtIZNBDdQtw9BlgPaITsa0LL5PMpOuyU9y7oVX77dIFu FK440pTzUVFlkRc1Q8BzzoQ0Xz5Jg110nT8NF5JMt3Qh37YFe9+kwVEwE +9C8QBV0dpClwRU8rq6Zme0MMxnFnK5zobPJ1aKsYJVqo8Est3Ne/CXw1 Mbbwt+dtv/bcrxEty8VdWuO6raYDP2La3P1obYbQPi7cXjKgn3SgA76QP 4rYL2u14FjbvMcwS7TNCMpFVYszOD77lJtmtW2gXirayh35LLj/L4tR4y g==; X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="342506221" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="342506221" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2023 15:29:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="753296797" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="753296797" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga008.fm.intel.com with SMTP; 11 Apr 2023 15:29:35 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Apr 2023 01:29:34 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Apr 2023 01:29:26 +0300 Message-Id: <20230411222931.15127-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411222931.15127-1-ville.syrjala@linux.intel.com> References: <20230411222931.15127-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/uapi: Document CTM matrix better X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Document in which order the CTM matrix elements are stored. Signed-off-by: Ville Syrjälä Reviewed-by: Xaver Hugl Acked-by: Simon Ser --- include/uapi/drm/drm_mode.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/drm/drm_mode.h b/include/uapi/drm/drm_mode.h index 46becedf5b2f..43691058d28f 100644 --- a/include/uapi/drm/drm_mode.h +++ b/include/uapi/drm/drm_mode.h @@ -834,6 +834,11 @@ struct drm_color_ctm { /* * Conversion matrix in S31.32 sign-magnitude * (not two's complement!) format. + * + * out matrix in + * |R| |0 1 2| |R| + * |G| = |3 4 5| x |G| + * |B| |6 7 8| |B| */ __u64 matrix[9]; }; From patchwork Tue Apr 11 22:29:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13208289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id AE7CEC76196 for ; Tue, 11 Apr 2023 22:29:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C411E10E1DB; Tue, 11 Apr 2023 22:29:43 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 454BC10E1D0; Tue, 11 Apr 2023 22:29:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681252180; x=1712788180; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=VO+hzf+JZT0LDwb9AwFVSgz/6tqEyB7SG90J+rO9ms0=; b=VPyn28V8v2XJ1Y3YyJmovgJF0vycrrUIZ9uyHX8dKsoBSfXLVcdSm8QU EfbGaBG6bPvO+QWAjoDAeBiL35/0JaKacyaHolOwmVfKxm+VvZC6RSPy9 12c9n6GEHn28orODkEiXyQih5cWXHBwdNsgg4ucPOHqCudIbDGCh1NBot hFEZpRpxJ4mzLocqi5jDT5XWVHic5RBmd9qaEVZh8Y7FOOXMka2jUAbyQ dPWin0IHAZ+6/i+ixJouZ9mpEL7zJikSOporKia1d5XvHJ0ktuOBR27kX eXXrQ/X8QOIvRRiSW3KqZzWoJCtHFb2PhEqvvMp8Qzo7Nry57qSakCL1c Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="342506235" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="342506235" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2023 15:29:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="753296812" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="753296812" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga008.fm.intel.com with SMTP; 11 Apr 2023 15:29:38 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Apr 2023 01:29:37 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Apr 2023 01:29:27 +0300 Message-Id: <20230411222931.15127-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411222931.15127-1-ville.syrjala@linux.intel.com> References: <20230411222931.15127-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915: Expose crtc CTM property on ilk/snb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The ilk/snb code is internally fully capable of handling the CTM property, so expose it. Note that we still choose not to expose DEGAMMA_LUT though. The hardware is capable if degamma or gamma, but not both similtanously due to lack of the split gamma mode. Exposing both LUTs might encourage userspace to try enabling both at the same time. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 07f1afe1d406..4fc16cac052d 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -3473,7 +3473,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc) gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size; - has_ctm = degamma_lut_size != 0; + has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915); /* * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the From patchwork Tue Apr 11 22:29:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13208292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 749FFC77B6F for ; Tue, 11 Apr 2023 22:29:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BC98C10E6B3; Tue, 11 Apr 2023 22:29:52 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 442C610E1DB; Tue, 11 Apr 2023 22:29:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681252183; x=1712788183; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xt8zT1YZRdFHhWLsgQphruGj5/L9fb/AakwpLz1znqY=; b=dIG8ktJWk12cbIjjsLmB07gEb+Y0qptQTGe6Pyt4qyupHoRNLL/UJ0mB xH2rwQYq/YCRwgj/uZ+GvcFalWFthPvpYYpB9wQ3tFRrWGUZmv/OEczp6 35jnL6gtiQ9gCCEPtzUY+N3+WFiSReJYGKrH9/FL55HGXM27T210PZWIk 8SIlI8iJnGz1Ajc49v2aNjV9JXVUTnTevd1o1UekuH+aV2OHhy4oEB7eW hDsktVe01c9KHWM2Nw1S9cCkjF4nnQ7hdHxKJ8YR/q9ej2TcDsskpzrAB 2smxS+wreM1duW4Toq8oPyGPRkCOJtSFeq9rBnuwX9POZ/1HS2S7PVBx1 g==; X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="342506246" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="342506246" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2023 15:29:43 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="753296821" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="753296821" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga008.fm.intel.com with SMTP; 11 Apr 2023 15:29:41 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Apr 2023 01:29:40 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Apr 2023 01:29:28 +0300 Message-Id: <20230411222931.15127-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411222931.15127-1-ville.syrjala@linux.intel.com> References: <20230411222931.15127-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915: Fix CHV CGM CSC coefficient sign handling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The CHV CGM CSC coefficients are in s4.12 two's complement format. Fix the CTM->CGM conversion to handle that correctly instead of pretending that the hw coefficients are also in some sign-magnitude format. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 46 ++++++++++++++-------- 1 file changed, 29 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 4fc16cac052d..63141f4ed372 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -568,29 +568,41 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state) icl_update_output_csc(crtc, &crtc_state->output_csc); } +static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits) +{ + s64 c = CTM_COEFF_ABS(coeff); + + /* leave an extra bit for rounding */ + c >>= 32 - frac_bits - 1; + + /* round and drop the extra bit */ + c = (c + 1) >> 1; + + if (CTM_COEFF_NEGATIVE(coeff)) + c = -c; + + c = clamp(c, -(s64)BIT(int_bits + frac_bits - 1), + (s64)(BIT(int_bits + frac_bits - 1) - 1)); + + return c & (BIT(int_bits + frac_bits) - 1); +} + +/* + * CHV Color Gamut Mapping (CGM) CSC + * |r| | c0 c1 c2 | |r| + * |g| = | c3 c4 c5 | x |g| + * |b| | c6 c7 c8 | |b| + * + * Coefficients are two's complement s4.12. + */ static void chv_cgm_csc_convert_ctm(const struct intel_crtc_state *crtc_state, struct intel_csc_matrix *csc) { const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; int i; - for (i = 0; i < 9; i++) { - u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i]; - - /* Round coefficient. */ - abs_coeff += 1 << (32 - 13); - /* Clamp to hardware limits. */ - abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1); - - csc->coeff[i] = 0; - - /* Write coefficients in S3.12 format. */ - if (ctm->matrix[i] & (1ULL << 63)) - csc->coeff[i] |= 1 << 15; - - csc->coeff[i] |= ((abs_coeff >> 32) & 7) << 12; - csc->coeff[i] |= (abs_coeff >> 20) & 0xfff; - } + for (i = 0; i < 9; i++) + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 4, 12); } static void chv_load_cgm_csc(struct intel_crtc *crtc, From patchwork Tue Apr 11 22:29:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13208290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30950C7619A for ; Tue, 11 Apr 2023 22:29:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7231D10E69B; Tue, 11 Apr 2023 22:29:49 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3D6DE10E354; Tue, 11 Apr 2023 22:29:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1681252186; x=1712788186; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gLT/Qx8Wzx/TkOdnQieEdUe840DSkIa33QlB+BSmgRs=; b=muZzd+BH5Nw3iD8LhGBOkfXcRekDKHeXnyH+fGcBSme/Xygh5M6sj7UO K5tczd/S5L7M1Sd0P4zVOUHp6yyRlDswT6fOqvI1hSbpEe8+SsqWUOnPT d7kZbD+4WsY3jrcOQ2ui/jDe1N9C+RXIavFe80CVjCjfc5lW0Y7CbBxuI p8tiO+4I/DuIURXbvpuiVhUzQxZcaJL4Ub0uCirRXbb9WgmWh1j/dWwNv pQzD5p5JPC5YIiKL0iNEQMmXlkUQf2l8ummRLr3dloPrAJZ4wUOK5eouI pDhB92VsZD/wq4y7iPTOZztFLlqBHRs4QmIoui96cf1KvPFDDtbgI5U+f g==; X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="342506256" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="342506256" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Apr 2023 15:29:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10677"; a="753296833" X-IronPort-AV: E=Sophos;i="5.98,336,1673942400"; d="scan'208";a="753296833" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by fmsmga008.fm.intel.com with SMTP; 11 Apr 2023 15:29:44 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Apr 2023 01:29:43 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Apr 2023 01:29:29 +0300 Message-Id: <20230411222931.15127-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411222931.15127-1-ville.syrjala@linux.intel.com> References: <20230411222931.15127-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915: Implement CTM property support for VLV X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä VLV has a so called "wide gamut color correction" unit (WGC). What it is is a 3x3 matrix similar to the later CHV CGM CSC, which less precisions/range. In fact CHV also has the WGC but using it there doesn't reall make sense when you have the superior CGM CSC around. Hook up the necessary stuff to expose the WGC as the CTM crtc property. One additional crazy idea that came to mind would be to use the WGC as an output CSC on CHV for YCbCr output. But it would be incompatible with the legacy LUT usage. In fact since the WGC lacks post-offsets we'd probably have to use the legacy LUT to do that final part of the RGB->YCbCr conversion. Sounds doable, but perhaps not worth the hassle. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_color.c | 170 +++++++++++++++++- .../drm/i915/display/intel_crtc_state_dump.c | 6 +- drivers/gpu/drm/i915/display/intel_display.c | 8 + .../drm/i915/display/intel_display_types.h | 3 + drivers/gpu/drm/i915/i915_reg.h | 15 ++ 5 files changed, 198 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index 63141f4ed372..051f86c125e5 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -587,6 +587,98 @@ static u16 ctm_to_twos_complement(u64 coeff, int int_bits, int frac_bits) return c & (BIT(int_bits + frac_bits) - 1); } +/* + * VLV/CHV Wide Gamut Color Correction (WGC) CSC + * |r| | c0 c1 c2 | |r| + * |g| = | c3 c4 c5 | x |g| + * |b| | c6 c7 c8 | |b| + * + * Coefficients are two's complement s2.10. + */ +static void vlv_wgc_csc_convert_ctm(const struct intel_crtc_state *crtc_state, + struct intel_csc_matrix *csc) +{ + const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data; + int i; + + for (i = 0; i < 9; i++) + csc->coeff[i] = ctm_to_twos_complement(ctm->matrix[i], 2, 10); +} + +static void vlv_load_wgc_csc(struct intel_crtc *crtc, + const struct intel_csc_matrix *csc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + + intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe), + csc->coeff[1] << 16 | csc->coeff[0]); + intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe), + csc->coeff[2]); + + intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe), + csc->coeff[4] << 16 | csc->coeff[3]); + intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe), + csc->coeff[5]); + + intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe), + csc->coeff[7] << 16 | csc->coeff[6]); + intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe), + csc->coeff[8]); +} + +static void vlv_read_wgc_csc(struct intel_crtc *crtc, + struct intel_csc_matrix *csc) +{ + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; + u32 tmp; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe)); + csc->coeff[0] = tmp & 0xffff; + csc->coeff[1] = tmp >> 16; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe)); + csc->coeff[2] = tmp & 0xffff; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe)); + csc->coeff[3] = tmp & 0xffff; + csc->coeff[4] = tmp >> 16; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe)); + csc->coeff[5] = tmp & 0xffff; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe)); + csc->coeff[6] = tmp & 0xffff; + csc->coeff[7] = tmp >> 16; + + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe)); + csc->coeff[8] = tmp & 0xffff; +} + +static void vlv_read_csc(struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if (crtc_state->wgc_enable) + vlv_read_wgc_csc(crtc, &crtc_state->csc); +} + +static void vlv_assign_csc(struct intel_crtc_state *crtc_state) +{ + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + + if (crtc_state->hw.ctm) { + drm_WARN_ON(&i915->drm, !crtc_state->wgc_enable); + + vlv_wgc_csc_convert_ctm(crtc_state, &crtc_state->csc); + } else { + drm_WARN_ON(&i915->drm, crtc_state->wgc_enable); + + intel_csc_clear(&crtc_state->csc); + } +} + /* * CHV Color Gamut Mapping (CGM) CSC * |r| | c0 c1 c2 | |r| @@ -662,6 +754,8 @@ static void chv_assign_csc(struct intel_crtc_state *crtc_state) { struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); + drm_WARN_ON(&i915->drm, crtc_state->wgc_enable); + if (crtc_state->hw.ctm) { drm_WARN_ON(&i915->drm, (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC) == 0); @@ -1564,6 +1658,16 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state) } } +static void vlv_load_luts(const struct intel_crtc_state *crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + + if (crtc_state->wgc_enable) + vlv_load_wgc_csc(crtc, &crtc_state->csc); + + i965_load_luts(crtc_state); +} + static u32 chv_cgm_degamma_ldw(const struct drm_color_lut *color) { return REG_FIELD_PREP(CGM_PIPE_DEGAMMA_GREEN_LDW_MASK, drm_color_lut_extract(color->green, 14)) | @@ -1718,6 +1822,18 @@ static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state !old_crtc_state->pre_csc_lut; } +static bool vlv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) +{ + struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); + struct intel_atomic_state *state = + to_intel_atomic_state(new_crtc_state->uapi.state); + const struct intel_crtc_state *old_crtc_state = + intel_atomic_get_old_crtc_state(state, crtc); + + return !old_crtc_state->wgc_enable && + !old_crtc_state->post_csc_lut; +} + static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) { struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc); @@ -1734,7 +1850,7 @@ static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state) if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode) return false; - return !old_crtc_state->post_csc_lut; + return vlv_can_preload_luts(new_crtc_state); } int intel_color_check(struct intel_crtc_state *crtc_state) @@ -2021,6 +2137,39 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state) return 0; } +/* + * VLV color pipeline: + * u0.10 -> WGC csc -> u0.10 -> pipe gamma -> u0.10 + */ +static int vlv_color_check(struct intel_crtc_state *crtc_state) +{ + int ret; + + ret = check_luts(crtc_state); + if (ret) + return ret; + + crtc_state->gamma_enable = + crtc_state->hw.gamma_lut && + !crtc_state->c8_planes; + + crtc_state->gamma_mode = i9xx_gamma_mode(crtc_state); + + crtc_state->wgc_enable = crtc_state->hw.ctm; + + ret = intel_color_add_affected_planes(crtc_state); + if (ret) + return ret; + + intel_assign_luts(crtc_state); + + vlv_assign_csc(crtc_state); + + crtc_state->preload_luts = vlv_can_preload_luts(crtc_state); + + return 0; +} + static u32 chv_cgm_mode(const struct intel_crtc_state *crtc_state) { u32 cgm_mode = 0; @@ -2064,6 +2213,12 @@ static int chv_color_check(struct intel_crtc_state *crtc_state) crtc_state->cgm_mode = chv_cgm_mode(crtc_state); + /* + * We always bypass the WGC CSC and use the CGM CSC + * instead since it has degamma and better precision. + */ + crtc_state->wgc_enable = false; + ret = intel_color_add_affected_planes(crtc_state); if (ret) return ret; @@ -3378,6 +3533,15 @@ static const struct intel_color_funcs chv_color_funcs = { .read_csc = chv_read_csc, }; +static const struct intel_color_funcs vlv_color_funcs = { + .color_check = vlv_color_check, + .color_commit_arm = i9xx_color_commit_arm, + .load_luts = vlv_load_luts, + .read_luts = i965_read_luts, + .lut_equal = i965_lut_equal, + .read_csc = vlv_read_csc, +}; + static const struct intel_color_funcs i965_color_funcs = { .color_check = i9xx_color_check, .color_commit_arm = i9xx_color_commit_arm, @@ -3485,7 +3649,7 @@ void intel_color_crtc_init(struct intel_crtc *crtc) gamma_lut_size = INTEL_INFO(i915)->display.color.gamma_lut_size; degamma_lut_size = INTEL_INFO(i915)->display.color.degamma_lut_size; - has_ctm = DISPLAY_VER(i915) >= 5 && !IS_VALLEYVIEW(i915); + has_ctm = DISPLAY_VER(i915) >= 5; /* * "DPALETTE_A: NOTE: The 8-bit (non-10-bit) mode is the @@ -3523,6 +3687,8 @@ void intel_color_init_hooks(struct drm_i915_private *i915) if (HAS_GMCH(i915)) { if (IS_CHERRYVIEW(i915)) i915->display.funcs.color = &chv_color_funcs; + else if (IS_VALLEYVIEW(i915)) + i915->display.funcs.color = &vlv_color_funcs; else if (DISPLAY_VER(i915) >= 4) i915->display.funcs.color = &i965_color_funcs; else diff --git a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c index 0cdcaa49656f..dd0895b24682 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c +++ b/drivers/gpu/drm/i915/display/intel_crtc_state_dump.c @@ -184,7 +184,7 @@ ilk_dump_csc(struct drm_i915_private *i915, const char *name, } static void -chv_dump_csc(struct drm_i915_private *i915, const char *name, +vlv_dump_csc(struct drm_i915_private *i915, const char *name, const struct intel_csc_matrix *csc) { int i; @@ -370,7 +370,9 @@ void intel_crtc_state_dump(const struct intel_crtc_state *pipe_config, if (!HAS_GMCH(i915)) ilk_dump_csc(i915, "pipe csc", &pipe_config->csc); else if (IS_CHERRYVIEW(i915)) - chv_dump_csc(i915, "cgm csc", &pipe_config->csc); + vlv_dump_csc(i915, "cgm csc", &pipe_config->csc); + else if (IS_VALLEYVIEW(i915)) + vlv_dump_csc(i915, "wgc csc", &pipe_config->csc); dump_planes: if (!state) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index e6f8f2d585f4..ce781ccff43c 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -2904,6 +2904,9 @@ void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state) val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode); + if (crtc_state->wgc_enable) + val |= TRANSCONF_WGC_ENABLE; + val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1); intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val); @@ -3096,6 +3099,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc, pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1; + if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && + (tmp & TRANSCONF_WGC_ENABLE)) + pipe_config->wgc_enable = true; + if (IS_CHERRYVIEW(dev_priv)) pipe_config->cgm_mode = intel_de_read(dev_priv, CGM_PIPE_MODE(crtc->pipe)); @@ -5681,6 +5688,7 @@ intel_pipe_config_compare(const struct intel_crtc_state *current_config, PIPE_CONF_CHECK_X(csc_mode); PIPE_CONF_CHECK_BOOL(gamma_enable); PIPE_CONF_CHECK_BOOL(csc_enable); + PIPE_CONF_CHECK_BOOL(wgc_enable); PIPE_CONF_CHECK_I(linetime); PIPE_CONF_CHECK_I(ips_linetime); diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index ed02399ee41d..42aa02f64e63 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1292,6 +1292,9 @@ struct intel_crtc_state { /* enable pipe csc? */ bool csc_enable; + /* enable vlv/chv wgc csc? */ + bool wgc_enable; + /* big joiner pipe bitmask */ u8 bigjoiner_pipes; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 736a8dcf777b..a677f43c4baa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2550,6 +2550,7 @@ #define TRANSCONF_MSA_TIMING_DELAY_MASK REG_GENMASK(19, 18) /* ilk/snb/ivb */ #define TRANSCONF_MSA_TIMING_DELAY(x) REG_FIELD_PREP(TRANSCONF_MSA_TIMING_DELAY_MASK, (x)) #define TRANSCONF_CXSR_DOWNCLOCK REG_BIT(16) +#define TRANSCONF_WGC_ENABLE REG_BIT(15) /* vlv/chv only */ #define TRANSCONF_REFRESH_RATE_ALT_VLV REG_BIT(14) #define TRANSCONF_COLOR_RANGE_SELECT REG_BIT(13) #define TRANSCONF_OUTPUT_COLORSPACE_MASK REG_GENMASK(12, 11) /* ilk-ivb */ @@ -6383,6 +6384,20 @@ enum skl_power_gate { (index) * 4, _PLANE_CSC_POSTOFF_HI_2(pipe) + \ (index) * 4) +#define _PIPE_A_WGC_C01_C00 0x600B0 /* s2.10 */ +#define _PIPE_A_WGC_C02 0x600B4 /* s2.10 */ +#define _PIPE_A_WGC_C11_C10 0x600B8 /* s2.10 */ +#define _PIPE_A_WGC_C12 0x600BC /* s2.10 */ +#define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */ +#define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */ + +#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00) +#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02) +#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10) +#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12) +#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20) +#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22) + /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) #define _CGM_PIPE_A_CSC_COEFF23 (VLV_DISPLAY_BASE + 0x67904) From patchwork Tue Apr 11 22:29:30 2023 Content-Type: text/plain; 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11 Apr 2023 15:29:47 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Apr 2023 01:29:46 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Apr 2023 01:29:30 +0300 Message-Id: <20230411222931.15127-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411222931.15127-1-ville.syrjala@linux.intel.com> References: <20230411222931.15127-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] drm/i915: No 10bit gamma on desktop gen3 parts X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Apparently desktop gen3 parts don't support the 10bit gamma mode at all. Stop claiming otherwise. As is the case with pipe A on gen3 mobile parts, the PIPECONF gamma mode bit can be set but it has no effect on the output. PNV seems to be the only slight exception, but generally the desktop PNV variant looks more like a mobile part so this is not entirely surprising. Fixes: 67630bacae23 ("drm/i915: Add 10bit gamma mode for gen2/3") Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_pci.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index cddb6e197972..305c05c3f93b 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -250,13 +250,13 @@ static const struct intel_device_info i865g_info = { .dma_mask_size = 32, \ I9XX_PIPE_OFFSETS, \ I9XX_CURSOR_OFFSETS, \ - I9XX_COLORS, \ GEN_DEFAULT_PAGE_SIZES, \ GEN_DEFAULT_REGIONS static const struct intel_device_info i915g_info = { GEN3_FEATURES, PLATFORM(INTEL_I915G), + I845_COLORS, .has_coherent_ggtt = false, .display.cursor_needs_physical = 1, .display.has_overlay = 1, @@ -268,6 +268,7 @@ static const struct intel_device_info i915g_info = { static const struct intel_device_info i915gm_info = { GEN3_FEATURES, PLATFORM(INTEL_I915GM), + I9XX_COLORS, .is_mobile = 1, .display.cursor_needs_physical = 1, .display.has_overlay = 1, @@ -281,6 +282,7 @@ static const struct intel_device_info i915gm_info = { static const struct intel_device_info i945g_info = { GEN3_FEATURES, PLATFORM(INTEL_I945G), + I845_COLORS, .display.has_hotplug = 1, .display.cursor_needs_physical = 1, .display.has_overlay = 1, @@ -292,6 +294,7 @@ static const struct intel_device_info i945g_info = { static const struct intel_device_info i945gm_info = { GEN3_FEATURES, PLATFORM(INTEL_I945GM), + I9XX_COLORS, .is_mobile = 1, .display.has_hotplug = 1, .display.cursor_needs_physical = 1, @@ -306,6 +309,7 @@ static const struct intel_device_info i945gm_info = { static const struct intel_device_info g33_info = { GEN3_FEATURES, PLATFORM(INTEL_G33), + I845_COLORS, .display.has_hotplug = 1, .display.has_overlay = 1, .dma_mask_size = 36, @@ -314,6 +318,7 @@ static const struct intel_device_info g33_info = { static const struct intel_device_info pnv_g_info = { GEN3_FEATURES, PLATFORM(INTEL_PINEVIEW), + I9XX_COLORS, .display.has_hotplug = 1, .display.has_overlay = 1, .dma_mask_size = 36, @@ -322,6 +327,7 @@ static const struct intel_device_info pnv_g_info = { static const struct intel_device_info pnv_m_info = { GEN3_FEATURES, PLATFORM(INTEL_PINEVIEW), + I9XX_COLORS, .is_mobile = 1, .display.has_hotplug = 1, .display.has_overlay = 1, From patchwork Tue Apr 11 22:29:31 2023 Content-Type: text/plain; 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11 Apr 2023 15:29:50 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 12 Apr 2023 01:29:49 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Wed, 12 Apr 2023 01:29:31 +0300 Message-Id: <20230411222931.15127-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230411222931.15127-1-ville.syrjala@linux.intel.com> References: <20230411222931.15127-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915: Do state check for color management changes X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: dri-devel@lists.freedesktop.org Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In order to validate LUT programming more thoroughly let's do a state check for all color management updates as well. Not sure we really want this outside CI. It is rather heavy and color management updates could become rather common with all the HDR/etc. stuff happening. Maybe we should have an extra knob for this that we could enable in CI? v2: Skip for initial_commit to avoid FDI dotclock sanity checks/etc. tripping up Reviewed-by: Uma Shankar Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_modeset_verify.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_modeset_verify.c b/drivers/gpu/drm/i915/display/intel_modeset_verify.c index 842d70f0dfd2..9e4767e1b900 100644 --- a/drivers/gpu/drm/i915/display/intel_modeset_verify.c +++ b/drivers/gpu/drm/i915/display/intel_modeset_verify.c @@ -228,6 +228,8 @@ void intel_modeset_verify_crtc(struct intel_crtc *crtc, struct intel_crtc_state *new_crtc_state) { if (!intel_crtc_needs_modeset(new_crtc_state) && + (!intel_crtc_needs_color_update(new_crtc_state) || + new_crtc_state->inherited) && !intel_crtc_needs_fastset(new_crtc_state)) return;