From patchwork Wed Apr 12 19:09:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13209432 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0FAAAC77B73 for ; Wed, 12 Apr 2023 19:10:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229670AbjDLTKJ (ORCPT ); Wed, 12 Apr 2023 15:10:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229705AbjDLTKH (ORCPT ); Wed, 12 Apr 2023 15:10:07 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2C44559F9 for ; Wed, 12 Apr 2023 12:10:05 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33CFsBEI013320; Wed, 12 Apr 2023 19:10:00 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=3TtQI71qOtd0TPp8bKUIe236bd/m09m5U4WSmTk54UQ=; b=gXDon69/wD0AegV8fLPqXP2bEMmifbi8VVhhybDiM5nLf3VwwHaHEo2IGOLLl9QnM4ZT e1NXIepnFEnvE4dDjyyRhl0Nq2EhJjSbWJE1KRm8A1QiguyPFSkevbX/oJ1wwYH3kgg7 aB4jwexxFjWRLX0xvsGC9zH3TDtROS+HrqAx3DBBjy8RSIZOJ1aaznyC28KtcZcE4mRR dzyjQVI4Qf9cZPOkQJdJL355jSC8hXQ1v6gly1VcAVLxAFpBQm9pZ71C0LWdFTmcpAQF bP5QsY3sNZTpPrSRHcVuFokBGgFWFW+FIzXESON9cLKF5b3Oph0ujHmUxzYyybgfDv+u YA== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3pwhhta9xb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Apr 2023 19:09:58 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 33CJ9vJe007431 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 12 Apr 2023 19:09:57 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 12 Apr 2023 12:09:56 -0700 From: Jessica Zhang Date: Wed, 12 Apr 2023 12:09:41 -0700 Subject: [PATCH v5 1/8] drm/msm/dsi: use new helpers for DSC setup MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v5-1-0108401d7886@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681326596; l=3366; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=a9VLK0oDQDcazg574rSjL3TYAMyzlM0hGgHg/0yl67M=; b=T1UP+BE2V0AmAu4D2xIFXUzO+SOm3axdjUSSffuvL05Nos/yJTm4ty1+EY90JzXnufLs77yAF EYgJNIPtFY5A7Vu6cOvXUkbIs/vZk4fIRir6mSAh+n5tAogt3MuZobs X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TxO9U4Z3QMBY1IUOzuYeZiaCjGd9zpPp X-Proofpoint-ORIG-GUID: TxO9U4Z3QMBY1IUOzuYeZiaCjGd9zpPp X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-12_10,2023-04-12_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 adultscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 bulkscore=0 phishscore=0 mlxscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304120164 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Dmitry Baryshkov Use new DRM DSC helpers to setup DSI DSC configuration. The initial_scale_value needs to be adjusted according to the standard, but this is a separate change. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 61 +++++--------------------------------- 1 file changed, 8 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 961689a255c4..74d38f90398a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1731,28 +1731,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, return -EINVAL; } -static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { - 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, - 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e -}; - -/* only 8bpc, 8bpp added */ -static char min_qp[DSC_NUM_BUF_RANGES] = { - 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 -}; - -static char max_qp[DSC_NUM_BUF_RANGES] = { - 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 -}; - -static char bpg_offset[DSC_NUM_BUF_RANGES] = { - 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 -}; - static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) { - int i; - u16 bpp = dsc->bits_per_pixel >> 4; + int ret; if (dsc->bits_per_pixel & 0xf) { DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); @@ -1764,49 +1745,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc return -EOPNOTSUPP; } - dsc->rc_model_size = 8192; - dsc->first_line_bpg_offset = 12; - dsc->rc_edge_factor = 6; - dsc->rc_tgt_offset_high = 3; - dsc->rc_tgt_offset_low = 3; dsc->simple_422 = 0; dsc->convert_rgb = 1; dsc->vbr_enable = 0; - /* handle only bpp = bpc = 8 */ - for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) - dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; + drm_dsc_set_const_params(dsc); + drm_dsc_set_rc_buf_thresh(dsc); - for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { - dsc->rc_range_params[i].range_min_qp = min_qp[i]; - dsc->rc_range_params[i].range_max_qp = max_qp[i]; - /* - * Range BPG Offset contains two's-complement signed values that fill - * 8 bits, yet the registers and DCS PPS field are only 6 bits wide. - */ - dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK; + /* handle only bpp = bpc = 8, pre-SCR panels */ + ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); + if (ret) { + DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); + return ret; } - dsc->initial_offset = 6144; /* Not bpp 12 */ - if (bpp != 8) - dsc->initial_offset = 2048; /* bpp = 12 */ - - if (dsc->bits_per_component <= 10) - dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; - else - dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; - - dsc->initial_xmit_delay = 512; dsc->initial_scale_value = 32; - dsc->first_line_bpg_offset = 12; dsc->line_buf_depth = dsc->bits_per_component + 1; - /* bpc 8 */ - dsc->flatness_min_qp = 3; - dsc->flatness_max_qp = 12; - dsc->rc_quant_incr_limit0 = 11; - dsc->rc_quant_incr_limit1 = 11; - return drm_dsc_compute_rc_parameters(dsc); } From patchwork Wed Apr 12 19:09:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13209430 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 78076C77B71 for ; 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Wed, 12 Apr 2023 12:09:57 -0700 From: Jessica Zhang Date: Wed, 12 Apr 2023 12:09:42 -0700 Subject: [PATCH v5 2/8] drm/msm: Add MSM-specific DSC helper methods MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v5-2-0108401d7886@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681326596; l=5978; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=eQLXDjK5g2aJtDuDqGyF02RFPdGyEd60vIVs6rDo4Nk=; b=HzaQinm0dOh8ori1bjR9UiDfkdSzW/omvwX4bX+zR9vn+Ax7G9RDa/qz8oUPXzqO+046ow/Ny Pz8DVOgfQ7XBnFD1KjxgdKsrKdvk9AOOKbYBXubEf2a2LsV+gt1KNsc X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: NDJwY_oAz7-wRmJoqqDbM9dQBhpWZppf X-Proofpoint-GUID: NDJwY_oAz7-wRmJoqqDbM9dQBhpWZppf X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-12_10,2023-04-12_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxlogscore=614 spamscore=0 clxscore=1015 impostorscore=0 suspectscore=0 malwarescore=0 phishscore=0 mlxscore=0 lowpriorityscore=0 bulkscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304120164 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce MSM-specific DSC helper methods, as some calculations are common between DP and DSC. Changes in v2: - Moved files up to msm/ directory - Dropped get_comp_ratio() helper - Used drm_int2fixp() to convert to integers to fp - Style changes to improve readability - Dropped unused bpp variable in msm_dsc_get_dce_bytes_per_line() - Changed msm_dsc_get_slice_per_intf() to a static inline method - Dropped last division step of msm_dsc_get_pclk_per_line() and changed method name accordingly - Changed DSC_BPP macro to drm_dsc_get_bpp_int() helper method - Fixed some math issues caused by passing in incorrect types to drm_fixed methods in get_bytes_per_soft_slice() Changes in v3: - Dropped src_bpp parameter from all methods -- src_bpp can be calculated as dsc->bits_per_component * 3 - Dropped intf_width parameter from get_bytes_per_soft_slice() - Moved dsc->bits_per_component to numerator calculation in get_bytes_per_soft_slice() - Renamed msm_dsc_get_uncompressed_pclk_per_line to *_get_uncompressed_pclk_per_intf() - Removed dsc->slice_width check from msm_dsc_get_uncompressed_pclk_per_intf() - Made get_bytes_per_soft_slice() a public method (this will be called later to help calculate DP pclk params) - Added documentation in comments - Moved extra_eol_bytes math out of msm_dsc_get_eol_byte_num() and renamed msm_dsc_get_eol_byte_num to *_get_bytes_per_intf. Changes in v4: - Changed msm_dsc_get_uncompressed_pclk_per_intf to msm_dsc_get_pclk_per_intf Changes in v5: - Added extra line at end of msm_dsc_helper.h - Simplified msm_dsc_get_bytes_per_soft_slice() math - Simplified and inlined msm_dsc_get_pclk_per_intf() math - Removed unused headers Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/msm_dsc_helper.c | 25 ++++++++++++ drivers/gpu/drm/msm/msm_dsc_helper.h | 75 ++++++++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7274c41228ed..b814fc80e2d5 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -94,6 +94,7 @@ msm-y += \ msm_atomic_tracepoints.o \ msm_debugfs.o \ msm_drv.o \ + msm_dsc_helper.o \ msm_fb.o \ msm_fence.o \ msm_gem.o \ diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.c b/drivers/gpu/drm/msm/msm_dsc_helper.c new file mode 100644 index 000000000000..a34614b8e131 --- /dev/null +++ b/drivers/gpu/drm/msm/msm_dsc_helper.c @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#include + +#include "msm_dsc_helper.h" + +s64 msm_dsc_get_bytes_per_soft_slice(struct drm_dsc_config *dsc) +{ + return drm_fixp_from_fraction(dsc->slice_width * msm_dsc_get_bpp_int(dsc), 8); +} + +u32 msm_dsc_get_bytes_per_intf(struct drm_dsc_config *dsc, int intf_width) +{ + u32 bytes_per_soft_slice; + s64 bytes_per_soft_slice_fp; + int slice_per_intf = msm_dsc_get_slice_per_intf(dsc, intf_width); + + bytes_per_soft_slice_fp = msm_dsc_get_bytes_per_soft_slice(dsc); + bytes_per_soft_slice = drm_fixp2int_ceil(bytes_per_soft_slice_fp); + + return bytes_per_soft_slice * slice_per_intf; +} diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.h b/drivers/gpu/drm/msm/msm_dsc_helper.h new file mode 100644 index 000000000000..34238153ffdf --- /dev/null +++ b/drivers/gpu/drm/msm/msm_dsc_helper.h @@ -0,0 +1,75 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#ifndef MSM_DSC_HELPER_H_ +#define MSM_DSC_HELPER_H_ + +#include +#include +#include + +/* + * Helper methods for MSM specific DSC calculations that are common between timing engine, + * DSI, and DP. + */ + +/** + * msm_dsc_get_bpp_int - get bits per pixel integer value + * @dsc: Pointer to drm dsc config struct + */ +static inline int msm_dsc_get_bpp_int(struct drm_dsc_config *dsc) +{ + WARN_ON_ONCE(dsc->bits_per_pixel & 0xf); + return dsc->bits_per_pixel >> 4; +} + +/** + * msm_dsc_get_slice_per_intf - get number of slices per interface + * @dsc: Pointer to drm dsc config struct + * @intf_width: interface width + */ +static inline int msm_dsc_get_slice_per_intf(struct drm_dsc_config *dsc, int intf_width) +{ + return DIV_ROUND_UP(intf_width, dsc->slice_width); +} + +/** + * msm_dsc_get_dce_bytes_per_line - get bytes per line to help calculate data width + * when configuring the timing engine + * @dsc: Pointer to drm dsc config struct + * @intf_width: interface width + */ +static inline u32 msm_dsc_get_dce_bytes_per_line(struct drm_dsc_config *dsc, int intf_width) +{ + return DIV_ROUND_UP(msm_dsc_get_bpp_int(dsc) * intf_width, 8); +} + +/** + * msm_dsc_get_pclk_per_intf - Calculate pclk per interface. + * @dsc: Pointer to drm dsc config struct + * + * Note: This value will then be passed along to DSI and DP for some more + * calculations. This is because DSI and DP divide the pclk_per_intf value + * by different values depending on if widebus is enabled. + */ +static inline int msm_dsc_get_pclk_per_intf(struct drm_dsc_config *dsc) +{ + return DIV_ROUND_UP(dsc->slice_width * dsc->slice_count * msm_dsc_get_bpp_int(dsc), 8); +} + +/** + * msm_dsc_get_bytes_per_soft_slice - get size of each soft slice for dsc + * @dsc: Pointer to drm dsc config struct + */ +s64 msm_dsc_get_bytes_per_soft_slice(struct drm_dsc_config *dsc); + +/** + * msm_dsc_get_bytes_per_intf - get total bytes per interface + * @dsc: Pointer to drm dsc config struct + * @intf_width: interface width + */ +u32 msm_dsc_get_bytes_per_intf(struct drm_dsc_config *dsc, int intf_width); + +#endif /* MSM_DSC_HELPER_H_ */ From patchwork Wed Apr 12 19:09:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13209429 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 696D4C77B77 for ; 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Wed, 12 Apr 2023 12:09:57 -0700 From: Jessica Zhang Date: Wed, 12 Apr 2023 12:09:43 -0700 Subject: [PATCH v5 3/8] drm/msm/dpu: Use DRM DSC helper for det_thresh_flatness MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v5-3-0108401d7886@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681326596; l=1282; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=miwaTqKJX3w3HDahg7jImz20J6rL9IpfTJm6EPOS6AI=; b=xCtJ9Xu3A+934ZwrzC2mghTIV4WKmHh85f+0ZSqL+I59UidS1dRW9+ALQ7Ot17Za1m5aezLGo JSKaKXgi6qoD1yddO+xr2Bbg4e5Kz7IVFzEVT2kJUoKE2r6+p/u6gig X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: vjfmUG0kuefpMh8B91K_hMCPoV1t8k_D X-Proofpoint-ORIG-GUID: vjfmUG0kuefpMh8B91K_hMCPoV1t8k_D X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-12_10,2023-04-12_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 priorityscore=1501 mlxlogscore=712 suspectscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304120164 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Use the DRM DSC helper for det_thresh_flatness to match downstream implementation and the DSC spec. Changes in V2: - Added a Fixes tag Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 619926da1441..b952f7d2b7f5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -3,6 +3,8 @@ * Copyright (c) 2020-2022, Linaro Limited */ +#include + #include "dpu_kms.h" #include "dpu_hw_catalog.h" #include "dpu_hwio.h" @@ -102,7 +104,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, data |= dsc->final_offset; DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); - det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8); + det_thresh_flatness = drm_dsc_calculate_flatness_det_thresh(dsc); data = det_thresh_flatness << 10; data |= dsc->flatness_max_qp << 5; data |= dsc->flatness_min_qp; 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Changes in v3: - Reworded slice_last_group_size calculation to `(dsc->slice_width + 2) % 3` Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index b952f7d2b7f5..ff1c8f92fb20 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -56,9 +56,10 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, if (is_cmd_mode) initial_lines += 1; - slice_last_group_size = 3 - (dsc->slice_width % 3); + slice_last_group_size = (dsc->slice_width + 2) % 3; + data = (initial_lines << 20); - data |= ((slice_last_group_size - 1) << 18); + data |= (slice_last_group_size << 18); /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ data |= (dsc->bits_per_pixel << 8); data |= (dsc->block_pred_enable << 7); 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Wed, 12 Apr 2023 19:09:58 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 12 Apr 2023 12:09:58 -0700 From: Jessica Zhang Date: Wed, 12 Apr 2023 12:09:45 -0700 Subject: [PATCH v5 5/8] drm/msm/dsi: Use MSM and DRM DSC helper methods MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v5-5-0108401d7886@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681326596; l=2243; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=9uQ4e/K+pbk9toY8K4dLpO654/bqIQJwjQqbmnNDKMI=; b=6mdZU6sZPC7E8vmNIN71SgrHYoVclILRuUiJb+qJ6mXEJ3gV0LBAYJPgi0yY1D5dwOz4RjLlw RXeG7IcROUPAtJ44lIq/xTbKPnly874EjkO+zGohR9m+o7oWaQm3MvH X-Developer-Key: i=quic_jesszhan@quicinc.com; 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Changes in v2: - *_calculate_initial_scale_value --> *_set_initial_scale_value - Split pkt_per_line and eol_byte_num changes to a separate patch - Moved pclk_per_line calculation to hdisplay adjustment in `if (dsc)` block of dsi_update_dsc_timing() Changes in v3: - Split pclk_per_intf calculation into a separate patch - Added slice_width check to dsi_timing_setup - Used MSM DSC helper to calculate total_bytes_per_intf Changes in v5: - Split slice_width check into a separate patch Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 74d38f90398a..508577c596ff 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -28,6 +28,7 @@ #include "dsi.xml.h" #include "sfpb.xml.h" #include "dsi_cfg.h" +#include "msm_dsc_helper.h" #include "msm_kms.h" #include "msm_gem.h" #include "phy/dsi_phy.h" @@ -848,7 +849,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* first calculate dsc parameters and then program * compress mode registers */ - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); + slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay); /* * If slice_count is greater than slice_per_intf @@ -858,7 +859,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod if (dsc->slice_count > slice_per_intf) dsc->slice_count = 1; - total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; + total_bytes_per_intf = msm_dsc_get_bytes_per_intf(dsc, hdisplay); eol_byte_num = total_bytes_per_intf % 3; pkt_per_line = slice_per_intf / dsc->slice_count; @@ -1759,7 +1760,7 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc return ret; } - dsc->initial_scale_value = 32; + drm_dsc_set_initial_scale_value(dsc); dsc->line_buf_depth = dsc->bits_per_component + 1; return drm_dsc_compute_rc_parameters(dsc); From patchwork Wed Apr 12 19:09:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13209427 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0FE2C77B6E for ; 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Wed, 12 Apr 2023 12:09:58 -0700 From: Jessica Zhang Date: Wed, 12 Apr 2023 12:09:46 -0700 Subject: [PATCH v5 6/8] drm/msm/dsi: Add check for slice_width in dsi_timing_setup MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v5-6-0108401d7886@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681326596; l=897; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=4GjhaxvpbpnL7eWJFnssOJBgp66Wxc5nKWxfy3b8/m0=; b=F6AbROXP4nA0mS0ZPNpT7s8RTiWjxAk5GMzbJEtVJpOjwW+2lfAfb10fW3y7SmDcTrzVb/9Ok mRJvSq/CJKyDFLjfH3oO/+/bAS36RNRotsfwch1fAkSMSSJU6K+9x8h X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: oy2-qvsLTXxzJ6dJvPnzB9qSJj0coAhI X-Proofpoint-ORIG-GUID: oy2-qvsLTXxzJ6dJvPnzB9qSJj0coAhI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-12_10,2023-04-12_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxscore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 malwarescore=0 bulkscore=0 priorityscore=1501 mlxlogscore=657 suspectscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304120164 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a check for valid dsc->slice_width value in dsi_timing_setup. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi_host.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 508577c596ff..6a6218a9655f 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -937,6 +937,12 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) return; } + if (!dsc->slice_width || (mode->hdisplay < dsc->slice_width)) { + pr_err("DSI: invalid slice width %d (pic_width: %d)\n", + dsc->slice_width, mode->hdisplay); + return; + } + dsc->pic_width = mode->hdisplay; dsc->pic_height = mode->vdisplay; DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); From patchwork Wed Apr 12 19:09:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13209433 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D9A3C7619A for ; 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Wed, 12 Apr 2023 12:09:58 -0700 From: Jessica Zhang Date: Wed, 12 Apr 2023 12:09:47 -0700 Subject: [PATCH v5 7/8] drm/msm/dsi: update hdisplay calculation for dsi_timing_setup MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v5-7-0108401d7886@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681326596; l=1208; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=5bRFk4n3/vQ/y+nHUAZ+k8i89vWEjvXIyCUkD76Tvto=; b=b8elRml6TrWSJ9bBBgHRcWAyIk58Tf1rXWT39DFgb9yC/JpF7CWvD9zCzE8dzdywuQE+0cnW3 15D7Rw07hyXAHXo2DmtnXXOiROEiZAA1l2dIz4tOI4XxmGEdGw+7Xc6 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: DfbDs38wRWZg66nfsbLKHf-rXCdypoG3 X-Proofpoint-GUID: DfbDs38wRWZg66nfsbLKHf-rXCdypoG3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-12_10,2023-04-12_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 mlxlogscore=943 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304120164 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org hdisplay for compressed images should be calculated as bytes_per_slice * slice_count. Thus, use MSM DSC helper to calculate hdisplay for dsi_timing_setup instead of directly using mode->hdisplay. Changes in v3: - Split from previous patch - Initialized hdisplay as uncompressed pclk per line at the beginning of dsi_timing_setup as to not break dual DSI calculations Changes in v4: - Moved pclk_per_intf calculations to DSC hdisplay adjustments Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 6a6218a9655f..412339cc9301 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -958,7 +958,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) * pulse width same */ h_total -= hdisplay; - hdisplay /= 3; + hdisplay = msm_dsc_get_pclk_per_intf(msm_host->dsc) / 3; h_total += hdisplay; ha_end = ha_start + hdisplay; } From patchwork Wed Apr 12 19:09:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 13209428 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5426C77B72 for ; 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Wed, 12 Apr 2023 12:09:58 -0700 From: Jessica Zhang Date: Wed, 12 Apr 2023 12:09:48 -0700 Subject: [PATCH v5 8/8] drm/msm/dsi: Fix calculation for pkt_per_line MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v5-8-0108401d7886@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v5-0-0108401d7886@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-00303 X-Developer-Signature: v=1; a=ed25519-sha256; t=1681326596; l=1392; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=epOztMquNcJjfSdTdLWdp4KesaKwtwKqdN08Dl1tTJA=; b=hB56qmkmNTcFr4ER+re/AP25uwZAHXMMtMoKz9rzXHjnJQvTCUA2/PyrtuvS+P20ojXkUEW6R 20c+KvZ2n//BBnotWAKiSwBQoLxfyFmrJC6xblYuHM1eFKbvQ6EZNGl X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: IhG9ZwIdYeloNIKNdGtpqmD-gr5NVWry X-Proofpoint-GUID: IhG9ZwIdYeloNIKNdGtpqmD-gr5NVWry X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-12_10,2023-04-12_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 mlxlogscore=977 suspectscore=0 adultscore=0 spamscore=0 impostorscore=0 malwarescore=0 clxscore=1015 mlxscore=0 lowpriorityscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304120164 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Currently, pkt_per_line is calculated by dividing slice_per_intf by slice_count. This is incorrect, as slice_per_intf should be divided by slice_per_pkt, which is not always equivalent to slice_count as it is possible for there to be multiple soft slices per interface even though a panel only specifies one slice per packet. Fixes: 08802f515c3c ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 412339cc9301..633b60acfe18 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -862,7 +862,11 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod total_bytes_per_intf = msm_dsc_get_bytes_per_intf(dsc, hdisplay); eol_byte_num = total_bytes_per_intf % 3; - pkt_per_line = slice_per_intf / dsc->slice_count; + + /* Default to 1 slice_per_pkt, so pkt_per_line will be equal to + * slice per intf. + */ + pkt_per_line = slice_per_intf; if (is_cmd_mode) /* packet data type */ reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE);