From patchwork Sun Apr 16 13:34:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 11741C77B77 for ; Sun, 16 Apr 2023 13:35:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id E4920C4339E; Sun, 16 Apr 2023 13:35:36 +0000 (UTC) Received: from mail-ej1-f53.google.com (mail-ej1-f53.google.com [209.85.218.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id DFBC1C4339B; Sun, 16 Apr 2023 13:35:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org DFBC1C4339B Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-f53.google.com with SMTP id dx24so13439960ejb.11; Sun, 16 Apr 2023 06:35:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681652134; x=1684244134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9UY+jtzkZVxp695kD2INeOepNCktKBgUK3witE0IcM4=; b=iaTooN0HV3wy+r8wq4Tu/QDcwsEjpCqQ8moi/+BO4r9tom4CDZcYLjR3oWufi4pXYN DUnYtHtrBufhSYykf/7uASG1jLIRcIi3pBOgIPvkPQCBjmZsGJ/YUYlo4nDw/5rtH9zJ 665gVk1zHEQlfSU2JIvzLHo32isQYdX9yg49Bfq0nSxHE9PS5Qn3oDcBa0H8Z2b19Ra7 aQTK413zxQxnMRKoXShJvxc2Q6l8qNMBDEyZPTzcn47LVOWJ0qYWr3ACHhxTDVhFU1Y7 3e6NsXzjs3aLxJvGCMBE7LzoPa8e2eh71tloy/03nMr0f17wKg5yH0wyP1l5TEXQdy+h JyCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681652134; x=1684244134; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9UY+jtzkZVxp695kD2INeOepNCktKBgUK3witE0IcM4=; b=aom4LRjunKIMQcmmZtxi/PzgkhJYe2APYx4bP45t5KwYNPAmd5+yQUuxoOVopWWLew yvxiixJYWyf3kIEzxi7uSkqfYtUviInA6V0rXGy/EVUk/vUiiZ7qQLVC9LZuHF26Z6xm lcTmpLeQVo3Ovj7XUmD38fa9fIKKx+STg3Oqth9feqwuTtrS5QP9zLGqeNK7ta18RQwN sS1Uu5hmV1Y3RlL+0yRIgmlXS/p73ozcrQ0Kxl/ttiW33V7a5EoEq7YTIFjWrVY3MXk0 N/BBaywSihAHEipTJVwbNYlAvXEmmg9Wuplm6QP6cOy+jIwkfL3xR69dR7oPh8C4g7EO m9yw== X-Gm-Message-State: AAQBX9dNSvXcQY8d5LX2ulJc+fk6eX8PgFHbJCPGipePgb7+ytsVrpmm kMf++WBrNf/+IwiM+1H5mX8= X-Google-Smtp-Source: AKy350ZO/bAqHPULEAVisdWwkRtRXKRD5ZhIpPWHtjHQe58iG5EhjU3xPTw+FcVrRY82zYRSX+U8RA== X-Received: by 2002:a17:906:58d:b0:94e:da66:c5b2 with SMTP id 13-20020a170906058d00b0094eda66c5b2mr3861559ejn.73.1681652134152; Sun, 16 Apr 2023 06:35:34 -0700 (PDT) Received: from localhost.my.domain (83.8.121.70.ipv4.supernova.orange.pl. [83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:33 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 01/12] dt-bindings: soc: samsung: add Exynos4212 PMU compatible Date: Sun, 16 Apr 2023 15:34:11 +0200 Message-Id: <20230416133422.1949-2-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The platform was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. Signed-off-by: Artur Weber --- Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index f7c141dd11ec..be3128f2c0df 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -17,6 +17,7 @@ select: enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5260-pmu @@ -36,6 +37,7 @@ properties: - enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5260-pmu @@ -122,6 +124,7 @@ allOf: enum: - samsung,exynos3250-pmu - samsung,exynos4210-pmu + - samsung,exynos4212-pmu - samsung,exynos4412-pmu - samsung,exynos5250-pmu - samsung,exynos5410-pmu From patchwork Sun Apr 16 13:34:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CCEF4C77B73 for ; Sun, 16 Apr 2023 13:35:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 8D69BC4339E; Sun, 16 Apr 2023 13:35:39 +0000 (UTC) Received: from mail-ej1-f43.google.com (mail-ej1-f43.google.com [209.85.218.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id ADD2DC4339B; Sun, 16 Apr 2023 13:35:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org ADD2DC4339B Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-f43.google.com with SMTP id fw30so4674450ejc.5; Sun, 16 Apr 2023 06:35:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681652137; x=1684244137; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lcsub8KhIgRh8+LjsAALX2kQhfzLuSTeBZW6A1vW2A0=; b=iwMbVHa2MlgG+jx7mloofP6Nhzg6eDc/daviEdAbzrJm8snqyK4r5K/LnDuGCaHplN ux+3e6SEg7bmLl68gyyylkkkc6rLq2fFEmXiRkrdalZUEHrdlB31AYnZsceJw8Fl7mNZ mCvXrGL20X921acbXCWbvcPEhzWQyG2zfcJPJpnT41ZIFpDoyNYtmGi++8qjAAGiPzSs X0TUE/6/+8998N2H5pjWRVr2lLuo7pMNW/ES/2BThl+wol5rBLzECPqcWewNU8ImVjVK a9JzopBdhbPXQgoJOBKvvA2PcVrJjf319Ie4UI/yrHgFnE8rEBclRJkEYHBKNrk9kF4n iEfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681652137; x=1684244137; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lcsub8KhIgRh8+LjsAALX2kQhfzLuSTeBZW6A1vW2A0=; b=athbsGCRD2JwMJqt1K6fByERxc/6+U3niGlKg8kB+ZizttJMVrOceFqcTK+hvrjnSH nykMG4w1kMsB55FzbOcm3REBBrhk8fxRnUwUSGLZGU+IVdwoRMAD3tuY2C0bFRhXLWQD 5pVnAqIWqH7J8qRN4E91HuxuACNd3j1FrR+FyLv3bVbjPZqPM9AngmMLzdqpFU/FZgbh 8fukJBengjgruV0PraDq5TbfPuCHGq76sYPq9gTZPNs4ehaLdPFKj58ycDZ8sLeCZmfj E6x3jlAiPiVQ4r94eNFuE3TU3vqkDtBwSfRoPbwphzck5Yju+VHcV5RTq+2WAZWYDRCz zxHg== X-Gm-Message-State: AAQBX9fsrkq3GB30tRoOGOJElr8sRrH6dIKRVkNLiqDyGF5JIfLkq3E8 jceiRUIylt/Qh2uNYwQCLMg= X-Google-Smtp-Source: AKy350bGaVuX5pzurnhlXfdKfoZIS5zhuQjlj1IZXMX185GoOm0fxbH3sL4jtNmKj8vjEVK4oORE4Q== X-Received: by 2002:a17:906:254:b0:93b:5f2:36c with SMTP id 20-20020a170906025400b0093b05f2036cmr4220124ejl.61.1681652136807; Sun, 16 Apr 2023 06:35:36 -0700 (PDT) Received: from localhost.my.domain (83.8.121.70.ipv4.supernova.orange.pl. [83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:36 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 02/12] dt-bindings: clock: add Exynos4212 clock compatible Date: Sun, 16 Apr 2023 15:34:12 +0200 Message-Id: <20230416133422.1949-3-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The platform was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. Signed-off-by: Artur Weber --- .../devicetree/bindings/clock/samsung,exynos-clock.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml index 0589a63e273a..a36781a455b6 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml @@ -24,6 +24,7 @@ properties: - samsung,exynos3250-cmu-dmc - samsung,exynos3250-cmu-isp - samsung,exynos4210-clock + - samsung,exynos4212-clock - samsung,exynos4412-clock - samsung,exynos5250-clock - items: From patchwork Sun Apr 16 13:34:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7AFF5C7EE20 for ; Sun, 16 Apr 2023 13:35:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 604B6C433AA; Sun, 16 Apr 2023 13:35:42 +0000 (UTC) Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 4E91BC433EF; Sun, 16 Apr 2023 13:35:41 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 4E91BC433EF Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-f44.google.com with SMTP id xd13so23553364ejb.4; Sun, 16 Apr 2023 06:35:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681652139; x=1684244139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ads9PaDpLFMxNXIqpGW0TRi2DREypjUaM/F9ijw7fLg=; b=hCmzpPTm6Llt0v3x9eLmqKG/7YKO62IIb3juGKudvZR4xIDmT5C1wwqnzTDmU8R0AX KcMrT6KZyrSwHjQInL/bEyEgXQefT78/wRKseJDRVImC3fhTrq/UoisJNe3XDwkJZnWE e2pGnAw2QcIXkhvDFAIpT/1Zm+N8Rvzv5d6Rn13/n+B7+n+BfYutoo8G/9z3wSoYMLSG eO5BmLFG9OvwYJ9WnrYEa7boSiavr/9qP3PYQDW6vmSTUeKZ/0QIzDVEW+6O5rHe+wSg /L7orLggpRECNhZ21VIFW8La46bMrMR+o+yFec4Pkj4t87t6bLK6EgEB1oazag3Dkc5H DH5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681652139; x=1684244139; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ads9PaDpLFMxNXIqpGW0TRi2DREypjUaM/F9ijw7fLg=; b=iB2Wf6CCFtPD5jv7ma1ufiYoS0WJcJuV00p6cg2kuhzkwybYtFi2x8l1z0wWVC5yKX Nmh6DMsfNVMmSYcgpe4UxMOU8bwOEYW4qdmAk7+Ab6CMrslzDDjmF7jEREPW6iuV2h1b P4Z3wePk7KeO2CkcEPuJcPILgdYFFWDO8nl2+bs2Vl+Y7zO+BE6ZyvFItQMwGJhZNZw3 DBZwBYqqzo7Tzcc2QeKczBo2gCD5fgPeedim12QRz8dWg+2lWtiYiLOD5Mhq4r8eQYH3 WrIOWiW+k21w0vP+eWFO7aTdke2kewAZxomOaR8UJsHgRYlPxK1TvnJ1TMQD0QYvRmbL dy2g== X-Gm-Message-State: AAQBX9e0Dll4jxbVfmNMLPYbovwfhFEuiGUxmIejMDMrxhYMGrdDAX7b 721922V9zDyPx6qjum8y7oQ= X-Google-Smtp-Source: AKy350YRu6qOt9Bau0nwy9dTE7kzSEMo8AqoB896i81vC6wp6OwNRfIlSgYDy0oCffJMuMEb/kLBWg== X-Received: by 2002:a17:906:4955:b0:8f4:ec13:d599 with SMTP id f21-20020a170906495500b008f4ec13d599mr5125024ejt.27.1681652139279; Sun, 16 Apr 2023 06:35:39 -0700 (PDT) Received: from localhost.my.domain (83.8.121.70.ipv4.supernova.orange.pl. [83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:38 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 03/12] ARM: exynos: Re-introduce Exynos4212 support Date: Sun, 16 Apr 2023 15:34:13 +0200 Message-Id: <20230416133422.1949-4-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The platform was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. This effectively reverts commit 9e43eca3c874 ("ARM: EXYNOS: Remove Exynos4212 related dead code"). Signed-off-by: Artur Weber --- arch/arm/mach-exynos/Kconfig | 5 +++++ arch/arm/mach-exynos/common.h | 8 ++++++++ arch/arm/mach-exynos/exynos.c | 2 ++ arch/arm/mach-exynos/firmware.c | 8 +++++++- arch/arm/mach-exynos/pm.c | 2 +- arch/arm/mach-exynos/suspend.c | 4 ++++ 6 files changed, 27 insertions(+), 2 deletions(-) diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig index 4d3b40e4049a..b3d5df5225fe 100644 --- a/arch/arm/mach-exynos/Kconfig +++ b/arch/arm/mach-exynos/Kconfig @@ -78,6 +78,11 @@ config CPU_EXYNOS4210 default y depends on ARCH_EXYNOS4 +config SOC_EXYNOS4212 + bool "Samsung Exynos4212" + default y + depends on ARCH_EXYNOS4 + config SOC_EXYNOS4412 bool "Samsung Exynos4412" default y diff --git a/arch/arm/mach-exynos/common.h b/arch/arm/mach-exynos/common.h index 29eb075b24a4..c9e85d33c309 100644 --- a/arch/arm/mach-exynos/common.h +++ b/arch/arm/mach-exynos/common.h @@ -15,6 +15,7 @@ #define EXYNOS3_SOC_MASK 0xFFFFF000 #define EXYNOS4210_CPU_ID 0x43210000 +#define EXYNOS4212_CPU_ID 0x43220000 #define EXYNOS4412_CPU_ID 0xE4412200 #define EXYNOS4_CPU_MASK 0xFFFE0000 @@ -34,6 +35,7 @@ static inline int is_samsung_##name(void) \ IS_SAMSUNG_CPU(exynos3250, EXYNOS3250_SOC_ID, EXYNOS3_SOC_MASK) IS_SAMSUNG_CPU(exynos4210, EXYNOS4210_CPU_ID, EXYNOS4_CPU_MASK) +IS_SAMSUNG_CPU(exynos4212, EXYNOS4212_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos4412, EXYNOS4412_CPU_ID, EXYNOS4_CPU_MASK) IS_SAMSUNG_CPU(exynos5250, EXYNOS5250_SOC_ID, EXYNOS5_SOC_MASK) IS_SAMSUNG_CPU(exynos5410, EXYNOS5410_SOC_ID, EXYNOS5_SOC_MASK) @@ -52,6 +54,12 @@ IS_SAMSUNG_CPU(exynos5800, EXYNOS5800_SOC_ID, EXYNOS5_SOC_MASK) # define soc_is_exynos4210() 0 #endif +#if defined(CONFIG_SOC_EXYNOS4212) +# define soc_is_exynos4212() is_samsung_exynos4212() +#else +# define soc_is_exynos4212() 0 +#endif + #if defined(CONFIG_SOC_EXYNOS4412) # define soc_is_exynos4412() is_samsung_exynos4412() #else diff --git a/arch/arm/mach-exynos/exynos.c b/arch/arm/mach-exynos/exynos.c index 51a247ca4da8..5671621f1661 100644 --- a/arch/arm/mach-exynos/exynos.c +++ b/arch/arm/mach-exynos/exynos.c @@ -178,6 +178,7 @@ static void __init exynos_dt_machine_init(void) exynos_cpuidle.dev.platform_data = &cpuidle_coupled_exynos_data; #endif if (of_machine_is_compatible("samsung,exynos4210") || + of_machine_is_compatible("samsung,exynos4212") || (of_machine_is_compatible("samsung,exynos4412") && (of_machine_is_compatible("samsung,trats2") || of_machine_is_compatible("samsung,midas") || @@ -192,6 +193,7 @@ static char const *const exynos_dt_compat[] __initconst = { "samsung,exynos3250", "samsung,exynos4", "samsung,exynos4210", + "samsung,exynos4212", "samsung,exynos4412", "samsung,exynos5", "samsung,exynos5250", diff --git a/arch/arm/mach-exynos/firmware.c b/arch/arm/mach-exynos/firmware.c index 2da5b60b59e2..110c8064ee64 100644 --- a/arch/arm/mach-exynos/firmware.c +++ b/arch/arm/mach-exynos/firmware.c @@ -63,12 +63,18 @@ static int exynos_cpu_boot(int cpu) * * On Exynos5 devices the call is ignored by trustzone firmware. */ - if (!soc_is_exynos4210() && !soc_is_exynos4412()) + if (!soc_is_exynos4210() && !soc_is_exynos4412() && + !soc_is_exynos4212()) return 0; /* * The second parameter of SMC_CMD_CPU1BOOT command means CPU id. + * But, Exynos4212 has only one secondary CPU so second parameter + * isn't used for informing secure firmware about CPU id. */ + if (soc_is_exynos4212()) + cpu = 0; + exynos_smc(SMC_CMD_CPU1BOOT, cpu, 0, 0); return 0; } diff --git a/arch/arm/mach-exynos/pm.c b/arch/arm/mach-exynos/pm.c index 30f4e55bf39e..9b6db04e4e34 100644 --- a/arch/arm/mach-exynos/pm.c +++ b/arch/arm/mach-exynos/pm.c @@ -161,7 +161,7 @@ void exynos_enter_aftr(void) exynos_pm_central_suspend(); - if (soc_is_exynos4412()) { + if (soc_is_exynos4412() || soc_is_exynos4212()) { /* Setting SEQ_OPTION register */ pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0, S5P_CENTRAL_SEQ_OPTION); diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c index 3bf14ca78b62..df1e10033f90 100644 --- a/arch/arm/mach-exynos/suspend.c +++ b/arch/arm/mach-exynos/suspend.c @@ -231,6 +231,7 @@ static int __init exynos_pmu_irq_init(struct device_node *node, EXYNOS_PMU_IRQ(exynos3250_pmu_irq, "samsung,exynos3250-pmu"); EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu"); +EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu"); EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu"); EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu"); EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu"); @@ -640,6 +641,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] __initconst = { }, { .compatible = "samsung,exynos4210-pmu", .data = &exynos4_pm_data, + }, { + .compatible = "samsung,exynos4212-pmu", + .data = &exynos4_pm_data, }, { .compatible = "samsung,exynos4412-pmu", .data = &exynos4_pm_data, From patchwork Sun Apr 16 13:34:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2F4D3C77B61 for ; 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[83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:41 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 04/12] soc: samsung: Re-introduce Exynos4212 support Date: Sun, 16 Apr 2023 15:34:14 +0200 Message-Id: <20230416133422.1949-5-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The platform was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. This effectively reverts commit c40610198f35 ("soc: samsung: Remove Exynos4212 related dead code"). Signed-off-by: Artur Weber --- drivers/soc/samsung/exynos-pmu.c | 9 +++++++++ drivers/soc/samsung/exynos-pmu.h | 2 ++ drivers/soc/samsung/exynos4-pmu.c | 13 +++++++++++-- 3 files changed, 22 insertions(+), 2 deletions(-) diff --git a/drivers/soc/samsung/exynos-pmu.c b/drivers/soc/samsung/exynos-pmu.c index 732c86ce2be8..f3437db2fbdc 100644 --- a/drivers/soc/samsung/exynos-pmu.c +++ b/drivers/soc/samsung/exynos-pmu.c @@ -57,6 +57,12 @@ void exynos_sys_powerdown_conf(enum sys_powerdown mode) if (pmu_data->powerdown_conf_extra) pmu_data->powerdown_conf_extra(mode); + + if (pmu_data->pmu_config_extra) { + for (i = 0; pmu_data->pmu_config_extra[i].offset != PMU_TABLE_END; i++) + pmu_raw_writel(pmu_data->pmu_config_extra[i].val[mode], + pmu_data->pmu_config_extra[i].offset); + } } /* @@ -79,6 +85,9 @@ static const struct of_device_id exynos_pmu_of_device_ids[] = { }, { .compatible = "samsung,exynos4210-pmu", .data = exynos_pmu_data_arm_ptr(exynos4210_pmu_data), + }, { + .compatible = "samsung,exynos4212-pmu", + .data = exynos_pmu_data_arm_ptr(exynos4212_pmu_data), }, { .compatible = "samsung,exynos4412-pmu", .data = exynos_pmu_data_arm_ptr(exynos4412_pmu_data), diff --git a/drivers/soc/samsung/exynos-pmu.h b/drivers/soc/samsung/exynos-pmu.h index 5e851f32307e..1c652ffd79b4 100644 --- a/drivers/soc/samsung/exynos-pmu.h +++ b/drivers/soc/samsung/exynos-pmu.h @@ -20,6 +20,7 @@ struct exynos_pmu_conf { struct exynos_pmu_data { const struct exynos_pmu_conf *pmu_config; + const struct exynos_pmu_conf *pmu_config_extra; void (*pmu_init)(void); void (*powerdown_conf)(enum sys_powerdown); @@ -32,6 +33,7 @@ extern void __iomem *pmu_base_addr; /* list of all exported SoC specific data */ extern const struct exynos_pmu_data exynos3250_pmu_data; extern const struct exynos_pmu_data exynos4210_pmu_data; +extern const struct exynos_pmu_data exynos4212_pmu_data; extern const struct exynos_pmu_data exynos4412_pmu_data; extern const struct exynos_pmu_data exynos5250_pmu_data; extern const struct exynos_pmu_data exynos5420_pmu_data; diff --git a/drivers/soc/samsung/exynos4-pmu.c b/drivers/soc/samsung/exynos4-pmu.c index cb35103565a6..f8092190b938 100644 --- a/drivers/soc/samsung/exynos4-pmu.c +++ b/drivers/soc/samsung/exynos4-pmu.c @@ -86,7 +86,7 @@ static const struct exynos_pmu_conf exynos4210_pmu_config[] = { { PMU_TABLE_END,}, }; -static const struct exynos_pmu_conf exynos4412_pmu_config[] = { +static const struct exynos_pmu_conf exynos4x12_pmu_config[] = { { S5P_ARM_CORE0_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE0, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL0, { 0x0, 0x0, 0x0 } }, @@ -191,6 +191,10 @@ static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_GPS_ALIVE_LOWPWR, { 0x7, 0x0, 0x0 } }, { S5P_CMU_SYSCLK_ISP_LOWPWR, { 0x1, 0x0, 0x0 } }, { S5P_CMU_SYSCLK_GPS_LOWPWR, { 0x1, 0x0, 0x0 } }, + { PMU_TABLE_END,}, +}; + +static const struct exynos_pmu_conf exynos4412_pmu_config[] = { { S5P_ARM_CORE2_LOWPWR, { 0x0, 0x0, 0x2 } }, { S5P_DIS_IRQ_CORE2, { 0x0, 0x0, 0x0 } }, { S5P_DIS_IRQ_CENTRAL2, { 0x0, 0x0, 0x0 } }, @@ -204,6 +208,11 @@ const struct exynos_pmu_data exynos4210_pmu_data = { .pmu_config = exynos4210_pmu_config, }; +const struct exynos_pmu_data exynos4212_pmu_data = { + .pmu_config = exynos4x12_pmu_config, +}; + const struct exynos_pmu_data exynos4412_pmu_data = { - .pmu_config = exynos4412_pmu_config, + .pmu_config = exynos4x12_pmu_config, + .pmu_config_extra = exynos4412_pmu_config, }; From patchwork Sun Apr 16 13:34:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 115B1C7EE25 for ; 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[83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:43 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 05/12] clk: samsung: Add Exynos4212 compatible to CLKOUT driver Date: Sun, 16 Apr 2023 15:34:15 +0200 Message-Id: <20230416133422.1949-6-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The platform was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. This is effectively a revert of commit d5cd103b06f9 ("clk: samsung: Remove support for Exynos4212 SoCs in Exynos CLKOUT driver"); the driver has changed significantly since then, prompting this re-make. Signed-off-by: Artur Weber --- drivers/clk/samsung/clk-exynos-clkout.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos-clkout.c b/drivers/clk/samsung/clk-exynos-clkout.c index e6d6cbf8c4e6..326d5fc58727 100644 --- a/drivers/clk/samsung/clk-exynos-clkout.c +++ b/drivers/clk/samsung/clk-exynos-clkout.c @@ -55,6 +55,9 @@ static const struct of_device_id exynos_clkout_ids[] = { }, { .compatible = "samsung,exynos4210-pmu", .data = &exynos_clkout_exynos4, + }, { + .compatible = "samsung,exynos4212-pmu", + .data = &exynos_clkout_exynos4, }, { .compatible = "samsung,exynos4412-pmu", .data = &exynos_clkout_exynos4, From patchwork Sun Apr 16 13:34:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A6E7EC77B7A for ; Sun, 16 Apr 2023 13:35:49 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 8A9ABC4339B; Sun, 16 Apr 2023 13:35:49 +0000 (UTC) Received: from mail-ej1-f44.google.com (mail-ej1-f44.google.com [209.85.218.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 714C9C433EF; Sun, 16 Apr 2023 13:35:48 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 714C9C433EF Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-f44.google.com with SMTP id c9so18616053ejz.1; Sun, 16 Apr 2023 06:35:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681652146; x=1684244146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rsVMP+nc4oNcZ87McW4OVdy6DpQdiSat54tBtHLhBBY=; b=BK9ciytjH5O2apYl911PFKkIxjD0zuyUTnHnkFvow0HPrFXNgXRS+bCDhdVp/D36t6 2P+yZB0Cqdr/gCuTRs5bqhMWolKAffqrQgg9iAQve6wBRsD6NVOxaeGXviUDLeV3rJuR xLdhNHynxxhPQGqFxrD6NL5AK92/CrwjBjCH+NRPxkfCyXCUTnTwKgi5E73R0eV7jBwZ HznmnxwUraE0gCIW5shq36yHLszhwO9+ho7QeR+RTJKYESs+Q3YqnnBWCavzVTrwfVvh 9ov5d3uIsJZKmu/pF0PG+eTcUExVaN7r7ETQ1ENn984AqaKihGNVEDbOeyz6yR/EZfad w00Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681652146; x=1684244146; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rsVMP+nc4oNcZ87McW4OVdy6DpQdiSat54tBtHLhBBY=; b=Lhg3RQyB6YugnE7UJOFKO61/3JIl7NYuHEtIATxvTjbDxnN1JMx1BAyJGFSvJV4c7M 0hoQNU+qZjjkm0bPD2fVezMHsLg0hGww/CmS2w6rv4ujSgW2Vr8c+FMC0HyY3R6KxeTI FHOTgGYC7KxkZL9BHVdgG6LAJoamfTmZeiQpeBu1PWEgaiEkNQLXKWn/dwUl5M47ChaA fJCebawYrKhBtDWT2TR+hH2boJDzb3RCE8CdjvLhgvpGXneeJRYwCB+gGUBiqRY6ICvZ XuDkapK01MNPIC/ja5xGguQHNtwTltDADiA5t8QXeu/8LRwMrYTCTy23EgRm9G/oGw33 TMNA== X-Gm-Message-State: AAQBX9c7/0YTbwAy9i4deQdyS789MbHx/4CVPxiv/MVbs7vI3oORmhz0 2H4Qz98D3PZv73+nQx3RfXs= X-Google-Smtp-Source: AKy350aOQZtUDJ6HCtW/XeHcJyZm9y8dSlT6kREJgZmf3EgNgVfgfeFUalYfzshLE7tAJJsTQfMIqQ== X-Received: by 2002:a17:906:4a0f:b0:94e:d664:c2d5 with SMTP id w15-20020a1709064a0f00b0094ed664c2d5mr4822386eju.21.1681652146503; Sun, 16 Apr 2023 06:35:46 -0700 (PDT) Received: from localhost.my.domain (83.8.121.70.ipv4.supernova.orange.pl. [83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:46 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 06/12] clk: samsung: Re-add support for Exynos4212 CPU clock Date: Sun, 16 Apr 2023 15:34:16 +0200 Message-Id: <20230416133422.1949-7-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The platform was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. This is effectively a revert of commit c9194fb623b0 ("clk: samsung: Remove support for obsolete Exynos4212 CPU clock"); the driver has changed significantly since then, prompting this re-make. Signed-off-by: Artur Weber --- drivers/clk/samsung/clk-exynos4.c | 44 +++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 5 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c index 22009cb53428..9655f46db95c 100644 --- a/drivers/clk/samsung/clk-exynos4.c +++ b/drivers/clk/samsung/clk-exynos4.c @@ -138,7 +138,8 @@ /* the exynos4 soc type */ enum exynos4_soc { EXYNOS4210, - EXYNOS4X12, + EXYNOS4412, + EXYNOS4212, }; /* list of PLLs to be registered */ @@ -1205,6 +1206,24 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = { { 0 }, }; +static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = { + { 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, + { 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), }, + { 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, + { 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), }, + { 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), }, + { 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), }, + { 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, + { 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), }, + { 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), }, + { 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), }, + { 0 }, +}; + #define E4412_CPU_DIV1(cores, hpm, copy) \ (((cores) << 8) | ((hpm) << 4) | ((copy) << 0)) @@ -1233,6 +1252,11 @@ static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = { CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d), }; +static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = { + CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, + CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d), +}; + static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = { CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C, CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d), @@ -1326,11 +1350,15 @@ static void __init exynos4_clk_init(struct device_node *np, samsung_clk_register_fixed_factor(ctx, exynos4x12_fixed_factor_clks, ARRAY_SIZE(exynos4x12_fixed_factor_clks)); - samsung_clk_register_cpu(ctx, exynos4412_cpu_clks, - ARRAY_SIZE(exynos4412_cpu_clks)); + if (soc == EXYNOS4412) + samsung_clk_register_cpu(ctx, exynos4412_cpu_clks, + ARRAY_SIZE(exynos4412_cpu_clks)); + else + samsung_clk_register_cpu(ctx, exynos4212_cpu_clks, + ARRAY_SIZE(exynos4212_cpu_clks)); } - if (soc == EXYNOS4X12) + if (soc == EXYNOS4412 || soc == EXYNOS4212) exynos4x12_core_down_clock(); samsung_clk_extended_sleep_init(reg_base, @@ -1363,8 +1391,14 @@ static void __init exynos4210_clk_init(struct device_node *np) } CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init); +static void __init exynos4212_clk_init(struct device_node *np) +{ + exynos4_clk_init(np, EXYNOS4212); +} +CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init); + static void __init exynos4412_clk_init(struct device_node *np) { - exynos4_clk_init(np, EXYNOS4X12); + exynos4_clk_init(np, EXYNOS4412); } CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init); From patchwork Sun Apr 16 13:34:17 2023 Content-Type: text/plain; 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[83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:48 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 07/12] Revert "media: exynos4-is: Remove dependency on obsolete SoC support" Date: Sun, 16 Apr 2023 15:34:17 +0200 Message-Id: <20230416133422.1949-8-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The platform was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit 2d41a0c9ae51ac363d107f2510022106e7234b33. Signed-off-by: Artur Weber --- drivers/media/platform/samsung/exynos4-is/Kconfig | 2 +- drivers/media/platform/samsung/exynos4-is/fimc-core.c | 2 +- drivers/media/platform/samsung/exynos4-is/fimc-lite.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/samsung/exynos4-is/Kconfig b/drivers/media/platform/samsung/exynos4-is/Kconfig index da33faa7132e..7f9ba053dd8e 100644 --- a/drivers/media/platform/samsung/exynos4-is/Kconfig +++ b/drivers/media/platform/samsung/exynos4-is/Kconfig @@ -47,7 +47,7 @@ config VIDEO_S5P_MIPI_CSIS config VIDEO_EXYNOS_FIMC_LITE tristate "EXYNOS FIMC-LITE camera interface driver" depends on I2C - depends on SOC_EXYNOS4412 || SOC_EXYNOS5250 || COMPILE_TEST + depends on SOC_EXYNOS4212 || SOC_EXYNOS4412 || SOC_EXYNOS5250 || COMPILE_TEST depends on HAS_DMA select VIDEOBUF2_DMA_CONTIG select VIDEO_EXYNOS4_IS_COMMON diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-core.c b/drivers/media/platform/samsung/exynos4-is/fimc-core.c index 1791100b6935..e2f394e60dee 100644 --- a/drivers/media/platform/samsung/exynos4-is/fimc-core.c +++ b/drivers/media/platform/samsung/exynos4-is/fimc-core.c @@ -1129,7 +1129,7 @@ static const struct fimc_drvdata fimc_drvdata_exynos4210 = { .out_buf_count = 32, }; -/* EXYNOS4412 */ +/* EXYNOS4212, EXYNOS4412 */ static const struct fimc_drvdata fimc_drvdata_exynos4x12 = { .num_entities = 4, .lclk_frequency = 166000000UL, diff --git a/drivers/media/platform/samsung/exynos4-is/fimc-lite.c b/drivers/media/platform/samsung/exynos4-is/fimc-lite.c index e185a40305a8..f80047095f30 100644 --- a/drivers/media/platform/samsung/exynos4-is/fimc-lite.c +++ b/drivers/media/platform/samsung/exynos4-is/fimc-lite.c @@ -1619,7 +1619,7 @@ static const struct dev_pm_ops fimc_lite_pm_ops = { NULL) }; -/* EXYNOS4412 */ +/* EXYNOS4212, EXYNOS4412 */ static struct flite_drvdata fimc_lite_drvdata_exynos4 = { .max_width = 8192, .max_height = 8192, From patchwork Sun Apr 16 13:34:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DB097C77B7A for ; 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[83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:50 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 08/12] Revert "phy: Remove SOC_EXYNOS4212 dep. from PHY_EXYNOS4X12_USB" Date: Sun, 16 Apr 2023 15:34:18 +0200 Message-Id: <20230416133422.1949-9-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The platform was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. This reverts commit fee7e1d50c6e6da1d99035181ba5a5c88f5bb526. Signed-off-by: Artur Weber --- drivers/phy/samsung/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/samsung/Kconfig b/drivers/phy/samsung/Kconfig index 3ccaabf2850a..f10afa3d7ff5 100644 --- a/drivers/phy/samsung/Kconfig +++ b/drivers/phy/samsung/Kconfig @@ -59,7 +59,7 @@ config PHY_EXYNOS4210_USB2 config PHY_EXYNOS4X12_USB2 bool depends on PHY_SAMSUNG_USB2 - default SOC_EXYNOS3250 || SOC_EXYNOS4412 + default SOC_EXYNOS3250 || SOC_EXYNOS4212 || SOC_EXYNOS4412 config PHY_EXYNOS5250_USB2 bool From patchwork Sun Apr 16 13:34:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212980 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id DCE35C7EE23 for ; Sun, 16 Apr 2023 13:35:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id B8F26C43444; Sun, 16 Apr 2023 13:35:58 +0000 (UTC) Received: from mail-ej1-f68.google.com (mail-ej1-f68.google.com [209.85.218.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 1457EC433A4; Sun, 16 Apr 2023 13:35:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 1457EC433A4 Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-f68.google.com with SMTP id c9so18616608ejz.1; Sun, 16 Apr 2023 06:35:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681652154; x=1684244154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pQtdUpGvqOFI5m3CYQBb7DJVZ7RwGog7OTZYtnBhNgg=; b=gEYHuKUzVAozCaD6E7EU2UuonkmY4sJyEur7ksh/befuOC9PPmaWSHzzNz/tIlvm86 /JQeTe3lJzY6R8380es7HPXvLRnEplN5h/+hRFKEzx09r7h9kMgLVmY0ulUKNX0Au5FG iHq0mY4ePwU1ut19LqIzI/f6dNI1K8tBO5NjbmeijSdbjV3TxNUVVsfUvD8mlYJlFKEN BIY/LZL1BuHP9WkaaWsnQDNDpW+tubyQMvgeIQ6AgEpMD4Z4QWV7wqFFTltff3AnLdRd 3piDlpuZajFMWORY6kcyr79CX7NTEZbUJr2rUnwfmP3v220ZbBm69/6UlZ8GRV+nPIar Hdig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681652154; x=1684244154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pQtdUpGvqOFI5m3CYQBb7DJVZ7RwGog7OTZYtnBhNgg=; b=LFjVfn4O6izI0Cx6h/aPtthaIe+vKoCbgdV0jgU5AfxboA9bijkBeUbDJnEgupK2dW Lek3MucCSJzOSRFle9/TdPDkHcn8g6diZFvXs13HF2m9hZhI8LnMgRAXDpPXL/UWQfkH zAAuW+AUORkWYQtvedLci0Ub+U1Gdcf350ya8g3Ef58VhG47bphOvgdM9l8QBym3fV1+ fYwLzlaVfyhoQu2EzXkygaMzkVE7wl9QeH4ZaFv+Mhkt1kmkChjY2UuZyTewWEYfBto5 WpTecZO0zy5XnXgZDqL295pd3fxIrvF+1at+1bXdhNYvTlmeCCzfEwv397YZLn4v7jqu tBaA== X-Gm-Message-State: AAQBX9e2scTjAxprFNUioUUruXvBZpHuVz2/nZWEojvAA1giudbZ95JW 5WZpJYuBlHPMiYAsyDsUrWI= X-Google-Smtp-Source: AKy350bcbt+kXqVbXMrRRzDyP3re999IIiqHnNBAXF6Vh3cRgJy9p0sNoIltZTtkc4toCfmkUyACbg== X-Received: by 2002:a17:906:f9cd:b0:94f:5fd0:dd42 with SMTP id lj13-20020a170906f9cd00b0094f5fd0dd42mr1205683ejb.39.1681652154038; Sun, 16 Apr 2023 06:35:54 -0700 (PDT) Received: from localhost.my.domain (83.8.121.70.ipv4.supernova.orange.pl. [83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:53 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 09/12] ARM: dts: Move common Exynos4x12 definitions to exynos4x12.dtsi Date: Sun, 16 Apr 2023 15:34:19 +0200 Message-Id: <20230416133422.1949-10-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 In preparation for the re-introduction of the Exynos4212, move their shared definitions to a separate file. Rename the pinctrl definitions accordingly, and adapt the Exynos4412 DTSI to these changes. Signed-off-by: Artur Weber --- arch/arm/boot/dts/exynos4412.dtsi | 645 +---------------- ...2-pinctrl.dtsi => exynos4x12-pinctrl.dtsi} | 4 +- arch/arm/boot/dts/exynos4x12.dtsi | 665 ++++++++++++++++++ 3 files changed, 671 insertions(+), 643 deletions(-) rename arch/arm/boot/dts/{exynos4412-pinctrl.dtsi => exynos4x12-pinctrl.dtsi} (99%) create mode 100644 arch/arm/boot/dts/exynos4x12.dtsi diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index 11f9dd94b6b3..c2b53f1b7a47 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -14,151 +14,11 @@ * nodes can be added to this file. */ -#include "exynos4.dtsi" - -#include "exynos4-cpu-thermal.dtsi" +#include "exynos4x12.dtsi" / { compatible = "samsung,exynos4412", "samsung,exynos4"; - aliases { - pinctrl0 = &pinctrl_0; - pinctrl1 = &pinctrl_1; - pinctrl2 = &pinctrl_2; - pinctrl3 = &pinctrl_3; - fimc-lite0 = &fimc_lite_0; - fimc-lite1 = &fimc_lite_1; - mshc0 = &mshc_0; - }; - - bus_acp: bus-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - - bus_acp_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - }; - - bus_c2c: bus-c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - samsung,data-clock-ratio = <4>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_display: bus-display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - interconnects = <&bus_leftbus &bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - - bus_display_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - - bus_fsys_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - interconnects = <&bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - - bus_peri_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - cpus { #address-cells = <1>; #size-cells = <0>; @@ -298,499 +158,20 @@ cpu0_opp_1500: opp-1500000000 { turbo-mode; }; }; +}; - bus_dmc_opp_table: opp-table-1 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - opp-suspend; - }; - }; - - bus_leftbus_opp_table: opp-table-2 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - opp-suspend; - }; - }; - - soc: soc { - - pinctrl_0: pinctrl@11400000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11400000 0x1000>; - interrupts = ; - }; - - pinctrl_1: pinctrl@11000000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x11000000 0x1000>; - interrupts = ; - - wakup_eint: wakeup-interrupt-controller { - compatible = "samsung,exynos4210-wakeup-eint"; - interrupt-parent = <&gic>; - interrupts = ; - }; - }; - - pinctrl_2: pinctrl@3860000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x03860000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <10 0>; - }; - - pinctrl_3: pinctrl@106e0000 { - compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106e0000 0x1000>; - interrupts = ; - }; - - sram@2020000 { - compatible = "mmio-sram"; - reg = <0x02020000 0x40000>; - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x02020000 0x40000>; - - smp-sram@0 { - compatible = "samsung,exynos4210-sysram"; - reg = <0x0 0x1000>; - }; - - smp-sram@2f000 { - compatible = "samsung,exynos4210-sysram-ns"; - reg = <0x2f000 0x1000>; - }; - }; - - pd_isp: power-domain@10023ca0 { - compatible = "samsung,exynos4210-pd"; - reg = <0x10023ca0 0x20>; - #power-domain-cells = <0>; - label = "ISP"; - }; - - l2c: cache-controller@10502000 { - compatible = "arm,pl310-cache"; - reg = <0x10502000 0x1000>; - cache-unified; - cache-level = <2>; - prefetch-data = <1>; - prefetch-instr = <1>; - arm,tag-latency = <2 2 1>; - arm,data-latency = <3 2 1>; - arm,double-linefill = <1>; - arm,double-linefill-incr = <0>; - arm,double-linefill-wrap = <1>; - arm,prefetch-drop = <1>; - arm,prefetch-offset = <7>; - }; - - clock: clock-controller@10030000 { - compatible = "samsung,exynos4412-clock"; - reg = <0x10030000 0x18000>; - #clock-cells = <1>; - }; - - isp_clock: clock-controller@10048000 { - compatible = "samsung,exynos4412-isp-clock"; - reg = <0x10048000 0x1000>; - #clock-cells = <1>; - power-domains = <&pd_isp>; - clocks = <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>; - clock-names = "aclk200", "aclk400_mcuisp"; - }; - - timer@10050000 { - compatible = "samsung,exynos4412-mct"; - reg = <0x10050000 0x800>; - clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; - clock-names = "fin_pll", "mct"; - interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, - <&combiner 12 5>, - <&combiner 12 6>, - <&combiner 12 7>, - <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; - }; - - watchdog: watchdog@10060000 { - compatible = "samsung,exynos5250-wdt"; - reg = <0x10060000 0x100>; - interrupts = ; - clocks = <&clock CLK_WDT>; - clock-names = "watchdog"; - samsung,syscon-phandle = <&pmu_system_controller>; - }; - - adc: adc@126c0000 { - compatible = "samsung,exynos4212-adc"; - reg = <0x126c0000 0x100>; - interrupt-parent = <&combiner>; - interrupts = <10 3>; - clocks = <&clock CLK_TSADC>; - clock-names = "adc"; - #io-channel-cells = <1>; - samsung,syscon-phandle = <&pmu_system_controller>; - status = "disabled"; - }; - - g2d: g2d@10800000 { - compatible = "samsung,exynos4212-g2d"; - reg = <0x10800000 0x1000>; - interrupts = ; - clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; - clock-names = "sclk_fimg2d", "fimg2d"; - iommus = <&sysmmu_g2d>; - }; - - mshc_0: mmc@12550000 { - compatible = "samsung,exynos4412-dw-mshc"; - reg = <0x12550000 0x1000>; - interrupts = ; - #address-cells = <1>; - #size-cells = <0>; - fifo-depth = <0x80>; - clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; - clock-names = "biu", "ciu"; - status = "disabled"; - }; - - sysmmu_g2d: sysmmu@10a40000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x10a40000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <4 7>; - clock-names = "sysmmu", "master"; - clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_isp: sysmmu@12260000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12260000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 2>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISP>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_drc: sysmmu@12270000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x12270000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 3>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_DRC>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_fd: sysmmu@122a0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122a0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 4>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_FD>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_mcuctl: sysmmu@122b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x122b0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 5>; - power-domains = <&pd_isp>; - clock-names = "sysmmu"; - clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite0: sysmmu@123b0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123b0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 0>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE0>; - #iommu-cells = <0>; - }; - - sysmmu_fimc_lite1: sysmmu@123c0000 { - compatible = "samsung,exynos-sysmmu"; - reg = <0x123c0000 0x1000>; - interrupt-parent = <&combiner>; - interrupts = <16 1>; - power-domains = <&pd_isp>; - clock-names = "sysmmu", "master"; - clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, - <&isp_clock CLK_ISP_FIMC_LITE1>; - #iommu-cells = <0>; - }; - }; +&clock { + compatible = "samsung,exynos4412-clock"; }; &combiner { samsung,combiner-nr = <20>; - interrupts = , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - , - ; -}; - -&camera { - clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, - <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; - clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; - - /* fimc_[0-3] are configured outside, under phandles */ - fimc_lite_0: fimc-lite@12390000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x12390000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite0>; - status = "disabled"; - }; - - fimc_lite_1: fimc-lite@123a0000 { - compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123a0000 0x1000>; - interrupts = ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; - clock-names = "flite"; - iommus = <&sysmmu_fimc_lite1>; - status = "disabled"; - }; - - fimc_is: fimc-is@12000000 { - compatible = "samsung,exynos4212-fimc-is"; - reg = <0x12000000 0x260000>; - interrupts = , - ; - power-domains = <&pd_isp>; - clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, - <&isp_clock CLK_ISP_FIMC_LITE1>, - <&isp_clock CLK_ISP_PPMUISPX>, - <&isp_clock CLK_ISP_PPMUISPMX>, - <&isp_clock CLK_ISP_FIMC_ISP>, - <&isp_clock CLK_ISP_FIMC_DRC>, - <&isp_clock CLK_ISP_FIMC_FD>, - <&isp_clock CLK_ISP_MCUISP>, - <&isp_clock CLK_ISP_GICISP>, - <&isp_clock CLK_ISP_MCUCTL_ISP>, - <&isp_clock CLK_ISP_PWM_ISP>, - <&isp_clock CLK_ISP_DIV_ISP0>, - <&isp_clock CLK_ISP_DIV_ISP1>, - <&isp_clock CLK_ISP_DIV_MCUISP0>, - <&isp_clock CLK_ISP_DIV_MCUISP1>, - <&clock CLK_MOUT_MPLL_USER_T>, - <&clock CLK_ACLK200>, - <&clock CLK_ACLK400_MCUISP>, - <&clock CLK_DIV_ACLK200>, - <&clock CLK_DIV_ACLK400_MCUISP>, - <&clock CLK_UART_ISP_SCLK>; - clock-names = "lite0", "lite1", "ppmuispx", - "ppmuispmx", "isp", - "drc", "fd", "mcuisp", - "gicisp", "mcuctl_isp", "pwm_isp", - "ispdiv0", "ispdiv1", "mcuispdiv0", - "mcuispdiv1", "mpll", "aclk200", - "aclk400mcuisp", "div_aclk200", - "div_aclk400mcuisp", "uart"; - iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, - <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; - iommu-names = "isp", "drc", "fd", "mcuctl"; - #address-cells = <1>; - #size-cells = <1>; - ranges; - status = "disabled"; - - pmu@10020000 { - reg = <0x10020000 0x3000>; - }; - - i2c1_isp: i2c-isp@12140000 { - compatible = "samsung,exynos4212-i2c-isp"; - reg = <0x12140000 0x100>; - clocks = <&isp_clock CLK_ISP_I2C1_ISP>; - clock-names = "i2c_isp"; - #address-cells = <1>; - #size-cells = <0>; - }; - }; -}; - -&exynos_usbphy { - compatible = "samsung,exynos4x12-usb2-phy"; - samsung,sysreg-phandle = <&sys_reg>; -}; - -&fimc_0 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_1 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,cam-if; -}; - -&fimc_2 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <4224 8192 1920 4224>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; - samsung,cam-if; -}; - -&fimc_3 { - compatible = "samsung,exynos4212-fimc"; - samsung,pix-limits = <1920 8192 1366 1920>; - samsung,rotators = <0>; - samsung,mainscaler-ext; - samsung,isp-wb; - samsung,lcd-wb; }; &gic { cpu-offset = <0x4000>; }; -&gpu { - interrupts = , - , - , - , - , - , - , - , - , - , - ; - interrupt-names = "gp", - "gpmmu", - "pp0", - "ppmmu0", - "pp1", - "ppmmu1", - "pp2", - "ppmmu2", - "pp3", - "ppmmu3", - "pmu"; - operating-points-v2 = <&gpu_opp_table>; - - gpu_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <875000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <900000>; - }; - opp-350000000 { - opp-hz = /bits/ 64 <350000000>; - opp-microvolt = <950000>; - }; - opp-440000000 { - opp-hz = /bits/ 64 <440000000>; - opp-microvolt = <1025000>; - }; - }; -}; - -&hdmi { - compatible = "samsung,exynos4212-hdmi"; -}; - -&jpeg_codec { - compatible = "samsung,exynos4212-jpeg"; -}; - -&rotator { - compatible = "samsung,exynos4212-rotator"; -}; - -&mixer { - compatible = "samsung,exynos4212-mixer"; - clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; - clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, - <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; - interconnects = <&bus_display &bus_dmc>; -}; - &pmu { interrupts = <2 2>, <3 2>, <18 2>, <19 2>; interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; @@ -799,22 +180,4 @@ &pmu { &pmu_system_controller { compatible = "samsung,exynos4412-pmu", "syscon"; - clock-names = "clkout0", "clkout1", "clkout2", "clkout3", - "clkout4", "clkout8", "clkout9"; - clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, - <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, - <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; - #clock-cells = <1>; }; - -&tmu { - compatible = "samsung,exynos4412-tmu"; - interrupt-parent = <&combiner>; - interrupts = <2 4>; - reg = <0x100c0000 0x100>; - clocks = <&clock CLK_TMU_APBIF>; - clock-names = "tmu_apbif"; - status = "disabled"; -}; - -#include "exynos4412-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi similarity index 99% rename from arch/arm/boot/dts/exynos4412-pinctrl.dtsi rename to arch/arm/boot/dts/exynos4x12-pinctrl.dtsi index 8ab31c3daa48..9f7ea5f2a91f 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4x12-pinctrl.dtsi @@ -1,11 +1,11 @@ // SPDX-License-Identifier: GPL-2.0 /* - * Samsung's Exynos4412 SoCs pin-mux and pin-config device tree source + * Samsung's Exynos4x12 SoCs pin-mux and pin-config device tree source * * Copyright (c) 2012 Samsung Electronics Co., Ltd. * http://www.samsung.com * - * Samsung's Exynos4412 SoCs pin-mux and pin-config optiosn are listed as device + * Samsung's Exynos4x12 SoCs pin-mux and pin-config optiosn are listed as device * tree nodes are listed in this file. */ diff --git a/arch/arm/boot/dts/exynos4x12.dtsi b/arch/arm/boot/dts/exynos4x12.dtsi new file mode 100644 index 000000000000..76118a34e540 --- /dev/null +++ b/arch/arm/boot/dts/exynos4x12.dtsi @@ -0,0 +1,665 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4x12 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4x12 SoC series device nodes are listed in this file. Particular + * SoCs from Exynos4x12 series can include this file and provide values for SoCs + * specfic bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4x12 SoC. As device tree coverage for Exynos4x12 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4.dtsi" + +#include "exynos4-cpu-thermal.dtsi" + +/ { + aliases { + pinctrl0 = &pinctrl_0; + pinctrl1 = &pinctrl_1; + pinctrl2 = &pinctrl_2; + pinctrl3 = &pinctrl_3; + fimc-lite0 = &fimc_lite_0; + fimc-lite1 = &fimc_lite_1; + mshc0 = &mshc_0; + }; + + bus_acp: bus-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + + bus_acp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + }; + + bus_c2c: bus-c2c { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_C2C>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_display: bus-display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + + bus_display_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + + bus_fsys_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + + bus_peri_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_dmc_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <900000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <900000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + opp-suspend; + }; + }; + + bus_leftbus_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + opp-suspend; + }; + }; + + soc: soc { + + pinctrl_0: pinctrl@11400000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11400000 0x1000>; + interrupts = ; + }; + + pinctrl_1: pinctrl@11000000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x11000000 0x1000>; + interrupts = ; + + wakup_eint: wakeup-interrupt-controller { + compatible = "samsung,exynos4210-wakeup-eint"; + interrupt-parent = <&gic>; + interrupts = ; + }; + }; + + pinctrl_2: pinctrl@3860000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x03860000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <10 0>; + }; + + pinctrl_3: pinctrl@106e0000 { + compatible = "samsung,exynos4x12-pinctrl"; + reg = <0x106e0000 0x1000>; + interrupts = ; + }; + + sram@2020000 { + compatible = "mmio-sram"; + reg = <0x02020000 0x40000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x02020000 0x40000>; + + smp-sram@0 { + compatible = "samsung,exynos4210-sysram"; + reg = <0x0 0x1000>; + }; + + smp-sram@2f000 { + compatible = "samsung,exynos4210-sysram-ns"; + reg = <0x2f000 0x1000>; + }; + }; + + pd_isp: power-domain@10023ca0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x10023ca0 0x20>; + #power-domain-cells = <0>; + label = "ISP"; + }; + + l2c: cache-controller@10502000 { + compatible = "arm,pl310-cache"; + reg = <0x10502000 0x1000>; + cache-unified; + cache-level = <2>; + prefetch-data = <1>; + prefetch-instr = <1>; + arm,tag-latency = <2 2 1>; + arm,data-latency = <3 2 1>; + arm,double-linefill = <1>; + arm,double-linefill-incr = <0>; + arm,double-linefill-wrap = <1>; + arm,prefetch-drop = <1>; + arm,prefetch-offset = <7>; + }; + + clock: clock-controller@10030000 { + reg = <0x10030000 0x18000>; + #clock-cells = <1>; + }; + + isp_clock: clock-controller@10048000 { + compatible = "samsung,exynos4412-isp-clock"; + reg = <0x10048000 0x1000>; + #clock-cells = <1>; + power-domains = <&pd_isp>; + clocks = <&clock CLK_ACLK200>, + <&clock CLK_ACLK400_MCUISP>; + clock-names = "aclk200", "aclk400_mcuisp"; + }; + + timer@10050000 { + compatible = "samsung,exynos4412-mct"; + reg = <0x10050000 0x800>; + clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; + clock-names = "fin_pll", "mct"; + interrupts-extended = <&gic GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <&combiner 12 5>, + <&combiner 12 6>, + <&combiner 12 7>, + <&gic GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH>; + }; + + watchdog: watchdog@10060000 { + compatible = "samsung,exynos5250-wdt"; + reg = <0x10060000 0x100>; + interrupts = ; + clocks = <&clock CLK_WDT>; + clock-names = "watchdog"; + samsung,syscon-phandle = <&pmu_system_controller>; + }; + + adc: adc@126c0000 { + compatible = "samsung,exynos4212-adc"; + reg = <0x126c0000 0x100>; + interrupt-parent = <&combiner>; + interrupts = <10 3>; + clocks = <&clock CLK_TSADC>; + clock-names = "adc"; + #io-channel-cells = <1>; + samsung,syscon-phandle = <&pmu_system_controller>; + status = "disabled"; + }; + + g2d: g2d@10800000 { + compatible = "samsung,exynos4212-g2d"; + reg = <0x10800000 0x1000>; + interrupts = ; + clocks = <&clock CLK_SCLK_FIMG2D>, <&clock CLK_G2D>; + clock-names = "sclk_fimg2d", "fimg2d"; + iommus = <&sysmmu_g2d>; + }; + + mshc_0: mmc@12550000 { + compatible = "samsung,exynos4412-dw-mshc"; + reg = <0x12550000 0x1000>; + interrupts = ; + #address-cells = <1>; + #size-cells = <0>; + fifo-depth = <0x80>; + clocks = <&clock CLK_SDMMC4>, <&clock CLK_SCLK_MMC4>; + clock-names = "biu", "ciu"; + status = "disabled"; + }; + + sysmmu_g2d: sysmmu@10a40000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x10a40000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <4 7>; + clock-names = "sysmmu", "master"; + clocks = <&clock CLK_SMMU_G2D>, <&clock CLK_G2D>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_isp: sysmmu@12260000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12260000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 2>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_ISP>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_drc: sysmmu@12270000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x12270000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 3>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_DRC>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_fd: sysmmu@122a0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122a0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 4>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_FD>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_mcuctl: sysmmu@122b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x122b0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 5>; + power-domains = <&pd_isp>; + clock-names = "sysmmu"; + clocks = <&isp_clock CLK_ISP_SMMU_ISPCX>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite0: sysmmu@123b0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123b0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 0>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&isp_clock CLK_ISP_SMMU_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE0>; + #iommu-cells = <0>; + }; + + sysmmu_fimc_lite1: sysmmu@123c0000 { + compatible = "samsung,exynos-sysmmu"; + reg = <0x123c0000 0x1000>; + interrupt-parent = <&combiner>; + interrupts = <16 1>; + power-domains = <&pd_isp>; + clock-names = "sysmmu", "master"; + clocks = <&isp_clock CLK_ISP_SMMU_LITE1>, + <&isp_clock CLK_ISP_FIMC_LITE1>; + #iommu-cells = <0>; + }; + }; +}; + +&combiner { + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; +}; + +&camera { + clocks = <&clock CLK_SCLK_CAM0>, <&clock CLK_SCLK_CAM1>, + <&clock CLK_PIXELASYNCM0>, <&clock CLK_PIXELASYNCM1>; + clock-names = "sclk_cam0", "sclk_cam1", "pxl_async0", "pxl_async1"; + + /* fimc_[0-3] are configured outside, under phandles */ + fimc_lite_0: fimc-lite@12390000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x12390000 0x1000>; + interrupts = ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>; + clock-names = "flite"; + iommus = <&sysmmu_fimc_lite0>; + status = "disabled"; + }; + + fimc_lite_1: fimc-lite@123a0000 { + compatible = "samsung,exynos4212-fimc-lite"; + reg = <0x123a0000 0x1000>; + interrupts = ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; + clock-names = "flite"; + iommus = <&sysmmu_fimc_lite1>; + status = "disabled"; + }; + + fimc_is: fimc-is@12000000 { + compatible = "samsung,exynos4212-fimc-is"; + reg = <0x12000000 0x260000>; + interrupts = , + ; + power-domains = <&pd_isp>; + clocks = <&isp_clock CLK_ISP_FIMC_LITE0>, + <&isp_clock CLK_ISP_FIMC_LITE1>, + <&isp_clock CLK_ISP_PPMUISPX>, + <&isp_clock CLK_ISP_PPMUISPMX>, + <&isp_clock CLK_ISP_FIMC_ISP>, + <&isp_clock CLK_ISP_FIMC_DRC>, + <&isp_clock CLK_ISP_FIMC_FD>, + <&isp_clock CLK_ISP_MCUISP>, + <&isp_clock CLK_ISP_GICISP>, + <&isp_clock CLK_ISP_MCUCTL_ISP>, + <&isp_clock CLK_ISP_PWM_ISP>, + <&isp_clock CLK_ISP_DIV_ISP0>, + <&isp_clock CLK_ISP_DIV_ISP1>, + <&isp_clock CLK_ISP_DIV_MCUISP0>, + <&isp_clock CLK_ISP_DIV_MCUISP1>, + <&clock CLK_MOUT_MPLL_USER_T>, + <&clock CLK_ACLK200>, + <&clock CLK_ACLK400_MCUISP>, + <&clock CLK_DIV_ACLK200>, + <&clock CLK_DIV_ACLK400_MCUISP>, + <&clock CLK_UART_ISP_SCLK>; + clock-names = "lite0", "lite1", "ppmuispx", + "ppmuispmx", "isp", + "drc", "fd", "mcuisp", + "gicisp", "mcuctl_isp", "pwm_isp", + "ispdiv0", "ispdiv1", "mcuispdiv0", + "mcuispdiv1", "mpll", "aclk200", + "aclk400mcuisp", "div_aclk200", + "div_aclk400mcuisp", "uart"; + iommus = <&sysmmu_fimc_isp>, <&sysmmu_fimc_drc>, + <&sysmmu_fimc_fd>, <&sysmmu_fimc_mcuctl>; + iommu-names = "isp", "drc", "fd", "mcuctl"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + status = "disabled"; + + pmu@10020000 { + reg = <0x10020000 0x3000>; + }; + + i2c1_isp: i2c-isp@12140000 { + compatible = "samsung,exynos4212-i2c-isp"; + reg = <0x12140000 0x100>; + clocks = <&isp_clock CLK_ISP_I2C1_ISP>; + clock-names = "i2c_isp"; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&exynos_usbphy { + compatible = "samsung,exynos4x12-usb2-phy"; + samsung,sysreg-phandle = <&sys_reg>; +}; + +&fimc_0 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; +}; + +&fimc_1 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,cam-if; +}; + +&fimc_2 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <4224 8192 1920 4224>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; + samsung,cam-if; +}; + +&fimc_3 { + compatible = "samsung,exynos4212-fimc"; + samsung,pix-limits = <1920 8192 1366 1920>; + samsung,rotators = <0>; + samsung,mainscaler-ext; + samsung,isp-wb; + samsung,lcd-wb; +}; + +&gpu { + interrupts = , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "gp", + "gpmmu", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3", + "pmu"; + operating-points-v2 = <&gpu_opp_table>; + + gpu_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <875000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <900000>; + }; + opp-350000000 { + opp-hz = /bits/ 64 <350000000>; + opp-microvolt = <950000>; + }; + opp-440000000 { + opp-hz = /bits/ 64 <440000000>; + opp-microvolt = <1025000>; + }; + }; +}; + +&hdmi { + compatible = "samsung,exynos4212-hdmi"; +}; + +&jpeg_codec { + compatible = "samsung,exynos4212-jpeg"; +}; + +&rotator { + compatible = "samsung,exynos4212-rotator"; +}; + +&mixer { + compatible = "samsung,exynos4212-mixer"; + clock-names = "mixer", "hdmi", "sclk_hdmi", "vp"; + clocks = <&clock CLK_MIXER>, <&clock CLK_HDMI>, + <&clock CLK_SCLK_HDMI>, <&clock CLK_VP>; + interconnects = <&bus_display &bus_dmc>; +}; + +&pmu_system_controller { + clock-names = "clkout0", "clkout1", "clkout2", "clkout3", + "clkout4", "clkout8", "clkout9"; + clocks = <&clock CLK_OUT_DMC>, <&clock CLK_OUT_TOP>, + <&clock CLK_OUT_LEFTBUS>, <&clock CLK_OUT_RIGHTBUS>, + <&clock CLK_OUT_CPU>, <&clock CLK_XXTI>, <&clock CLK_XUSBXTI>; + #clock-cells = <1>; +}; + +&tmu { + compatible = "samsung,exynos4412-tmu"; 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[83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:56 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 10/12] ARM: dts: Re-introduce Exynos4212 DTSI Date: Sun, 16 Apr 2023 15:34:20 +0200 Message-Id: <20230416133422.1949-11-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 The DTSI file was originally dropped in commit bca9085e0ae9 ("ARM: dts: exynos: remove Exynos4212 support (dead code)"), as there were no boards using it. We will be adding a device that uses it, so add it back. Signed-off-by: Artur Weber --- arch/arm/boot/dts/exynos4212.dtsi | 157 ++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4212.dtsi diff --git a/arch/arm/boot/dts/exynos4212.dtsi b/arch/arm/boot/dts/exynos4212.dtsi new file mode 100644 index 000000000000..9261c14a4489 --- /dev/null +++ b/arch/arm/boot/dts/exynos4212.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 SoC device tree source + * + * Copyright (c) 2012 Samsung Electronics Co., Ltd. + * http://www.samsung.com + * + * Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212 + * based board files can include this file and provide values for board specfic + * bindings. + * + * Note: This file does not include device nodes for all the controllers in + * Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional + * nodes can be added to this file. + */ + +#include "exynos4x12.dtsi" + +/ { + compatible = "samsung,exynos4212", "samsung,exynos4"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + }; + }; + + cpu0: cpu@a00 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa00>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@a01 { + device_type = "cpu"; + compatible = "arm,cortex-a9"; + reg = <0xa01>; + clocks = <&clock CLK_ARM_CLK>; + clock-names = "cpu"; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; /* min followed by max */ + }; + }; + + cpu0_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000>; + clock-latency-ns = <200000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <925000>; + clock-latency-ns = <200000>; + }; + opp-500000000 { + opp-hz = /bits/ 64 <500000000>; + opp-microvolt = <950000>; + clock-latency-ns = <200000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <975000>; + clock-latency-ns = <200000>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <987500>; + clock-latency-ns = <200000>; + }; + opp-800000000 { + opp-hz = /bits/ 64 <800000000>; + opp-microvolt = <1000000>; + clock-latency-ns = <200000>; + opp-suspend; + }; + opp-900000000 { + opp-hz = /bits/ 64 <900000000>; + opp-microvolt = <1037500>; + clock-latency-ns = <200000>; + }; + opp-1000000000 { + opp-hz = /bits/ 64 <1000000000>; + opp-microvolt = <1087500>; + clock-latency-ns = <200000>; + }; + opp-1100000000 { + opp-hz = /bits/ 64 <1100000000>; + opp-microvolt = <1137500>; + clock-latency-ns = <200000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <1187500>; + clock-latency-ns = <200000>; + }; + opp-1300000000 { + opp-hz = /bits/ 64 <1300000000>; + opp-microvolt = <1250000>; + clock-latency-ns = <200000>; + }; + opp-1400000000 { + opp-hz = /bits/ 64 <1400000000>; + opp-microvolt = <1287500>; + clock-latency-ns = <200000>; + }; + cpu0_opp_1500: opp-1500000000 { + opp-hz = /bits/ 64 <1500000000>; + opp-microvolt = <1350000>; + clock-latency-ns = <200000>; + turbo-mode; + }; + }; +}; + +&clock { + compatible = "samsung,exynos4212-clock"; +}; + +&combiner { + samsung,combiner-nr = <18>; +}; + +&gic { + cpu-offset = <0x8000>; +}; + +&pmu { + interrupts = <2 2>, <3 2>; + interrupt-affinity = <&cpu0>, <&cpu1>; + status = "okay"; +}; + +&pmu_system_controller { + compatible = "samsung,exynos4212-pmu", "syscon"; +}; From patchwork Sun Apr 16 13:34:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212979 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 593D0C77B77 for ; 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[83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:35:58 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 11/12] dt-bindings: arm: samsung: Add Samsung Galaxy Tab3 family boards Date: Sun, 16 Apr 2023 15:34:21 +0200 Message-Id: <20230416133422.1949-12-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 Add the compatible strings for the Samsung Galaxy Tab 3 8.0 series of tablets. Signed-off-by: Artur Weber --- .../bindings/arm/samsung/samsung-boards.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index deb2cf971871..4ee026e7f7ad 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -104,6 +104,16 @@ properties: - const: samsung,exynos4412 - const: samsung,exynos4 + - description: Samsung Tab3 family boards + items: + - enum: + - samsung,t310 # Samsung Galaxy Tab 3 8.0 WiFi (SM-T310) + - samsung,t311 # Samsung Galaxy Tab 3 8.0 3G (SM-T311) + - samsung,t315 # Samsung Galaxy Tab 3 8.0 LTE (SM-T315) + - const: samsung,tab3 + - const: samsung,exynos4212 + - const: samsung,exynos4 + - description: Exynos5250 based boards items: - enum: From patchwork Sun Apr 16 13:34:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Artur Weber X-Patchwork-Id: 13212981 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 1E207C77B61 for ; Sun, 16 Apr 2023 13:36:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 09391C4339E; Sun, 16 Apr 2023 13:36:06 +0000 (UTC) Received: from mail-ej1-f65.google.com (mail-ej1-f65.google.com [209.85.218.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 6C27EC433EF; Sun, 16 Apr 2023 13:36:03 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 6C27EC433EF Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-ej1-f65.google.com with SMTP id dm2so57578650ejc.8; Sun, 16 Apr 2023 06:36:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681652161; x=1684244161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NEstScdC/T/ToWMfwjiR2JvGLVx9qSGkPzA8VP0t1N8=; b=Seu78VrMOfFaNG6til/hoE27i5vcj8WDnLI467Gmb/hQ5kgZmkrNfZBd+DGljRiUFw +PYC2dJocNeEsSKEPRbqc3f+Ae4i0R5hjVbQDRx8EczFt6OmfD20LLC0IODqphEqz2V9 eU7OQBS+ktaS7wXe2oj/txJo23sCG+gLB8FhnqbocOOz46DCIGO3wU8yxL/CwKsGr5N0 sHJS+cPBCV1CDO0Y741bfG5GBpCRWAk/D0ZjW5D2HZu/sSOX12Jr2cncWHDBgyOkEMqB 5QsiQoVKbKBZWnJ7xWoHoul+Dn26RgUUUh21ddxUGUefJBAgu7fbxOMBKSX/Y270DKlH ud4w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681652161; x=1684244161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NEstScdC/T/ToWMfwjiR2JvGLVx9qSGkPzA8VP0t1N8=; b=Eh9XYL9X3+CGuzo0vr+OG2kfhqCtUJKXE3X+uRvIDmODQtwpxaNIBX1rH2HfJreqai +lYsR43hUTTF9VYqRFhp+RAWLudkVE8P/bU4XMss3+5oCLbJTGEO6/LohMB2BSc7dCGy dj/r6BttS89XdHY1TvDf7I/nJ/0dZCTe9Qcjmo1w1jmdsfIcNg75c+mMcFKPOzLwmV0I sPAooLObzycv7sCb+kQE3gwYmA7ZTiYQ3XoirSjN1y82xPsTHQbi52YxxwC200SjCPf/ tQ2tbZP/calViaugodt8bny/QFmoJLgBjmUTM/esA+vqs19oOZgDKTUcnNPxs2p3Jjat C0Ig== X-Gm-Message-State: AAQBX9fPJh/ABAY9OfIkxTN5+c2j5pIOdFuL02EnJvxabNY0w6G/xn2C VHFk39deT2dxsUrhlWNrcaI= X-Google-Smtp-Source: AKy350YuMMevGG64KSa71jyQz9R8NLZah82rGb2f//1Jnr6iJz8A5Q5uX5ut3tOuYjOQzhHRn8eujw== X-Received: by 2002:a17:906:f14f:b0:94e:3d6f:9c0f with SMTP id gw15-20020a170906f14f00b0094e3d6f9c0fmr4523226ejb.55.1681652161396; Sun, 16 Apr 2023 06:36:01 -0700 (PDT) Received: from localhost.my.domain (83.8.121.70.ipv4.supernova.orange.pl. [83.8.121.70]) by smtp.gmail.com with ESMTPSA id gn23-20020a1709070d1700b009373f1b5c4esm5122958ejc.161.2023.04.16.06.35.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 06:36:00 -0700 (PDT) From: Artur Weber To: Krzysztof Kozlowski List-Id: Cc: Alim Akhtar , Rob Herring , Sylwester Nawrocki , Tomasz Figa , Chanwoo Choi , Michael Turquette , Stephen Boyd , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King , Daniel Lezcano , Kukjin Kim , Mauro Carvalho Chehab , Vinod Koul , Kishon Vijay Abraham I , linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-pm@vger.kernel.org, linux-media@vger.kernel.org, linux-phy@lists.infradead.org, ~postmarketos/upstreaming@lists.sr.ht, Artur Weber Subject: [PATCH v2 12/12] ARM: dts: exynos: Add Samsung Galaxy Tab 3 8.0 boards Date: Sun, 16 Apr 2023 15:34:22 +0200 Message-Id: <20230416133422.1949-13-aweber.kernel@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230416133422.1949-1-aweber.kernel@gmail.com> References: <20230416133422.1949-1-aweber.kernel@gmail.com> MIME-Version: 1.0 Introduce support for the Galaxy Tab 3 8.0 series of boards: - Samsung Galaxy Tab 3 8.0 WiFi (SM-T310/lt01wifi) - Samsung Galaxy Tab 3 8.0 3G (SM-T311/lt013g) - Samsung Galaxy Tab 3 8.0 LTE (SM-T315/lt01lte) What works: - Display and backlight - Touchscreen (without touchkeys) - GPIO buttons, hall sensor - WiFi and Bluetooth - USB, fuel gauge, charging (partial) - Accelerometer and magnetometer - WiFi model only: light sensor Signed-off-by: Artur Weber --- Display panel bindings are added by a separate patchset: "[PATCH 0/3] Add Samsung S6D7AA0 panel controller driver"[1] [1] https://lore.kernel.org/all/20230416131632.31673-1-aweber.kernel@gmail.com/ --- arch/arm/boot/dts/Makefile | 3 + arch/arm/boot/dts/exynos4212-tab3-3g8.dts | 30 + arch/arm/boot/dts/exynos4212-tab3-lte8.dts | 43 + arch/arm/boot/dts/exynos4212-tab3-wifi8.dts | 25 + arch/arm/boot/dts/exynos4212-tab3.dtsi | 1175 +++++++++++++++++++ 5 files changed, 1276 insertions(+) create mode 100644 arch/arm/boot/dts/exynos4212-tab3-3g8.dts create mode 100644 arch/arm/boot/dts/exynos4212-tab3-lte8.dts create mode 100644 arch/arm/boot/dts/exynos4212-tab3-wifi8.dts create mode 100644 arch/arm/boot/dts/exynos4212-tab3.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index efe4152e5846..e5f63b636637 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -217,6 +217,9 @@ dtb-$(CONFIG_ARCH_EXYNOS4) += \ exynos4210-smdkv310.dtb \ exynos4210-trats.dtb \ exynos4210-universal_c210.dtb \ + exynos4212-tab3-3g8.dtb \ + exynos4212-tab3-lte8.dtb \ + exynos4212-tab3-wifi8.dtb \ exynos4412-i9300.dtb \ exynos4412-i9305.dtb \ exynos4412-itop-elite.dtb \ diff --git a/arch/arm/boot/dts/exynos4212-tab3-3g8.dts b/arch/arm/boot/dts/exynos4212-tab3-3g8.dts new file mode 100644 index 000000000000..c503a2d351dd --- /dev/null +++ b/arch/arm/boot/dts/exynos4212-tab3-3g8.dts @@ -0,0 +1,30 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 based Galaxy Tab 3 8.0 WiFi board device tree + * source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4212-tab3.dtsi" + +/ { + model = "Samsung Galaxy Tab 3 8.0 3G (SM-T311) based on Exynos4212"; + compatible = "samsung,t311", "samsung,tab3", "samsung,exynos4212", "samsung,exynos4"; + chassis-type = "tablet"; +}; + +/* Pin control sleep state overrides */ + +&sleep0 { + PIN_SLP(gpb-5, INPUT, UP); +}; + +&sleep1 { + PIN_SLP(gpl0-0, OUT0, NONE); + PIN_SLP(gpl1-0, OUT0, NONE); + PIN_SLP(gpl2-4, OUT0, NONE); + PIN_SLP(gpm3-3, OUT1, NONE); +}; diff --git a/arch/arm/boot/dts/exynos4212-tab3-lte8.dts b/arch/arm/boot/dts/exynos4212-tab3-lte8.dts new file mode 100644 index 000000000000..158c6a2e24bf --- /dev/null +++ b/arch/arm/boot/dts/exynos4212-tab3-lte8.dts @@ -0,0 +1,43 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 based Galaxy Tab 3 8.0 WiFi board device tree + * source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4212-tab3.dtsi" + +/ { + model = "Samsung Galaxy Tab 3 8.0 LTE (SM-T315) based on Exynos4212"; + compatible = "samsung,t315", "samsung,tab3", "samsung,exynos4212", "samsung,exynos4"; + chassis-type = "tablet"; +}; + +&sleep0 { + PIN_SLP(gpa0-4, INPUT, UP); + PIN_SLP(gpa0-5, INPUT, UP); + + PIN_SLP(gpb-5, INPUT, UP); + + PIN_SLP(gpc0-0, PREV, NONE); + PIN_SLP(gpc1-3, INPUT, NONE); + + PIN_SLP(gpf1-6, INPUT, NONE); + PIN_SLP(gpf2-2, PREV, NONE); +}; + +&sleep1 { + PIN_SLP(gpl0-0, PREV, NONE); + + PIN_SLP(gpl1-0, PREV, NONE); + + PIN_SLP(gpl2-1, INPUT, DOWN); + PIN_SLP(gpl2-2, INPUT, DOWN); + PIN_SLP(gpl2-4, OUT0, NONE); + PIN_SLP(gpl2-5, PREV, NONE); + + PIN_SLP(gpm3-3, OUT1, NONE); +}; diff --git a/arch/arm/boot/dts/exynos4212-tab3-wifi8.dts b/arch/arm/boot/dts/exynos4212-tab3-wifi8.dts new file mode 100644 index 000000000000..0527a75710d8 --- /dev/null +++ b/arch/arm/boot/dts/exynos4212-tab3-wifi8.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 based Galaxy Tab 3 8.0 WiFi board device tree + * source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4212-tab3.dtsi" + +/ { + model = "Samsung Galaxy Tab 3 8.0 WiFi (SM-T310) based on Exynos4212"; + compatible = "samsung,t310", "samsung,tab3", "samsung,exynos4212", "samsung,exynos4"; + chassis-type = "tablet"; +}; + +&i2c_lightsensor { + /* Capella Micro CM3323 color light sensor */ + colorsensor@10 { + compatible = "capella,cm3323"; + reg = <0x10>; + }; +}; diff --git a/arch/arm/boot/dts/exynos4212-tab3.dtsi b/arch/arm/boot/dts/exynos4212-tab3.dtsi new file mode 100644 index 000000000000..b8ad5497506c --- /dev/null +++ b/arch/arm/boot/dts/exynos4212-tab3.dtsi @@ -0,0 +1,1175 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung's Exynos4212 based Galaxy Tab 3 board common source + * + * Copyright (c) 2013 Samsung Electronics Co., Ltd. + * http://www.samsung.com + */ + +/dts-v1/; +#include "exynos4212.dtsi" +#include "exynos4412-ppmu-common.dtsi" +#include "exynos-mfc-reserved-memory.dtsi" +#include +#include +#include +#include +#include +#include "exynos-pinctrl.h" + +/ { + compatible = "samsung,tab3", "samsung,exynos4212", "samsung,exynos4"; + + memory@40000000 { + device_type = "memory"; + + /* Technically 2GB, but last 1GB is flaky, so we ignore it for now */ + reg = <0x40000000 0x3FC00000>; + }; + + chosen { + stdout-path = &serial_2; + + /* Default S-BOOT bootloader loads initramfs here */ + linux,initrd-start = <0x42000000>; + linux,initrd-end = <0x42800000>; + }; + + firmware@204f000 { + compatible = "samsung,secure-firmware"; + reg = <0x0204F000 0x1000>; + }; + + fixed-rate-clocks { + xxti { + compatible = "samsung,clock-xxti"; + clock-frequency = <0>; + }; + + xusbxti { + compatible = "samsung,clock-xusbxti"; + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-power { + gpios = <&gpx2 7 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "power"; + debounce-interval = <10>; + wakeup-source; + }; + + key-up { + gpios = <&gpx2 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume down"; + debounce-interval = <10>; + }; + + key-down { + gpios = <&gpx3 3 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "volume up"; + debounce-interval = <10>; + }; + + key-home { + gpios = <&gpx1 2 GPIO_ACTIVE_LOW>; + linux,code = ; + label = "home"; + debounce-interval = <10>; + }; + + switch-hall-sensor { + gpios = <&gpx2 4 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + label = "hall effect sensor"; + debounce-interval = <10>; + wakeup-source; + }; + }; + + vbatt_reg: voltage-regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "VBATT"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; + + backlight_reset_supply: voltage-regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "BACKLIGHT_ENVDDIO"; + pinctrl-names = "default"; + pinctrl-0 = <&backlight_reset>; + gpio = <&gpm0 1 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + lcd_enable_supply: voltage-regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "LCD_VDD_2.2V"; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_en>; + gpio = <&gpc0 1 GPIO_ACTIVE_HIGH>; /* LCD_EN */ + enable-active-high; + }; + + i2c_max77693: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm2 0 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm2 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + pmic@66 { + compatible = "maxim,max77693"; + interrupt-parent = <&gpx1>; + interrupts = <5 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_irq>; + reg = <0x66>; + + regulators { + esafeout1_reg: ESAFEOUT1 { + regulator-name = "ESAFEOUT1"; + regulator-boot-on; + }; + + esafeout2_reg: ESAFEOUT2 { + regulator-name = "ESAFEOUT2"; + }; + + charger_reg: CHARGER { + regulator-name = "CHARGER"; + regulator-min-microamp = <60000>; + regulator-max-microamp = <2580000>; + regulator-boot-on; + }; + }; + + charger { + compatible = "maxim,max77693-charger"; + + maxim,constant-microvolt = <4350000>; + maxim,min-system-microvolt = <3600000>; + maxim,thermal-regulation-celsius = <100>; + maxim,battery-overcurrent-microamp = <3500000>; + maxim,charge-input-threshold-microvolt = <4300000>; + }; + }; + }; + + i2c_max77693_fuel: i2c-gpio-2 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy0 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + fuel-gauge@36 { + compatible = "maxim,max17050"; + interrupt-parent = <&gpx2>; + interrupts = <3 IRQ_TYPE_EDGE_FALLING>; + pinctrl-names = "default"; + pinctrl-0 = <&max77693_fuel_irq>; + reg = <0x36>; + + maxim,over-heat-temp = <500>; + maxim,over-volt = <4500>; + }; + }; + + i2c_yas532_magnetometer: i2c-gpio-3 { + compatible = "i2c-gpio"; + sda-gpios = <&gpy2 4 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpy2 5 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* Magnetometer: Yamaha YAS532 */ + magnetometer@2e { + compatible = "yamaha,yas532"; + reg = <0x2e>; + iovdd-supply = <&ldo3_reg>; /* VCC_1.8V_AP */ + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; + }; + + i2c_lightsensor: i2c-gpio-4 { + compatible = "i2c-gpio"; + sda-gpios = <&gpl0 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpl0 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* WiFi model uses CM3323, 3G/LTE use CM36653 */ + }; + + i2c_bl: i2c-gpio-24 { + compatible = "i2c-gpio"; + sda-gpios = <&gpm4 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpm4 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + backlight: backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + status = "okay"; + + bl-name = "lcd-bl"; + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x78>; /* 120 */ + + power-supply = <&vbatt_reg>; + enable-supply = <&backlight_reset_supply>; + + pwms = <&pwm 1 78770 0>; + pwm-names = "lp8556"; + pwm-period = <78770>; + + rom_a3h { + rom-addr = /bits/ 8 <0xa3>; + rom-val = /bits/ 8 <0x5e>; + }; + + rom_a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x34>; + }; + + rom_a7h { + rom-addr = /bits/ 8 <0xa7>; + rom-val = /bits/ 8 <0xfa>; + }; + }; + }; + + wlan_pwrseq: sdhci3-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpm3 5 GPIO_ACTIVE_LOW>; + }; +}; + +&bus_dmc { + devfreq-events = <&ppmu_dmc0_3>, <&ppmu_dmc1_3>; + vdd-supply = <&buck1_reg>; + status = "okay"; +}; + +&bus_acp { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_c2c { + devfreq = <&bus_dmc>; + status = "okay"; +}; + +&bus_leftbus { + devfreq-events = <&ppmu_leftbus_3>, <&ppmu_rightbus_3>; + vdd-supply = <&buck3_reg>; + status = "okay"; +}; + +&bus_rightbus { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_display { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_fsys { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_peri { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&bus_mfc { + devfreq = <&bus_leftbus>; + status = "okay"; +}; + +&cpu0 { + cpu0-supply = <&buck2_reg>; +}; + +&dsi_0 { + vddcore-supply = <&ldo8_reg>; + vddio-supply = <&ldo10_reg>; + samsung,burst-clock-frequency = <500000000>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <24000000>; + status = "okay"; + + panel@0 { + compatible = "samsung,s6d7aa0-lsl080al02"; + reg = <0>; + enable-supply = <&lcd_enable_supply>; + pinctrl-names = "default"; + pinctrl-0 = <&lcd_nrst>; + reset-gpios = <&gpf0 4 GPIO_ACTIVE_LOW>; + backlight = <&backlight>; + }; +}; + +&exynos_usbphy { + vbus-supply = <&esafeout1_reg>; + status = "okay"; +}; + +&fimd { + status = "okay"; +}; + +&gpu { + mali-supply = <&buck4_reg>; + status = "okay"; +}; + +&hsotg { + vusb_d-supply = <&ldo15_reg>; + vusb_a-supply = <&ldo12_reg>; + dr_mode = "peripheral"; + status = "okay"; +}; + +/* Accelerometer: K2DH/K3DH */ +&i2c_1 { + pinctrl-0 = <&i2c1_bus>; + pinctrl-names = "default"; + status = "okay"; + + lis3dh: accelerometer@19 { + /* K2DH seems to be the same as lis2dh12 in terms of registers */ + compatible = "st,lis2dh12-accel"; + reg = <0x19>; + + interrupt-parent = <&gpx0>; + interrupts = <0 IRQ_TYPE_EDGE_FALLING>; + + vdd-supply = <&ldo17_reg>; /* VCC_2.8V_AP */ + vddio-supply = <&ldo3_reg>; /* VCC_1.8V_AP */ + + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "-1"; + }; +}; + +/* Touchscreen: MMS252 */ +&i2c_3 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <400000>; + pinctrl-0 = <&i2c3_bus>; + pinctrl-names = "default"; + status = "okay"; + + touchscreen@48 { + /* Using mms114 compatible for now */ + compatible = "melfas,mms114"; + reg = <0x48>; + interrupt-parent = <&gpb>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; + touchscreen-size-x = <800>; + touchscreen-size-y = <1280>; + avdd-supply = <&ldo21_reg>; + vdd-supply = <&ldo25_reg>; + }; +}; + +/* PMIC: s5m8767 */ +&i2c_7 { + samsung,i2c-sda-delay = <100>; + samsung,i2c-slave-addr = <0x10>; + samsung,i2c-max-bus-freq = <100000>; + pinctrl-0 = <&i2c7_bus>; + pinctrl-names = "default"; + status = "okay"; + + s5m8767: pmic@66 { + compatible = "samsung,s5m8767-pmic"; + reg = <0x66>; + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&s5m8767_irq &s5m8767_dvs &s5m8767_ds>; + wakeup-source; + + s5m8767,pmic-buck2-ramp-enable; + s5m8767,pmic-buck3-ramp-enable; + s5m8767,pmic-buck4-ramp-enable; + + s5m8767,pmic-buck-ramp-delay = <25>; + s5m8767,pmic-buck-default-dvs-idx = <1>; + + s5m8767,pmic-buck-dvs-gpios = <&gpm3 0 GPIO_ACTIVE_HIGH>, + <&gpm3 1 GPIO_ACTIVE_HIGH>, + <&gpm3 2 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck-ds-gpios = <&gpf3 1 GPIO_ACTIVE_HIGH>, + <&gpf3 2 GPIO_ACTIVE_HIGH>, + <&gpf3 3 GPIO_ACTIVE_HIGH>; + + s5m8767,pmic-buck2-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>; + + s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>; + + s5m8767,pmic-buck4-dvs-voltage = <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>, + <1100000>, <1100000>; + + regulators { + ldo1_reg: LDO1 { + regulator-name = "VALIVE_1.0V_AP"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo2_reg: LDO2 { + regulator-name = "VM1M2_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + ldo3_reg: LDO3 { + regulator-name = "VCC_1.8V_AP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + op_mode = <1>; + }; + + ldo5_reg: LDO5 { + regulator-name = "VCC_3.3V_MHL"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo8_reg: LDO8 { + regulator-name = "VMIPI_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + op_mode = <3>; + }; + + ldo9_reg: LDO9 { + regulator-name = "VSIL_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; + }; + + ldo10_reg: LDO10 { + regulator-name = "VMIPI_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <3>; + }; + + ldo12_reg: LDO12 { + regulator-name = "VUOTG_3.0V"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + op_mode = <1>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VCC_1.8V_MHL"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + ldo15_reg: LDO15 { + regulator-name = "VHSIC_1.0V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + op_mode = <1>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + regulator-name = "VCC_2.8V_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + regulator-always-on; + }; + + ldo19_reg: LDO19 { + regulator-name = "VLED_IC_1.9V"; + regulator-min-microvolt = <1900000>; + regulator-max-microvolt = <1900000>; + op_mode = <1>; + regulator-always-on; + }; + + ldo20_reg: LDO20 { + regulator-name = "VTOUCH_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo21_reg: LDO21 { + regulator-name = "TSP_VDD_3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + op_mode = <1>; + }; + + ldo22_reg: LDO22 { + regulator-name = "5M_AF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo23_reg: LDO23 { + regulator-name = "VTF_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <3>; + }; + + ldo24_reg: LDO24 { + regulator-name = "LEDA_2.8V"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + op_mode = <1>; + }; + + ldo25_reg: LDO25 { + regulator-name = "TSP_VDD_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + ldo26_reg: LDO26 { + regulator-name = "CAM_IO_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + ldo27_reg: LDO27 { + regulator-name = "VTCAM_1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + op_mode = <1>; + }; + + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + op_mode = <3>; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1150000>; + regulator-boot-on; + op_mode = <3>; + }; + + buck5_reg: BUCK5 { + regulator-name = "VMEM_1.2V_AP"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + op_mode = <1>; + }; + + buck6_reg: BUCK6 { + regulator-name = "CAM_ISP_CORE_1.2V"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + op_mode = <1>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + + s5m8767_osc: clocks { + compatible = "samsung,s5m8767-clk"; + #clock-cells = <1>; + clock-output-names = "en32khz_ap", + "en32khz_cp", + "en32khz_bt"; + }; + }; +}; + +&mshc_0 { + broken-cd; + non-removable; + card-detect-delay = <200>; + vmmc-supply = <&ldo22_reg>; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <0>; + samsung,dw-mshc-sdr-timing = <2 3>; + samsung,dw-mshc-ddr-timing = <1 2>; + pinctrl-0 = <&sd4_clk &sd4_cmd &sd4_bus4 &sd4_bus8>; + pinctrl-names = "default"; + status = "okay"; + bus-width = <8>; + cap-mmc-highspeed; +}; + +&pinctrl_0 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep0>; + + s5m8767_ds: s5m8767-ds { + samsung,pins = "gpf3-1", "gpf3-2", "gpf3-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + lcd_en: lcd-en { + samsung,pins = "gpc0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + lcd_nrst: lcd-nrst { + samsung,pins = "gpf0-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + sleep0: sleep-state { + PIN_SLP(gpa0-0, INPUT, NONE); + PIN_SLP(gpa0-1, OUT0, NONE); + PIN_SLP(gpa0-2, INPUT, NONE); + PIN_SLP(gpa0-3, INPUT, UP); + PIN_SLP(gpa0-4, INPUT, DOWN); /* UP on LTE model */ + PIN_SLP(gpa0-5, INPUT, DOWN); /* UP on LTE model */ + PIN_SLP(gpa0-6, INPUT, DOWN); + PIN_SLP(gpa0-7, INPUT, DOWN); + + PIN_SLP(gpa1-0, INPUT, DOWN); + PIN_SLP(gpa1-1, INPUT, DOWN); + PIN_SLP(gpa1-2, INPUT, DOWN); + PIN_SLP(gpa1-3, INPUT, DOWN); + PIN_SLP(gpa1-4, INPUT, DOWN); + PIN_SLP(gpa1-5, INPUT, DOWN); + + PIN_SLP(gpb-0, INPUT, NONE); + PIN_SLP(gpb-1, INPUT, NONE); + PIN_SLP(gpb-2, INPUT, NONE); + PIN_SLP(gpb-3, INPUT, NONE); + PIN_SLP(gpb-4, INPUT, DOWN); + PIN_SLP(gpb-5, INPUT, DOWN); /* UP on all models with modem */ + PIN_SLP(gpb-6, INPUT, DOWN); + PIN_SLP(gpb-7, INPUT, DOWN); + + PIN_SLP(gpc0-0, INPUT, DOWN); /* PREV, NONE on LTE model */ + PIN_SLP(gpc0-1, INPUT, DOWN); + PIN_SLP(gpc0-2, INPUT, DOWN); + PIN_SLP(gpc0-3, INPUT, DOWN); + PIN_SLP(gpc0-4, INPUT, DOWN); + + PIN_SLP(gpc1-0, INPUT, DOWN); + PIN_SLP(gpc1-1, INPUT, DOWN); + PIN_SLP(gpc1-2, INPUT, DOWN); + PIN_SLP(gpc1-3, INPUT, DOWN); /* NONE on LTE model */ + PIN_SLP(gpc1-4, INPUT, DOWN); + + PIN_SLP(gpd0-0, INPUT, DOWN); + PIN_SLP(gpd0-1, OUT0, NONE); + PIN_SLP(gpd0-2, INPUT, NONE); + PIN_SLP(gpd0-3, INPUT, NONE); + + PIN_SLP(gpd1-0, INPUT, DOWN); + PIN_SLP(gpd1-1, INPUT, DOWN); + PIN_SLP(gpd1-2, INPUT, NONE); + PIN_SLP(gpd1-3, INPUT, NONE); + + PIN_SLP(gpf0-0, INPUT, DOWN); + PIN_SLP(gpf0-1, INPUT, DOWN); + PIN_SLP(gpf0-2, INPUT, DOWN); + PIN_SLP(gpf0-3, INPUT, DOWN); + PIN_SLP(gpf0-4, OUT0, NONE); + PIN_SLP(gpf0-5, OUT0, NONE); + PIN_SLP(gpf0-6, INPUT, DOWN); + PIN_SLP(gpf0-7, INPUT, DOWN); + + PIN_SLP(gpf1-0, INPUT, DOWN); + PIN_SLP(gpf1-1, INPUT, DOWN); + PIN_SLP(gpf1-2, INPUT, DOWN); + PIN_SLP(gpf1-3, INPUT, DOWN); + PIN_SLP(gpf1-4, INPUT, DOWN); + PIN_SLP(gpf1-5, INPUT, DOWN); + PIN_SLP(gpf1-6, INPUT, DOWN); /* NONE on LTE model */ + PIN_SLP(gpf1-7, INPUT, DOWN); + + PIN_SLP(gpf2-0, INPUT, DOWN); + PIN_SLP(gpf2-1, INPUT, DOWN); + PIN_SLP(gpf2-2, INPUT, DOWN); /* PREV, NONE on LTE model */ + PIN_SLP(gpf2-3, INPUT, DOWN); + PIN_SLP(gpf2-4, INPUT, DOWN); + PIN_SLP(gpf2-5, INPUT, DOWN); + PIN_SLP(gpf2-6, INPUT, DOWN); + PIN_SLP(gpf2-7, INPUT, DOWN); + + PIN_SLP(gpf3-0, INPUT, DOWN); + PIN_SLP(gpf3-1, INPUT, DOWN); + PIN_SLP(gpf3-2, INPUT, DOWN); + PIN_SLP(gpf3-3, INPUT, DOWN); + PIN_SLP(gpf3-4, PREV, NONE); + PIN_SLP(gpf3-5, OUT0, DOWN); + + PIN_SLP(gpj0-0, INPUT, DOWN); + PIN_SLP(gpj0-1, INPUT, DOWN); + PIN_SLP(gpj0-2, INPUT, DOWN); + PIN_SLP(gpj0-3, OUT0, NONE); + PIN_SLP(gpj0-4, INPUT, DOWN); + PIN_SLP(gpj0-5, INPUT, DOWN); + PIN_SLP(gpj0-6, OUT0, NONE); + PIN_SLP(gpj0-7, OUT0, NONE); + + PIN_SLP(gpj1-0, OUT0, NONE); + PIN_SLP(gpj1-1, INPUT, DOWN); + PIN_SLP(gpj1-2, PREV, NONE); + PIN_SLP(gpj1-3, INPUT, DOWN); + PIN_SLP(gpj1-4, INPUT, DOWN); + }; +}; + +&pinctrl_1 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep1>; + + max77693_irq: max77693-irq { + samsung,pins = "gpx1-5"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + max77693_fuel_irq: max77693-fuel-irq { + samsung,pins = "gpx2-3"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + s5m8767_dvs: s5m8767-dvs { + samsung,pins = "gpm3-0", "gpm3-1", "gpm3-2"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + s5m8767_irq: s5m8767-irq { + samsung,pins = "gpx0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + sdhci2_cd: sdhci2-cd-irq { + samsung,pins = "gpx3-4"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + bt_shutdown: bt-shutdown-pins { + samsung,pins = "gpl0-6"; + samsung,pin-pud = ; + }; + + bt_host_wakeup: bt-host-wakeup-pins { + samsung,pins = "gpx2-6"; + samsung,pin-pud = ; + }; + + bt_device_wakeup: bt-device-wakeup-pins { + samsung,pins = "gpx3-1"; + samsung,pin-pud = ; + }; + + backlight_reset: backlight-reset { + samsung,pins = "gpm0-1"; + samsung,pin-function = ; + samsung,pin-pud = ; + }; + + gpio_keys: gpio-keys-pins { + samsung,pins = "gpx1-2", "gpx2-2", "gpx2-4", "gpx2-7", "gpx3-3"; + samsung,pin-pud = ; + }; + + sleep1: sleep-state { + PIN_SLP(gpk0-0, PREV, NONE); + PIN_SLP(gpk0-1, PREV, NONE); + PIN_SLP(gpk0-2, PREV, NONE); + PIN_SLP(gpk0-3, PREV, NONE); + PIN_SLP(gpk0-4, PREV, NONE); + PIN_SLP(gpk0-5, PREV, NONE); + PIN_SLP(gpk0-6, PREV, NONE); + + PIN_SLP(gpk1-0, INPUT, DOWN); + PIN_SLP(gpk1-1, INPUT, DOWN); + PIN_SLP(gpk1-2, INPUT, DOWN); + PIN_SLP(gpk1-3, PREV, NONE); + PIN_SLP(gpk1-4, PREV, NONE); + PIN_SLP(gpk1-5, PREV, NONE); + PIN_SLP(gpk1-6, PREV, NONE); + + PIN_SLP(gpk2-0, INPUT, DOWN); + PIN_SLP(gpk2-1, INPUT, DOWN); + PIN_SLP(gpk2-2, INPUT, DOWN); + PIN_SLP(gpk2-3, INPUT, DOWN); + PIN_SLP(gpk2-4, INPUT, DOWN); + PIN_SLP(gpk2-5, INPUT, DOWN); + PIN_SLP(gpk2-6, INPUT, DOWN); + + PIN_SLP(gpk3-0, OUT0, NONE); + PIN_SLP(gpk3-1, INPUT, NONE); + PIN_SLP(gpk3-2, INPUT, DOWN); + PIN_SLP(gpk3-3, INPUT, NONE); + PIN_SLP(gpk3-4, INPUT, NONE); + PIN_SLP(gpk3-5, INPUT, NONE); + PIN_SLP(gpk3-6, INPUT, NONE); + + PIN_SLP(gpl0-0, INPUT, DOWN); /* OUT0 on 3G, PREV on LTE; NONE on both */ + PIN_SLP(gpl0-1, INPUT, NONE); + PIN_SLP(gpl0-2, INPUT, NONE); + PIN_SLP(gpl0-3, INPUT, DOWN); + PIN_SLP(gpl0-4, INPUT, DOWN); + PIN_SLP(gpl0-6, PREV, NONE); + + PIN_SLP(gpl1-0, INPUT, DOWN); /* OUT0 on 3G, PREV on LTE; NONE on both */ + PIN_SLP(gpl1-1, OUT0, NONE); + PIN_SLP(gpl2-0, INPUT, DOWN); + PIN_SLP(gpl2-1, PREV, NONE); /* INPUT, DOWN on LTE */ + PIN_SLP(gpl2-2, PREV, NONE); /* INPUT, DOWN on LTE */ + PIN_SLP(gpl2-3, INPUT, DOWN); + PIN_SLP(gpl2-4, INPUT, DOWN); /* OUT0, NONE on models with modem */ + PIN_SLP(gpl2-5, INPUT, DOWN); /* PREV, NONE on LTE */ + PIN_SLP(gpl2-6, INPUT, DOWN); + PIN_SLP(gpl2-7, INPUT, DOWN); + + PIN_SLP(gpm0-0, PREV, NONE); + PIN_SLP(gpm0-1, OUT0, NONE); + PIN_SLP(gpm0-2, INPUT, DOWN); + PIN_SLP(gpm0-3, INPUT, DOWN); + PIN_SLP(gpm0-4, INPUT, DOWN); + PIN_SLP(gpm0-5, INPUT, DOWN); + PIN_SLP(gpm0-6, INPUT, DOWN); + PIN_SLP(gpm0-7, INPUT, DOWN); + + PIN_SLP(gpm1-0, INPUT, DOWN); + PIN_SLP(gpm1-1, INPUT, DOWN); + PIN_SLP(gpm1-2, INPUT, NONE); + PIN_SLP(gpm1-3, INPUT, NONE); + PIN_SLP(gpm1-4, INPUT, NONE); + PIN_SLP(gpm1-5, INPUT, NONE); + PIN_SLP(gpm1-6, OUT0, NONE); + + PIN_SLP(gpm2-0, INPUT, NONE); + PIN_SLP(gpm2-1, INPUT, NONE); + PIN_SLP(gpm2-2, OUT0, NONE); + PIN_SLP(gpm2-3, INPUT, DOWN); + PIN_SLP(gpm2-4, INPUT, DOWN); + + PIN_SLP(gpm3-0, PREV, NONE); + PIN_SLP(gpm3-1, PREV, NONE); + PIN_SLP(gpm3-2, PREV, NONE); + PIN_SLP(gpm3-3, INPUT, DOWN); /* OUT1, NONE for 3G */ + PIN_SLP(gpm3-4, INPUT, DOWN); + PIN_SLP(gpm3-5, PREV, NONE); + PIN_SLP(gpm3-6, INPUT, DOWN); + PIN_SLP(gpm3-7, OUT0, NONE); + + PIN_SLP(gpm4-0, INPUT, DOWN); + PIN_SLP(gpm4-1, INPUT, DOWN); + PIN_SLP(gpm4-2, INPUT, DOWN); + PIN_SLP(gpm4-3, INPUT, DOWN); + PIN_SLP(gpm4-4, PREV, NONE); + PIN_SLP(gpm4-5, INPUT, NONE); + PIN_SLP(gpm4-6, INPUT, DOWN); + PIN_SLP(gpm4-7, INPUT, DOWN); + + PIN_SLP(gpy0-0, INPUT, DOWN); + PIN_SLP(gpy0-1, INPUT, DOWN); + PIN_SLP(gpy0-2, INPUT, NONE); + PIN_SLP(gpy0-3, INPUT, NONE); + PIN_SLP(gpy0-4, INPUT, DOWN); + PIN_SLP(gpy0-5, INPUT, DOWN); + + PIN_SLP(gpy1-0, INPUT, DOWN); + PIN_SLP(gpy1-1, INPUT, DOWN); + PIN_SLP(gpy1-2, INPUT, DOWN); + PIN_SLP(gpy1-3, INPUT, DOWN); + + PIN_SLP(gpy2-0, PREV, NONE); + PIN_SLP(gpy2-1, INPUT, DOWN); + PIN_SLP(gpy2-2, INPUT, NONE); + PIN_SLP(gpy2-3, INPUT, NONE); + PIN_SLP(gpy2-4, INPUT, NONE); + PIN_SLP(gpy2-5, INPUT, NONE); + + PIN_SLP(gpy3-0, INPUT, DOWN); + PIN_SLP(gpy3-1, INPUT, DOWN); + PIN_SLP(gpy3-2, INPUT, DOWN); + PIN_SLP(gpy3-3, INPUT, DOWN); + PIN_SLP(gpy3-4, INPUT, DOWN); + PIN_SLP(gpy3-5, INPUT, DOWN); + PIN_SLP(gpy3-6, INPUT, DOWN); + PIN_SLP(gpy3-7, INPUT, DOWN); + + PIN_SLP(gpy4-0, INPUT, DOWN); + PIN_SLP(gpy4-1, INPUT, DOWN); + PIN_SLP(gpy4-2, INPUT, DOWN); + PIN_SLP(gpy4-3, INPUT, DOWN); + PIN_SLP(gpy4-4, INPUT, DOWN); + PIN_SLP(gpy4-5, INPUT, DOWN); + PIN_SLP(gpy4-6, INPUT, DOWN); + PIN_SLP(gpy4-7, INPUT, DOWN); + + PIN_SLP(gpy5-0, INPUT, DOWN); + PIN_SLP(gpy5-1, INPUT, DOWN); + PIN_SLP(gpy5-2, INPUT, DOWN); + PIN_SLP(gpy5-3, INPUT, DOWN); + PIN_SLP(gpy5-4, INPUT, DOWN); + PIN_SLP(gpy5-5, INPUT, DOWN); + PIN_SLP(gpy5-6, INPUT, DOWN); + PIN_SLP(gpy5-7, INPUT, DOWN); + + PIN_SLP(gpy6-0, INPUT, DOWN); + PIN_SLP(gpy6-1, INPUT, DOWN); + PIN_SLP(gpy6-2, INPUT, DOWN); + PIN_SLP(gpy6-3, INPUT, DOWN); + PIN_SLP(gpy6-4, INPUT, DOWN); + PIN_SLP(gpy6-5, INPUT, DOWN); + PIN_SLP(gpy6-6, INPUT, DOWN); + PIN_SLP(gpy6-7, INPUT, DOWN); + }; +}; + +&pinctrl_2 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep2>; + + sleep2: sleep-state { + PIN_SLP(gpz-0, INPUT, DOWN); + PIN_SLP(gpz-1, INPUT, DOWN); + PIN_SLP(gpz-2, INPUT, DOWN); + PIN_SLP(gpz-3, INPUT, DOWN); + PIN_SLP(gpz-4, INPUT, DOWN); + PIN_SLP(gpz-5, INPUT, DOWN); + PIN_SLP(gpz-6, INPUT, DOWN); + }; +}; + +&pinctrl_3 { + pinctrl-names = "default"; + pinctrl-0 = <&sleep3>; + + sleep3: sleep-state { + PIN_SLP(gpv0-0, INPUT, DOWN); + PIN_SLP(gpv0-1, INPUT, DOWN); + PIN_SLP(gpv0-2, INPUT, DOWN); + PIN_SLP(gpv0-3, INPUT, DOWN); + PIN_SLP(gpv0-4, INPUT, DOWN); + PIN_SLP(gpv0-5, INPUT, DOWN); + PIN_SLP(gpv0-6, INPUT, DOWN); + PIN_SLP(gpv0-7, INPUT, DOWN); + + PIN_SLP(gpv1-0, INPUT, DOWN); + PIN_SLP(gpv1-1, INPUT, DOWN); + PIN_SLP(gpv1-2, INPUT, DOWN); + PIN_SLP(gpv1-3, INPUT, DOWN); + PIN_SLP(gpv1-4, INPUT, DOWN); + PIN_SLP(gpv1-5, INPUT, DOWN); + PIN_SLP(gpv1-6, INPUT, DOWN); + PIN_SLP(gpv1-7, INPUT, DOWN); + + PIN_SLP(gpv2-0, INPUT, DOWN); + PIN_SLP(gpv2-1, INPUT, DOWN); + PIN_SLP(gpv2-2, INPUT, DOWN); + PIN_SLP(gpv2-3, INPUT, DOWN); + PIN_SLP(gpv2-4, INPUT, DOWN); + PIN_SLP(gpv2-5, INPUT, DOWN); + PIN_SLP(gpv2-6, INPUT, DOWN); + PIN_SLP(gpv2-7, INPUT, DOWN); + + PIN_SLP(gpv3-0, INPUT, DOWN); + PIN_SLP(gpv3-1, INPUT, DOWN); + PIN_SLP(gpv3-2, INPUT, DOWN); + PIN_SLP(gpv3-3, INPUT, DOWN); + PIN_SLP(gpv3-4, INPUT, DOWN); + PIN_SLP(gpv3-5, INPUT, DOWN); + PIN_SLP(gpv3-6, INPUT, DOWN); + PIN_SLP(gpv3-7, INPUT, DOWN); + + PIN_SLP(gpv4-0, INPUT, DOWN); + PIN_SLP(gpv4-1, INPUT, DOWN); + }; +}; + +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_XUSBXTI>; +}; + +&pwm { + pinctrl-0 = <&pwm1_out>; + pinctrl-names = "default"; + samsung,pwm-outputs = <1>; + status = "okay"; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&sdhci_2 { + bus-width = <4>; + cd-gpios = <&gpx3 4 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4 &sdhci2_cd>; + pinctrl-names = "default"; + vmmc-supply = <&ldo23_reg>; + status = "okay"; +}; + +&sdhci_3 { + #address-cells = <1>; + #size-cells = <0>; + non-removable; + bus-width = <4>; + + mmc-pwrseq = <&wlan_pwrseq>; + pinctrl-names = "default"; + pinctrl-0 = <&sd3_clk &sd3_cmd &sd3_bus4>; + status = "okay"; + + /* BCM4334 Wi-Fi */ + brcmf: wifi@1 { + compatible = "brcm,bcm4334-fmac", "brcm,bcm4329-fmac"; + reg = <1>; + + interrupt-parent = <&gpx2>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "host-wake"; + }; +}; + +&serial_0 { + pinctrl-0 = <&uart0_data &uart0_fctl>; + pinctrl-names = "default"; + status = "okay"; + + /* BCM4334B0 Bluetooth */ + bluetooth { + compatible = "brcm,bcm4330-bt"; + pinctrl-0 = <&bt_shutdown &bt_device_wakeup &bt_host_wakeup>; + pinctrl-names = "default"; + max-speed = <3000000>; + shutdown-gpios = <&gpl0 6 GPIO_ACTIVE_HIGH>; + device-wakeup-gpios = <&gpx3 1 GPIO_ACTIVE_HIGH>; + host-wakeup-gpios = <&gpx2 6 GPIO_ACTIVE_HIGH>; + clocks = <&s5m8767_osc S2MPS11_CLK_BT>; + }; +}; + +&serial_1 { + status = "okay"; +}; + +&serial_2 { + status = "okay"; +}; + +&serial_3 { + status = "okay"; +}; + +&tmu { + vtmu-supply = <&ldo10_reg>; + status = "okay"; +};