From patchwork Sun Apr 16 19:46:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Yang X-Patchwork-Id: 13213062 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB30BC77B76 for ; Sun, 16 Apr 2023 19:47:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229911AbjDPTrb (ORCPT ); Sun, 16 Apr 2023 15:47:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34162 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229484AbjDPTra (ORCPT ); Sun, 16 Apr 2023 15:47:30 -0400 Received: from mail-pj1-x1031.google.com (mail-pj1-x1031.google.com [IPv6:2607:f8b0:4864:20::1031]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DD76CA; Sun, 16 Apr 2023 12:47:29 -0700 (PDT) Received: by mail-pj1-x1031.google.com with SMTP id hg12so8917168pjb.2; Sun, 16 Apr 2023 12:47:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681674449; x=1684266449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d8RDYyBWM9aB5+0URoWw6nSww5qd8o7lKOxHtXf6E94=; b=DdUz7BsFGLe2B3Dq7ogdYMMVvzVows4H0hFyiX7sf3tlj4jg8vhN03DC7jFcsd3/O7 H22iD6CIsh5zPgUXEp/vJEKhh9MPqN1p2r6crV6y5tDXDAqvMjIqLOY1efnbAGNF/eZG veJMbW6Hm1P5DYi3uOB6E/4mM8J9OjmGNrjorNf8ECFdggetyc8mIJ6k8Spo9omeGofX O3/tDJeN5NgE70Ll4zV7PVveZQ63hd371KxWn4J90f7SpV6i3KxogyPjOLQaJPizw4qG OkMVIldWv0lqUA0pMXRQX74DbIkQInK+9Whfy8O1nyQV7AjqV8CwMgn5PN9ImndhdYGw Zxng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681674449; x=1684266449; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8RDYyBWM9aB5+0URoWw6nSww5qd8o7lKOxHtXf6E94=; b=iqCebffU/70zWc7PTKdfbgPiflM/6DcCdIIvhm31bcKNaRQEqQOfueyHotI9hJrTzZ V9OO9SkDqRdf98Ozkb9VqVctQwO06cjDnslCnqB2PsCeqXE+skwH4ZHWe/0OwInSriFz G8DTNYUjcA+9peydMbVV3jgUcktr1ujYrHmKgnwXJ6zbFiSreZRWKA0VSWScn2guxM+y Y2UHVWGpnxwa2Ghe8YzuegjlLOE1VAKM3K9Vng/lctcb0lgasSlP4dmk6U9JzmpIxIOt Esi5ySHZ2ZVrXAndxb0g5uK5EJZ+nXAocMRvSxWsvaIbr5kmgRzlxt8mtPk3n0yULroC /7nA== X-Gm-Message-State: AAQBX9cVt4ue5jEqScubijyM3X1v16ZUywuOZOK+yB6MakBUEKSWCW0s 9j2/DJ+oRKljSRXafUVhd1Tti6Jpj+1LHUu73CA= X-Google-Smtp-Source: AKy350antjMDSCJPJLs0I24peNByemlM7dBXeuD4NSTp1JnWY/iEw8+7DIvoiQLR52B+apQlC5gacg== X-Received: by 2002:a17:902:c40f:b0:1a0:549d:399e with SMTP id k15-20020a170902c40f00b001a0549d399emr13241340plk.21.1681674448739; Sun, 16 Apr 2023 12:47:28 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.201]) by smtp.gmail.com with ESMTPSA id jd9-20020a170903260900b001a69b28f5c5sm4490375plb.222.2023.04.16.12.47.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 12:47:28 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/4] dt-bindings: clock: Add simple-clock-controller Date: Mon, 17 Apr 2023 03:46:19 +0800 Message-Id: <20230416194624.1258860-2-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230416194624.1258860-1-mmyangfl@gmail.com> References: <20230416194624.1258860-1-mmyangfl@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add DT bindings documentation for simple clock controller, just a contiguous region of multiple clock registers. Signed-off-by: David Yang --- .../clock/simple-clock-controller.yaml | 39 +++++++++++++++++++ 1 file changed, 39 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/simple-clock-controller.yaml diff --git a/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml b/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml new file mode 100644 index 000000000000..3d9b436b0ef9 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/simple-clock-controller.yaml @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/simple-clock-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Simple clock controller + +maintainers: + - David Yang + +description: | + A contiguous register region of multiple different clocks. No operations are + required to enable or disable the clock controller. + +properties: + compatible: + const: simple-clock-controller + + reg: + maxItems: 1 + +patternProperties: + '.*clock.*': + type: object + description: Clock devices. + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + clock-controller@ffff000 { + compatible = "simple-clock-controller"; + reg = <0xffff000 0x1000>; + }; From patchwork Sun Apr 16 19:46:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Yang X-Patchwork-Id: 13213063 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82C76C77B73 for ; Sun, 16 Apr 2023 19:47:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229912AbjDPTrm (ORCPT ); Sun, 16 Apr 2023 15:47:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229747AbjDPTrl (ORCPT ); Sun, 16 Apr 2023 15:47:41 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 126B535A3; Sun, 16 Apr 2023 12:47:37 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id g6so6530785pjx.4; Sun, 16 Apr 2023 12:47:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681674457; x=1684266457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nSrRFiyosuWW/GNoXp6d9t9RRxXJdRUwrLc5G51X3r4=; b=gxmMxbe4nvL+QW0NHprvSvcBsVjIgGir/LDWubXOXuVFXax5Nvftm2AGdfVbCil6sd QvFmj9NtnUTDM+AUWvmIkADgOg/onSgiyIcue4lr2BFMN6H03HvRXuIW0AsSomEARoFk s3+U7t+xGGrrCrx+FJac5fgPLdgwtWqCVwP0JdGOfuNEcL0upcjrezvVQI+J7RWxeWZU pFhlSbEIW0Ta+7H/gkz5lxTKGfBms3QzaYazNe3TYzNWkHUFVI/0Ss3sVotRKTmokCz1 jrG29BDtxye7xDfSCXoxDb7SdQAns8vc7aAvECtNU06YXHyzm6lKksOTUCfreBOBBx49 f/Ew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681674457; x=1684266457; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nSrRFiyosuWW/GNoXp6d9t9RRxXJdRUwrLc5G51X3r4=; b=fQvWr6E0lHlbrQ2US98pJEnN0ry3gl9gwSma2m7ubbChD+oRyQ5wZjmE8j6QQAjJdu Eh85hEsqk6mPrc5I0ikK0mNMuVa0q0cP12CBbGXG672ah6wRswgVYXO8tidlOp9SC4UC Ezj4FAXYJQ/JVE3ZNt7q4Q4BPTatSOnN9KBoCW7vTk/XB/0oM0d5m6aq3x8lL675Ld19 A7LRnWro2v5cZ3uFE7Zyr/v1Z2z+0GFFBTBnHdBmkp63//PHbTXRrbGa/O8uQ0AIWBOK EJ29b9DDiEO59eyj0M8/DawKWPThgj34Zw4dDRITkPz7HTziS3PEEaMioWD8C80PsDzz tJwg== X-Gm-Message-State: AAQBX9dm5gteEVMad0nmgu49vq605babnfM3SwbfIcVvKZv9fleSftVa Mb44bHk/huSshRpiSOtmPBGWVnKcjAHmqsgR65Y= X-Google-Smtp-Source: AKy350buBDqSEPzMK6gPKxwDpv7z0G++jROpu4Iptl5zv5uabF2Q9+fMpMjcIzElhJgdBsr75NU74Q== X-Received: by 2002:a17:902:c943:b0:1a6:4fbd:d5c0 with SMTP id i3-20020a170902c94300b001a64fbdd5c0mr10335262pla.53.1681674457134; Sun, 16 Apr 2023 12:47:37 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.201]) by smtp.gmail.com with ESMTPSA id jd9-20020a170903260900b001a69b28f5c5sm4490375plb.222.2023.04.16.12.47.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 12:47:36 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 2/4] clk: Add simple clock controller Date: Mon, 17 Apr 2023 03:46:20 +0800 Message-Id: <20230416194624.1258860-3-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230416194624.1258860-1-mmyangfl@gmail.com> References: <20230416194624.1258860-1-mmyangfl@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Basic common clocks were provided in `include/linux/clk-provider.h`, but lacks DT bindings for direct declaration. To use them, a lock is required to avoid operation conflict on a same register. Add a clock controller to manage this lock. Signed-off-by: David Yang --- drivers/clk/Makefile | 1 + drivers/clk/clk-of.c | 292 +++++++++++++++++++++++++++++++++++++++++++ drivers/clk/clk-of.h | 26 ++++ 3 files changed, 319 insertions(+) create mode 100644 drivers/clk/clk-of.c create mode 100644 drivers/clk/clk-of.h diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index e3ca0d058a25..6cf0a888b673 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-fractional-divider.o obj-$(CONFIG_COMMON_CLK) += clk-gpio.o ifeq ($(CONFIG_OF), y) obj-$(CONFIG_COMMON_CLK) += clk-conf.o +obj-$(CONFIG_COMMON_CLK) += clk-of.o endif # hardware specific clock types diff --git a/drivers/clk/clk-of.c b/drivers/clk/clk-of.c new file mode 100644 index 000000000000..3518ae848ed0 --- /dev/null +++ b/drivers/clk/clk-of.c @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2023 David Yang + * + * Simple straight-forward register clocks bindings + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "clk-of.h" + +struct of_clk_ctrl_priv { + spinlock_t lock; + + struct reset_controller_dev rcdev; + void __iomem *base; + bool rst_set_to_disable; +}; + +static const struct of_clk_flag of_clk_common_flags[] = { + { "set-rate-gate", CLK_SET_RATE_GATE }, + { "set-parent-gate", CLK_SET_PARENT_GATE }, + { "set-rate-parent", CLK_SET_RATE_PARENT }, + { "ignore-unused", CLK_IGNORE_UNUSED }, + { "get-rate-nocache", CLK_GET_RATE_NOCACHE }, + { "set-rate-no-reparent", CLK_SET_RATE_NO_REPARENT }, + { "get-accuracy-nocache", CLK_GET_ACCURACY_NOCACHE }, + { "recalc-new-rates", CLK_RECALC_NEW_RATES }, + { "set-rate-ungate", CLK_SET_RATE_UNGATE }, + { "critical", CLK_IS_CRITICAL }, + { "ops-parent-enable", CLK_OPS_PARENT_ENABLE }, + { "duty-cycle-parent", CLK_DUTY_CYCLE_PARENT }, + { } +}; + +void __iomem *of_clk_get_reg(struct device_node *np) +{ + u32 offset; + void __iomem *reg; + + if (of_property_read_u32(np, "offset", &offset)) + return NULL; + + reg = of_iomap(np->parent, 0); + if (!reg) + return NULL; + + return reg + offset; +} +EXPORT_SYMBOL_GPL(of_clk_get_reg); + +const char *of_clk_get_name(struct device_node *np) +{ + const char *name; + + if (!of_property_read_string(np, "clock-output-name", &name)) + return name; + + return of_node_full_name(np); +} +EXPORT_SYMBOL_GPL(of_clk_get_name); + +unsigned long +of_clk_get_flags(struct device_node *np, const struct of_clk_flag *defs) +{ + unsigned long flags = 0; + + if (!defs) + defs = of_clk_common_flags; + + for (int i = 0; defs[i].prop; i++) + if (of_property_read_bool(np, defs[i].prop)) + flags |= defs[i].flag; + + return flags; +} +EXPORT_SYMBOL_GPL(of_clk_get_flags); + +int of_clk_remove(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + + of_clk_del_provider(np); + clk_hw_unregister(np->data); + + return 0; +} +EXPORT_SYMBOL_GPL(of_clk_remove); + +int of_clk_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + int (*setup)(struct device_node *np) = of_device_get_match_data(dev); + + return setup(np); +} +EXPORT_SYMBOL_GPL(of_clk_probe); + +/** of_rst_ctrl **/ + +#if IS_ENABLED(CONFIG_RESET_CONTROLLER) +static int +of_rst_ctrl_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct of_clk_ctrl_priv *priv = container_of(rcdev, struct of_clk_ctrl_priv, rcdev); + unsigned long flags; + u32 offset = id >> 16; + u8 index = id & 0x1f; + u32 val; + + if (WARN_ON(!priv->base)) + return 0; + + spin_lock_irqsave(&priv->lock, flags); + + val = readl(priv->base + offset); + if (priv->rst_set_to_disable) + val &= ~BIT(index); + else + val |= BIT(index); + writel(val, priv->base + offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static int +of_rst_ctrl_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct of_clk_ctrl_priv *priv = container_of(rcdev, struct of_clk_ctrl_priv, rcdev); + unsigned long flags; + u32 offset = id >> 16; + u8 index = id & 0x1f; + u32 val; + + if (WARN_ON(!priv->base)) + return 0; + + spin_lock_irqsave(&priv->lock, flags); + + val = readl(priv->base + offset); + if (priv->rst_set_to_disable) + val |= BIT(index); + else + val &= ~BIT(index); + writel(val, priv->base + offset); + + spin_unlock_irqrestore(&priv->lock, flags); + + return 0; +} + +static const struct reset_control_ops of_rst_ctrl_ops = { + .assert = of_rst_ctrl_assert, + .deassert = of_rst_ctrl_deassert, +}; + +static int of_rst_ctrl_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + return (reset_spec->args[0] << 16) | (reset_spec->args[1] & 0x1f); +} + +static void of_rst_ctrl_unsetup(struct device_node *np) +{ + struct of_clk_ctrl_priv *priv = np->data; + + reset_controller_unregister(&priv->rcdev); +} + +static int of_rst_ctrl_setup(struct device_node *np, struct of_clk_ctrl_priv *priv) +{ + priv->base = of_iomap(np, 0); + priv->rst_set_to_disable = of_property_read_bool(np, "set-to-disable"); + + /* register no matter whether reg exists, to detect dts bug */ + priv->rcdev.ops = &of_rst_ctrl_ops; + priv->rcdev.of_node = np; + priv->rcdev.of_reset_n_cells = 2; + priv->rcdev.of_xlate = of_rst_ctrl_of_xlate; + return reset_controller_register(&priv->rcdev); +} +#else +static void of_rst_ctrl_unsetup(struct device_node *np) +{ +} + +static int of_rst_ctrl_setup(struct device_node *np, struct of_clk_ctrl_priv *priv) +{ + return 0; +} +#endif + +/** of_crg_ctrl **/ + +static void of_crg_ctrl_unsetup(struct device_node *np, bool crg) +{ + if (crg) + of_rst_ctrl_unsetup(np); + + kfree(np->data); + np->data = NULL; +} + +static int of_crg_ctrl_setup(struct device_node *np, bool crg) +{ + struct of_clk_ctrl_priv *priv; + int ret; + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + np->data = priv; + + spin_lock_init(&priv->lock); + + if (crg) { + ret = of_rst_ctrl_setup(np, priv); + if (ret) + goto err; + } + + return 0; + +err: + kfree(np->data); + np->data = NULL; + return ret; +} + +/** driver **/ + +static void __init of_clk_ctrl_init(struct device_node *np) +{ + of_crg_ctrl_setup(np, false); +} +CLK_OF_DECLARE(of_clk_ctrl, "simple-clock-controller", of_clk_ctrl_init); + +static void __init of_crg_ctrl_init(struct device_node *np) +{ + of_crg_ctrl_setup(np, true); +} +CLK_OF_DECLARE(of_crg_ctrl, "simple-clock-reset-controller", of_crg_ctrl_init); + +static int of_crg_ctrl_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + bool crg = (bool) of_device_get_match_data(dev); + + of_crg_ctrl_unsetup(np, crg); + + return 0; +} + +/* This function is not executed when of_clk_ctrl_init succeeded. */ +static int of_crg_ctrl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = pdev->dev.of_node; + bool crg = (bool) of_device_get_match_data(dev); + + return of_crg_ctrl_setup(np, crg); +} + +static const struct of_device_id of_crg_ctrl_ids[] = { + { .compatible = "simple-clock-controller", .data = (void *) false }, + { .compatible = "simple-clock-reset-controller", .data = (void *) true }, + { } +}; + +static struct platform_driver of_crg_ctrl_driver = { + .driver = { + .name = "clk_of", + .of_match_table = of_crg_ctrl_ids, + }, + .probe = of_crg_ctrl_probe, + .remove = of_crg_ctrl_remove, +}; +builtin_platform_driver(of_crg_ctrl_driver); diff --git a/drivers/clk/clk-of.h b/drivers/clk/clk-of.h new file mode 100644 index 000000000000..ddb1e57ec2f1 --- /dev/null +++ b/drivers/clk/clk-of.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR MIT */ +/* + * Copyright (c) 2023 David Yang + */ + +#include + +struct device_node; +struct platform_device; + +struct of_clk_ctrl { + spinlock_t lock; +}; + +struct of_clk_flag { + const char *prop; + unsigned long flag; +}; + +void __iomem *of_clk_get_reg(struct device_node *np); +const char *of_clk_get_name(struct device_node *np); +unsigned long +of_clk_get_flags(struct device_node *np, const struct of_clk_flag *defs); + +int of_clk_remove(struct platform_device *pdev); +int of_clk_probe(struct platform_device *pdev); From patchwork Sun Apr 16 19:46:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Yang X-Patchwork-Id: 13213064 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB140C77B73 for ; Sun, 16 Apr 2023 19:48:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229802AbjDPTsB (ORCPT ); Sun, 16 Apr 2023 15:48:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229959AbjDPTr7 (ORCPT ); Sun, 16 Apr 2023 15:47:59 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7204D3C39; Sun, 16 Apr 2023 12:47:46 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id la15so224142plb.11; Sun, 16 Apr 2023 12:47:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681674465; x=1684266465; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UEI0eSnVROGbttT9l8rewKYrct6gZV9DrPEigxvXAbE=; b=ifKVIowjbe1YizUEM+3ST0gRExiI9O1DyUUeZRr6cCIJTD8X7F3XPXMR9B5TX25zC3 8lgoJhipUwQSlAcNGXf0UDxuYQXUNjT1Avz7WST6RvDZm1L9XCSnXV3oGq8Xy7Pym28c kpFuaq8nAIRzEhNjSKl/fglm0W7iZh/9LKL8J12Nb8f20Y0KgIu61FRUjvmSipXOOd3q Iuitg/MTszSXpLUI3InHo0cTIONDg4GusUqg362stUuW8ih3Ub33mOla55pwLE0BPGI6 lawHzvtD1T4+doDwmmKML2FFGcH13ysKjhIhVdXSDDAf8Momc8JaxsugQz+iDNtQNsWX 9Mhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681674465; x=1684266465; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UEI0eSnVROGbttT9l8rewKYrct6gZV9DrPEigxvXAbE=; b=dtG4YdBBN/vD/hpFq5V5vNuQ92BDXCyHPRxaBZ4aeRwH0fkq5CccjsuxyPgi/+Vs+q 4cAxho/Tr/efxuenx0qr3PBHZfnAPeZMbGHdNbcG5Ew+bWwL/c6ZS7KmXAoSihJRuu1T 5+nzegcdvODHuaWwct7+K2j1FdvebGbNQQZ45hcDY8wztWzqGZMmbDfm3hxuXJA1df2v ubOgY9Br+LtUDdaNrFTzrrT76gIwedXWnAv/nevDu+anyYbI1Zkg14qFPUHmvkJrS3qZ ezz1FpGYw4aH1Mz3YoN9MFYEVU7oELlaB+bJdGStn4+/fcjjfYuowXsG9tdgpkumgURP VTkg== X-Gm-Message-State: AAQBX9dUuDXub8nJWZXBDc7XC3WOODB4NYyzHNPIXCAbIH/jqCIPAcLJ d2Zgipbis5l1e30pvTr0bxoe5uHKBhMIdXAUV5I= X-Google-Smtp-Source: AKy350ZKEfzMft2d47xJWzGkkBgfFmWE+rP1k3yCCATbX7mx8o+16vpezzFP4/TdvvMOC1/mG7MNgA== X-Received: by 2002:a17:903:22c3:b0:1a6:4032:ef2 with SMTP id y3-20020a17090322c300b001a640320ef2mr11717060plg.28.1681674465407; Sun, 16 Apr 2023 12:47:45 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.201]) by smtp.gmail.com with ESMTPSA id jd9-20020a170903260900b001a69b28f5c5sm4490375plb.222.2023.04.16.12.47.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 12:47:45 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 3/4] dt-bindings: clock: Add gate-clock Date: Mon, 17 Apr 2023 03:46:21 +0800 Message-Id: <20230416194624.1258860-4-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230416194624.1258860-1-mmyangfl@gmail.com> References: <20230416194624.1258860-1-mmyangfl@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add DT bindings documentation for gate clock, which can gate its output. Signed-off-by: David Yang --- .../devicetree/bindings/clock/gate-clock.yaml | 59 +++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/gate-clock.yaml diff --git a/Documentation/devicetree/bindings/clock/gate-clock.yaml b/Documentation/devicetree/bindings/clock/gate-clock.yaml new file mode 100644 index 000000000000..bcd549dd9db1 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/gate-clock.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/gate-clock.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Clock which can gate its output + +maintainers: + - David Yang + +description: | + Clock which can gate its output, by toggling one bit in a register. Such + register may also control other clocks or reset requests. + + The registers map is retrieved from the parental dt-node. So the clock node + should be represented as a sub-node of a "clock-controller" node. + + See also: Documentation/devicetree/bindings/clock/simple-clock-controller.yaml + +properties: + compatible: + const: gate-clock + + '#clock-cells': + const: 0 + + clocks: + maxItems: 1 + description: Parent clock. + + offset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Offset in the register map for the control register (in bytes). + + bits: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Bit index which controls the output. + + clock-output-names: + maxItems: 1 + +required: + - compatible + - '#clock-cells' + - offset + - bits + +additionalProperties: false + +examples: + - | + clock { + compatible = "gate-clock"; + #clock-cells = <0>; + offset = <0xcc>; + bits = <3>; + clock-output-names = "my-clk"; + }; From patchwork Sun Apr 16 19:46:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Yang X-Patchwork-Id: 13213065 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EDAAC77B76 for ; Sun, 16 Apr 2023 19:48:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229932AbjDPTsY (ORCPT ); Sun, 16 Apr 2023 15:48:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229593AbjDPTsX (ORCPT ); Sun, 16 Apr 2023 15:48:23 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3128E3AA7; Sun, 16 Apr 2023 12:47:58 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id p8so23526234plk.9; Sun, 16 Apr 2023 12:47:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1681674474; x=1684266474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bxfOnlh1gWPz4ECc5+gyXwuy61sNCNvLdcJJf29rWhA=; b=A5N7ttd+GYkilmlvtj+KtFUZGLlXeWa2/lQC4BLJPMTdvqPpppJSz2wwXpvbGUnqkH BcLUfkVue72PzL+gWUSgIPi+aZzmXVe3HLVRlZJWpJm1+du8k/4SQ1uMg/F0V1VXp2eI wbP/ovn3eQssgVTaM4CvwGBMme04YX/bLsvbYH7txalwmDCIPAY8LUvKDRMTnMaMQj00 jBax7l6/0Vij4TqDSwRJnoYKsETwT00mr27xtm3M5PBXJdhaDli+Sd5o35866ICOWba5 Jz2mTWatkoNYK2rOvXqY5QIMfcWnzePy0J82H1+MshVziEnNW1RKeJGZnOSgm9mUdCMS seGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681674474; x=1684266474; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bxfOnlh1gWPz4ECc5+gyXwuy61sNCNvLdcJJf29rWhA=; b=DOqngfy0JVSTSUuR0WtYh6qsP1vfh0j32Z9ApoPOUdXra092AIuv6u6B/85QlUnyjk idYWE49gnSUw4UjBgoMDg5nPIao50P4NsCkFbyL2GS3jJ0H6KHRqveSZvZ5g1nCLWrPU GgiqheFQzU2U6jOF8D/HTR7VOjaOlx6NaBtvf19GU0/eh8LfNy27Zw/D6RYbXl47e2uQ 0dIfoiF+pK/8dyoqy7TiFnQkS4Uy2L9EZWAp1pug9Z2KrY3l2DGCCIzvsrEIG141kuMj aW9QGKq/dQPbfks9Ov730L6PB4QHcQNS7oWQ+zDyLATPnt3kB9h0xHKMY5QyHzcqHCnZ DTMw== X-Gm-Message-State: AAQBX9fgJdYBmY0uLzgfkSRHAwvCj9XPH5Gxbqpv8qKsUBlj6OguLTZY POrNrEGG0vxhQ9nYo/hzbDBXaYSoNEgOzS4/Qus= X-Google-Smtp-Source: AKy350YNW0o4BxR7h0HrV31DgHcaDX8VRrafFkGAVtSacy2Ns4UtFBDAxhmCLeiKBHTvKRzzP8g83A== X-Received: by 2002:a17:902:da8d:b0:1a6:5274:c1b0 with SMTP id j13-20020a170902da8d00b001a65274c1b0mr12262127plx.60.1681674473708; Sun, 16 Apr 2023 12:47:53 -0700 (PDT) Received: from d.home.yangfl.dn42 ([104.28.245.201]) by smtp.gmail.com with ESMTPSA id jd9-20020a170903260900b001a69b28f5c5sm4490375plb.222.2023.04.16.12.47.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Apr 2023 12:47:53 -0700 (PDT) From: David Yang To: linux-clk@vger.kernel.org Cc: David Yang , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Philipp Zabel , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 4/4] clk: gate: Add DT binding Date: Mon, 17 Apr 2023 03:46:22 +0800 Message-Id: <20230416194624.1258860-5-mmyangfl@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230416194624.1258860-1-mmyangfl@gmail.com> References: <20230416194624.1258860-1-mmyangfl@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-clk@vger.kernel.org Add DT binding for gate clock as "gate-clock". Signed-off-by: David Yang --- drivers/clk/clk-gate.c | 81 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c index 64283807600b..a70df4a2a9a7 100644 --- a/drivers/clk/clk-gate.c +++ b/drivers/clk/clk-gate.c @@ -12,8 +12,11 @@ #include #include #include +#include #include +#include "clk-of.h" + /** * DOC: basic gatable clock which can gate and ungate it's ouput * @@ -257,3 +260,81 @@ struct clk_hw *__devm_clk_hw_register_gate(struct device *dev, return hw; } EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate); + +#if IS_ENABLED(CONFIG_OF) +static const struct of_clk_flag of_clk_gate_flags[] = { + { "set-to-disable", CLK_GATE_SET_TO_DISABLE }, + { "hiword-mask", CLK_GATE_HIWORD_MASK }, + { "big-endian", CLK_GATE_BIG_ENDIAN }, + { } +}; + +static int of_clk_gate_setup(struct device_node *np) +{ + struct of_clk_ctrl *ctrl = np->parent->data; + const char *name; + void __iomem *reg; + u32 bit_idx; + + const char *property; + struct clk_hw *hw; + int ret; + + reg = of_clk_get_reg(np); + if (!reg) + return -ENOMEM; + name = of_clk_get_name(np); + if (!name) + return -EINVAL; + + property = "bits"; + if (of_property_read_u32(np, property, &bit_idx)) + goto err_property; + + hw = __clk_hw_register_gate(NULL, np, name, + of_clk_get_parent_name(np, 0), + NULL, NULL, of_clk_get_flags(np, NULL), + reg, bit_idx, + of_clk_get_flags(np, of_clk_gate_flags), + &ctrl->lock); + if (IS_ERR(hw)) + return PTR_ERR(hw); + + ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, hw); + if (ret) + goto err_register; + + np->data = hw; + return 0; + +err_register: + clk_hw_unregister(hw); + return ret; + +err_property: + pr_err("%s: clock %s missing required property \"%s\"\n", + __func__, name, property); + return -EINVAL; +} + +static void __init of_clk_gate_init(struct device_node *np) +{ + of_clk_gate_setup(np); +} +CLK_OF_DECLARE(of_clk_gate, "gate-clock", of_clk_gate_init); + +static const struct of_device_id of_clk_gate_ids[] = { + { .compatible = "gate-clock", .data = of_clk_gate_setup }, + { } +}; + +static struct platform_driver of_clk_gate_driver = { + .driver = { + .name = "clk_gate", + .of_match_table = of_clk_gate_ids, + }, + .probe = of_clk_probe, + .remove = of_clk_remove, +}; +builtin_platform_driver(of_clk_gate_driver); +#endif