From patchwork Thu Jan 31 08:49:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10790081 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 7AC5C13B4 for ; Thu, 31 Jan 2019 08:51:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7B69A303B0 for ; Thu, 31 Jan 2019 08:51:08 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6FFD2303B7; Thu, 31 Jan 2019 08:51:08 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EB8D2301EB for ; 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Thu, 31 Jan 2019 08:50:05 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 1/8] clk: samsung: add needed IDs for DMC clocks in Exynos5420 Date: Thu, 31 Jan 2019 09:49:47 +0100 Message-Id: <1548924594-19084-2-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJKsWRmVeSWpSXmKPExsWy7djPc7r7tgXFGFz8r2yxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbdY ev0ik8XtxhVsFq17j7BbHH7Tzuog4LFm3hpGj02rOtk8Ni+p9zj4bg+TR9+WVYwenzfJBbBF cdmkpOZklqUW6dslcGWsmL6CvWC1YMWPTWeZGxjv8HUxcnBICJhIvNtt2cXIxSEksIJR4sbZ dkYI5wujxMsnt1ggnM+MEsvuPmDuYuQE65jacIUVIrGcUWL+0jXMcC1Hp09kBpnLJqAnsWNV IUiDiEC1xJ3r+8FqmAXuMEnsnbmUBSQhLBAsMXn3FzCbRUBV4vz0dawgNq+Al8SO65eZILbJ Sdw81wm2mVPAW2JJ11+oK3axS3ye7AVhu0hsa9wIVS8s8er4FnYIW0bi/875UPFiibMdq9gg 7BqJ9pM7oGqsJQ4fv8gKcjOzgKbE+l36EGFHiTcvLzJBgohP4sZbQZAwM5A5adt0Zogwr0RH mxBEtYbElp4LUIvEJJavmQY13EPi1fYWaBjOY5TY9Pkc6wRG+VkIyxYwMq5iFE8tLc5NTy02 ykst1ytOzC0uzUvXS87P3cQITECn/x3/soNx15+kQ4wCHIxKPLwP1gbGCLEmlhVX5h5ilOBg VhLhNfztHyPEm5JYWZValB9fVJqTWnyIUZqDRUmct5rhQbSQQHpiSWp2ampBahFMlomDU6qB UboiUex9qNw+puRjbInJOilvPTcyvJpm+ulOxwwu1gAZnjOWMWsXSYVMi7LfeShvEZvTq53P k4UOCxmLpU14kTClkqWbzzlg8cPZ0y7uWh23Uinl26O3a+tOnLshrlbVL/dZ77xcT/UZTl1V ncc5AgtmXz6j+FugITpZWoZjp55H5a9J5oyHlViKMxINtZiLihMBA580gDwDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42I5/e/4Xd2924JiDJYf17PYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslss vX6RyeJ24wo2i9a9R9gtDr9pZ3UQ8Fgzbw2jx6ZVnWwem5fUexx8t4fJo2/LKkaPz5vkAtii 9GyK8ktLUhUy8otLbJWiDS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DJWTF/B XrBasOLHprPMDYx3+LoYOTkkBEwkpjZcYe1i5OIQEljKKLHp9Q4WiISYxKR929khbGGJP9e6 2CCKPjFK3HtykrmLkYODTUBPYseqQpAaEYF6if43l9hAbGaBV0wSDe81QGxhgUCJtvuLweaw CKhKnJ++jhXE5hXwkthx/TITxHw5iZvnOplBbE4Bb4klXX/BbCGgmh//PjJOYORbwMiwilEk tbQ4Nz232FCvODG3uDQvXS85P3cTIzAmth37uXkH46WNwYcYBTgYlXh4H6wNjBFiTSwrrsw9 xCjBwawkwmv42z9GiDclsbIqtSg/vqg0J7X4EKMp0FETmaVEk/OB8ZpXEm9oamhuYWlobmxu bGahJM573qAySkggPbEkNTs1tSC1CKaPiYNTqoHR24T1UHHI9OwPRjOZ6gvTjvjXTbxok3Lk GYOCjVpA3K6jbgwO9+KmBTXb1xT+8be2rHhRs5/ly/G2//mBUT/cVLx5jWUf9JTLlHqIzJ0i VGV9lf3YR6a+X3/d7qU53suZPDWnS/W9vlbrvwMh7Xot+1udz5u8uPbq3S5P5WnvF4Zm5Lqw rlFiKc5INNRiLipOBAAyp4GUnwIAAA== X-CMS-MailID: 20190131085006eucas1p2e4ba3f69e039c394e7cd42389ac8bfa7 X-Msg-Generator: CA X-RootMTR: 20190131085006eucas1p2e4ba3f69e039c394e7cd42389ac8bfa7 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085006eucas1p2e4ba3f69e039c394e7cd42389ac8bfa7 References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new IDs for clocks used by Dynamic Memory Controller in Exynos5422 SoC. CC: Sylwester Nawrocki CC: Chanwoo Choi CC: Rob Herring CC: Mark Rutland CC: Kukjin Kim CC: Krzysztof Kozlowski CC: linux-samsung-soc@vger.kernel.org CC: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-kernel@vger.kernel.org Signed-off-by: Lukasz Luba --- include/dt-bindings/clock/exynos5420.h | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h index 355f469..1827a64 100644 --- a/include/dt-bindings/clock/exynos5420.h +++ b/include/dt-bindings/clock/exynos5420.h @@ -60,6 +60,7 @@ #define CLK_MAU_EPLL 159 #define CLK_SCLK_HSIC_12M 160 #define CLK_SCLK_MPHY_IXTAL24 161 +#define CLK_SCLK_BPLL 162 /* gate clocks */ #define CLK_UART0 257 @@ -195,6 +196,16 @@ #define CLK_ACLK432_CAM 518 #define CLK_ACLK_FL1550_CAM 519 #define CLK_ACLK550_CAM 520 +#define CLK_CLKM_PHY0 521 +#define CLK_CLKM_PHY1 522 +#define CLK_ACLK_PPMU_DREX0_0 523 +#define CLK_ACLK_PPMU_DREX0_1 524 +#define CLK_ACLK_PPMU_DREX1_0 525 +#define CLK_ACLK_PPMU_DREX1_1 526 +#define CLK_PCLK_PPMU_DREX0_0 527 +#define CLK_PCLK_PPMU_DREX0_1 528 +#define CLK_PCLK_PPMU_DREX1_0 529 +#define CLK_PCLK_PPMU_DREX1_1 530 /* mux clocks */ #define CLK_MOUT_HDMI 640 @@ -217,6 +228,10 @@ #define CLK_MOUT_EPLL 657 #define CLK_MOUT_MAU_EPLL 658 #define CLK_MOUT_USER_MAU_EPLL 659 +#define CLK_MOUT_DPLL 660 +#define CLK_MOUT_ACLK_G3D 661 +#define CLK_MOUT_SCLK_SPLL 662 +#define CLK_MOUT_MX_MSPLL_CCORE_PHY 663 /* divider clocks */ #define CLK_DOUT_PIXEL 768 @@ -248,8 +263,9 @@ #define CLK_DOUT_CCLK_DREX0 794 #define CLK_DOUT_CLK2X_PHY0 795 #define CLK_DOUT_PCLK_CORE_MEM 796 +#define CLK_FF_DOUT_SPLL2 797 /* must be greater than maximal clock id */ -#define CLK_NR_CLKS 797 +#define CLK_NR_CLKS 798 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ From patchwork Thu Jan 31 08:49:48 2019 Content-Type: text/plain; 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Thu, 31 Jan 2019 08:50:05 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 2/8] clk: samsung: add new clocks for DMC for Exynos5422 SoC Date: Thu, 31 Jan 2019 09:49:48 +0100 Message-Id: <1548924594-19084-3-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrLKsWRmVeSWpSXmKPExsWy7djPc7r7twXFGMzeLWaxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBYfe+6xWlzeNYfN4nPvEUaLGef3MVms PXKX3eLiKVeL240r2CwOv2lntfh3bSOLg6DH+xut7B6bVnWyeWxeUu9x8N0eJo++LasYPT5v kgtgi+KySUnNySxLLdK3S+DK+Hx3IWvBBf2KK3dOsjYw/tXoYuTkkBAwkZh9YwNTFyMXh5DA CkaJPzcPskM4Xxglfu/4xgbhfAZyZrQxwbQ8ntUCVbWcUWLFzXvMcC1nDqxm6WLk4GAT0JPY saoQpEFEoFrizvX9YDXMAg3MEjuaJrCAJIQFAiVe//gBNpVFQFXi4rRn7CC9vAJeEtdnCkEs k5O4ea6TGcTmFPCWWNL1lxkivo9d4nVnAITtInFnxgV2CFtY4tXxLVC2jMT/nfOhji6WONux ig3CrpFoP7kDqsZa4vDxi6wga5kFNCXW79KHCDtKHNl7jRkkLCHAJ3HjrSBImBnInLRtOlSY V6KjDepIDYktPRegFolJLF8zDWq4h8SGZ1uhgTOPUeLDtzOsExjlZyEsW8DIuIpRPLW0ODc9 tdgoL7Vcrzgxt7g0L10vOT93EyMwEZ3+d/zLDsZdf5IOMQpwMCrx8D5YGxgjxJpYVlyZe4hR goNZSYTX8Ld/jBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHeaoYH0UIC6YklqdmpqQWpRTBZJg5O qQZGo+uqe6s3m3tV/Y5wuZr6/mFW/qIKeT3dJsFb+icvNFSliRz/tqWmkCFD4guTmdSBORHr bu5kOBPz5KCVPsc1I9XnqiVOm3oTmW9uWLRlYsCOg43n1Q8URd2+7e7QuV3QgClhlWtX7Oql M8wX/o5NVRHWeF9U6yIR/X5bpE6Jrffsc3K6cbVKLMUZiYZazEXFiQBix1X1QAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprAIsWRmVeSWpSXmKPExsVy+t/xu7r7tgXFGEzpVbDYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VouPPfdYLS7vmsNm8bn3CKPFjPP7mCzW HrnLbnHxlKvF7cYVbBaH37SzWvy7tpHFQdDj/Y1Wdo9NqzrZPDYvqfc4+G4Pk0ffllWMHp83 yQWwRenZFOWXlqQqZOQXl9gqRRtaGOkZWlroGZlY6hkam8daGZkq6dvZpKTmZJalFunbJehl fL67kLXggn7FlTsnWRsY/2p0MXJySAiYSDye1cLexcjFISSwlFFi+/8FjBAJMYlJ+7azQ9jC En+udbFBFH1ilNg6bzpQEQcHm4CexI5VhSA1IgL1Ev1vLoHVMAv0MUs0Hl/MCpIQFvCXWH7g HxuIzSKgKnFx2jN2kF5eAS+J6zOFIObLSdw818kMYnMKeEss6foLZgsBlfz495FxAiPfAkaG VYwiqaXFuem5xYZ6xYm5xaV56XrJ+bmbGIGxse3Yz807GC9tDD7EKMDBqMTD+2BtYIwQa2JZ cWXuIUYJDmYlEV7D3/4xQrwpiZVVqUX58UWlOanFhxhNgW6ayCwlmpwPjNu8knhDU0NzC0tD c2NzYzMLJXHe8waVUUIC6YklqdmpqQWpRTB9TBycUg2MLjp982ebvtsyeeerbpXpoUvkz7Jw p8z1S9jxqHF5CZflU9P7q6Yf31i/tOgCM//HS+tFd229E/BHzsD/3Am/nLfeG5dMXcHhwZMt xK90Zeox11//2fY+6NKdo9qR/O1dhvBpi8i3NyTM6g/y39EWlAgU6U/NkDtVZC/Hpfv63i1x 15wr7L3ySizFGYmGWsxFxYkANLs6oaMCAAA= X-CMS-MailID: 20190131085006eucas1p1ca478545c107086d427909c88d3b232e X-Msg-Generator: CA X-RootMTR: 20190131085006eucas1p1ca478545c107086d427909c88d3b232e X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085006eucas1p1ca478545c107086d427909c88d3b232e References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch provides support for clocks needed for Dynamic Memory Controller in Exynos5422 SoC. It adds CDREX base register addresses, new DIV, MUX and GATE entries. CC: Sylwester Nawrocki CC: Chanwoo Choi CC: Michael Turquette CC: Stephen Boyd CC: Kukjin Kim CC: Krzysztof Kozlowski CC: linux-samsung-soc@vger.kernel.org CC: linux-clk@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-kernel@vger.kernel.org Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 48 +++++++++++++++++++++++++++++++++--- 1 file changed, 44 insertions(+), 4 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 34cce3c..3e87421 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -132,6 +132,8 @@ #define BPLL_LOCK 0x20010 #define BPLL_CON0 0x20110 #define SRC_CDREX 0x20200 +#define GATE_BUS_CDREX0 0x20700 +#define GATE_BUS_CDREX1 0x20704 #define DIV_CDREX0 0x20500 #define DIV_CDREX1 0x20504 #define KPLL_LOCK 0x28000 @@ -248,6 +250,8 @@ static const unsigned long exynos5x_clk_regs[] __initconst = { DIV_CDREX1, SRC_KFC, DIV_KFC0, + GATE_BUS_CDREX0, + GATE_BUS_CDREX1, }; static const unsigned long exynos5800_clk_regs[] __initconst = { @@ -425,6 +429,10 @@ PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" }; PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" }; PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" }; PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" }; +PNAME(mout_mx_mspll_ccore_phy_p) = { "sclk_bpll", "mout_dpll_ctrl", + "mout_mpll_ctrl", "ff_dout_spll2", + "mout_sclk_spll"}; + /* fixed rate clocks generated outside the soc */ static struct samsung_fixed_rate_clock @@ -450,7 +458,7 @@ static const struct samsung_fixed_factor_clock static const struct samsung_fixed_factor_clock exynos5800_fixed_factor_clks[] __initconst = { FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0), - FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), + FFACTOR(CLK_FF_DOUT_SPLL2, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0), }; static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { @@ -472,11 +480,14 @@ static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = { MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2), MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2), + MUX(CLK_MOUT_MX_MSPLL_CCORE_PHY, "mout_mx_mspll_ccore_phy", + mout_mx_mspll_ccore_phy_p, SRC_TOP7, 0, 3), + MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore", - mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2), + mout_mx_mspll_ccore_p, SRC_TOP7, 16, 3), MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p, SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0), - MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), + MUX(CLK_SCLK_BPLL, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1), MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1), MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3), @@ -648,7 +659,7 @@ static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = { MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1), MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1), - MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), + MUX(CLK_MOUT_SCLK_SPLL, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1), MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1), MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1), MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1, @@ -814,9 +825,13 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { DIV_CDREX0, 16, 3), DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0", DIV_CDREX0, 8, 3), + DIV(0, "dout_cclk_drex1", "dout_clk2x_phy0", DIV_CDREX0, 8, 3), DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex", DIV_CDREX0, 3, 5), + DIV(0, "dout_pclk_drex0", "dout_cclk_drex0", DIV_CDREX0, 28, 3), + DIV(0, "dout_pclk_drex1", "dout_cclk_drex1", DIV_CDREX0, 28, 3), + DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex", DIV_CDREX1, 8, 3), @@ -1170,6 +1185,31 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = { GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0), GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0), + + GATE(CLK_CLKM_PHY0, "clkm_phy0", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 0, 0, 0), + GATE(CLK_CLKM_PHY1, "clkm_phy1", "dout_sclk_cdrex", + GATE_BUS_CDREX0, 1, 0, 0), + GATE(0, "mx_mspll_ccore_phy", "mout_mx_mspll_ccore_phy", + SRC_MASK_TOP7, 0, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_ACLK_PPMU_DREX0_0, "aclk_ppmu_drex0_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 15, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX0_1, "aclk_ppmu_drex0_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 14, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX1_0, "aclk_ppmu_drex1_0", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 13, CLK_IGNORE_UNUSED, 0), + GATE(CLK_ACLK_PPMU_DREX1_1, "aclk_ppmu_drex1_1", "dout_aclk_cdrex1", + GATE_BUS_CDREX1, 12, CLK_IGNORE_UNUSED, 0), + + GATE(CLK_PCLK_PPMU_DREX0_0, "pclk_ppmu_drex0_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 29, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX0_1, "pclk_ppmu_drex0_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 28, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX1_0, "pclk_ppmu_drex1_0", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 27, CLK_IGNORE_UNUSED, 0), + GATE(CLK_PCLK_PPMU_DREX1_1, "pclk_ppmu_drex1_1", "dout_pclk_cdrex", + GATE_BUS_CDREX1, 26, CLK_IGNORE_UNUSED, 0), }; static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = { From patchwork Thu Jan 31 08:49:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10790025 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C780117E9 for ; Thu, 31 Jan 2019 08:50:15 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C1EC1301EB for ; Thu, 31 Jan 2019 08:50:15 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B601230221; Thu, 31 Jan 2019 08:50:15 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E1D14301EB for ; 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Thu, 31 Jan 2019 08:50:06 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 3/8] clk: samsung: add BPLL rate table for Exynos 5422 SoC Date: Thu, 31 Jan 2019 09:49:49 +0100 Message-Id: <1548924594-19084-4-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSa0hTYRj229nZOYpHj0fJLzODkVBKmhH1gV0MKpYh2gWJMmrpYQ6v7XjJ tJrmdWiKUEpp+kPQlqIulTUv2SaK5mVieEktRWqlZoWjCG85z6p/z/dc3ud94SMx5hnuRspj E1hFrDRaLLITtnT/HtzX2XI+bL+mgEaNpfU4GjObcFTRNYijwrkFDA0NNRBoIGORQO+U7kgz N4qjH/nvcTSiKxOh5YIugEqHOgSormuaQMN9p9Bkeo0IGRZzcLQ+2igMcJJ8G88iJBp1nkjy ouqe5PVSm0DyoEkNJMsajxDRZbsjEWy0PIlV+B67bhfZ3roqjNcytxp0mYQSfHdUAVsS0gdh lumjUAXsSIauAbBW1QP4hxnAeUO3VVkGsLL3E64C5FbEaIrn+WoA+/srRf8SqpJpwmIS0T5Q q75pqXChU+HU2CvM4sFoJQa1GUVCi+BMB8OsX7MCi19Ie8KyNk8LTdGBUDtfQPDrecCJwTzM gm3ps7BKtYbxfAcBzT9xHp+Ea8ZqK+8M53uarFl3uPGyQsBjDg7kqkU8ToM5vVqrxx8aeoa3 7sLovbBe56sCxCZ9ArYH8Mc6wPGvThYvtgmLW0ownqZgbjbDj9gDm/KN1pptsLr2kXW0BBaX F29VMvRTAMc6/IvArsf/myoBUANXNpGLkbHcgVg22YeTxnCJsTKf8LgYDdj8QG/We8xaoFu9 oQc0CcT21EzduTAGlyZxKTF6AElM7EL5rQSHMVSENOU2q4i7pkiMZjk92EEKxa5Uqs3MFYaW SRPYKJaNZxV/VQFp66YE3p+nvkTqAwckq0m1FVTb5KFOZmEGKtcNWGeIMWS7FxU6dGluZqIj Sm56GOR9eilNrC6X3fVonn7iN6YevNMbburb2J3ukOzj6BWw2Jxhlgcdbh05XthvjLTJZnc2 Jd7vzzxKrVz0g2c8oijD8w+erkZdyQUn+9DKWflb+mq3WMhFSv28MAUn/QPzdQXiPAMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupnkeLIzCtJLcpLzFFi42I5/e/4Xd3924JiDF40CFpsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLHY9Pgaq8XHnnusFpd3zWGz+Nx7hNFixvl9TBZr j9xlt7h4ytXiduMKNovDb9pZLf5d28jiIOjx/kYru8emVZ1sHpuX1HscfLeHyaNvyypGj8+b 5ALYovRsivJLS1IVMvKLS2yVog0tjPQMLS30jEws9QyNzWOtjEyV9O1sUlJzMstSi/TtEvQy 9u7+w1KwQ6hiw64W9gbGD/xdjBwcEgImEheeF3QxcnEICSxllJizax1TFyMnUFxMYtK+7ewQ trDEn2tdbBBFnxglWpovsoA0swnoSexYVQhSIyJQL9H/5hJYDbNAH7NE4/HFrCAJYQFfiaO/ V7CD1LMIqErM2aMKEuYV8JLY8aoXar6cxM1zncwgNqeAt8SSrr9gthBQzY9/HxknMPItYGRY xSiSWlqcm55bbKRXnJhbXJqXrpecn7uJERgZ24793LKDsetd8CFGAQ5GJR7eB2sDY4RYE8uK K3MPMUpwMCuJ8Br+9o8R4k1JrKxKLcqPLyrNSS0+xGgKdNNEZinR5Hxg1OaVxBuaGppbWBqa G5sbm1koifOeN6iMEhJITyxJzU5NLUgtgulj4uCUamDc8krC3jr/htiOv9O8deT+hjqFTTop +bDvf8mJb7F3y6xz5l730vl4XCRv5VrZtf7Wk58efD334jO5vHDFxERm/5BLkrX1lnsq1PQq QtdPb8gJvLsnoj+v5nn3pj0Mwc0Nb0tjzpdN3ndVtqZVzL9+d5vKjVk68g8vyuee1jB84DO7 x9T9NrsSS3FGoqEWc1FxIgBD/FAZogIAAA== X-CMS-MailID: 20190131085007eucas1p2f16107042b8ce5638811840618bcf017 X-Msg-Generator: CA X-RootMTR: 20190131085007eucas1p2f16107042b8ce5638811840618bcf017 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085007eucas1p2f16107042b8ce5638811840618bcf017 References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory Controller frequencies for driver's DRAM timings. CC: Sylwester Nawrocki CC: Chanwoo Choi CC: Michael Turquette CC: Stephen Boyd CC: Kukjin Kim CC: Krzysztof Kozlowski CC: linux-samsung-soc@vger.kernel.org CC: linux-clk@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-kernel@vger.kernel.org Signed-off-by: Lukasz Luba --- drivers/clk/samsung/clk-exynos5420.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 3e87421..8bf9579 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1325,6 +1325,19 @@ static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __ini PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5422_bpll_rate_table[] = { + PLL_35XX_RATE(24 * MHZ, 933000000, 311, 4, 1), + PLL_35XX_RATE(24 * MHZ, 825000000, 275, 4, 1), + PLL_35XX_RATE(24 * MHZ, 728000000, 182, 3, 1), + PLL_35XX_RATE(24 * MHZ, 633000000, 211, 4, 1), + PLL_35XX_RATE(24 * MHZ, 543000000, 181, 2, 2), + PLL_35XX_RATE(24 * MHZ, 413000000, 413, 6, 2), + PLL_35XX_RATE(24 * MHZ, 275000000, 275, 3, 3), + PLL_35XX_RATE(24 * MHZ, 206000000, 206, 3, 3), + PLL_35XX_RATE(24 * MHZ, 165000000, 110, 2, 3), + PLL_35XX_RATE(24 * MHZ, 138000000, 184, 2, 4), +}; + static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0), PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0), @@ -1467,7 +1480,7 @@ static void __init exynos5x_clk_init(struct device_node *np, exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[bpll].rate_table = exynos5422_bpll_rate_table; } samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls), From patchwork Thu Jan 31 08:49:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10790037 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 4CE131874 for ; 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Thu, 31 Jan 2019 08:50:07 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 4/8] drivers: devfreq: add DMC driver for Exynos5422 Date: Thu, 31 Jan 2019 09:49:50 +0100 Message-Id: <1548924594-19084-5-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprDKsWRmVeSWpSXmKPExsWy7djPc7oHtgXFGFz8pWexccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbe4 3biCzeLwm3ZWBz6PTas62Tw2L6n3OPhuD5NH35ZVjB6fN8kFsEZx2aSk5mSWpRbp2yVwZXS9 bmEuOHGFqWL2vm6mBsYVU5m6GDk5JARMJN5/6WbsYuTiEBJYwSjRe/8kK4TzhVHi0fnZ7BDO Z0aJVc9WMMK0nFpyDaplOaPE1IedCC073iwDGszBwSagJ7FjVSFIg4hAtcSd6/uZQWqYBSYz SSw63Q22XFjAXeL0ixdsIPUsAqoSC7bZgoR5BbwkLq6eww6xTE7i5rlOZhCbU8BbYknXX7A5 EgLL2CVeXd3BClHkIvFt1QqoBmGJV8e3QNkyEv93zod6tFjibMcqNgi7RqL95A6oGmuJw8cv soLcwCygKbF+lz6IKSHgKNH70gPC5JO48VYQpJgZyJy0bTozRJhXoqNNCGKGhsSWngtQe8Qk lq+ZBjXbQ6KjZQILJHDmMUrM/DODdQKj/CyEXQsYGVcxiqeWFuempxYb5qWW6xUn5haX5qXr JefnbmIEppnT/45/2sH49VLSIUYBDkYlHt4HawNjhFgTy4orcw8xSnAwK4nwGv72jxHiTUms rEotyo8vKs1JLT7EKM3BoiTOW83wIFpIID2xJDU7NbUgtQgmy8TBKdXAuCBkwzVNuSfHS3fv 3Jr6ODg4fvHRdVVlfNLREyb1rp0Tmd4e6Lwt7vWaW0f0dJ7EbZe+vd9i59K5Ui1/2Oxm59Ye k53mV1BkYXhnlSmb65LM46vEEr52N0xR0irwSjL+Hq7+U6lv9oHjMjtev05fnf/GQ7R3iR6H 8Ov+k5eqlzt6xi1qV12xRomlOCPRUIu5qDgRAAOFcUcvAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t/xu7r7twXFGLycZmOxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbe4 3biCzeLwm3ZWBz6PTas62Tw2L6n3OPhuD5NH35ZVjB6fN8kFsEbp2RTll5akKmTkF5fYKkUb WhjpGVpa6BmZWOoZGpvHWhmZKunb2aSk5mSWpRbp2yXoZXS9bmEuOHGFqWL2vm6mBsYVU5m6 GDk5JARMJE4tucYIYgsJLGWUmNvJAREXk5i0bzs7hC0s8edaF1sXIxdQzSdGiYsr/gM1c3Cw CehJ7FhVCFIjIlAv0f/mElgNs8B8Jon+KXNZQRLCAu4Sp1+8YAOpZxFQlViwzRYkzCvgJXFx 9Ryo+XISN891MoPYnALeEku6/jJD3OMl8ePfR8YJjHwLGBlWMYqklhbnpucWG+oVJ+YWl+al 6yXn525iBIb9tmM/N+9gvLQx+BCjAAejEg/vg7WBMUKsiWXFlbmHGCU4mJVEeA1/+8cI8aYk VlalFuXHF5XmpBYfYjQFumkis5Rocj4wJvNK4g1NDc0tLA3Njc2NzSyUxHnPG1RGCQmkJ5ak ZqemFqQWwfQxcXBKNTBOzz1bcHnKgo7/F51fHfZ7/axS69Z+OS5ezwvR51Qm6bTOORSpds5w vWDLLMdbM6+4da/L2RVgzS7TfJVDVtvSfWXsC+nTF7aarfRPee/TebXO7uyOyhsvFFWXyx/w 2/psbv7DNd6+mxbPri6/ErslzsTM0KxBm6Ehy3PJv0kvXp2urshyO7BZiaU4I9FQi7moOBEA qQ+9BZECAAA= X-CMS-MailID: 20190131085008eucas1p237fe9e2f8cb6254e8da7c97c2984e6b2 X-Msg-Generator: CA X-RootMTR: 20190131085008eucas1p237fe9e2f8cb6254e8da7c97c2984e6b2 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085008eucas1p237fe9e2f8cb6254e8da7c97c2984e6b2 References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds driver for Exynos5422 Dynamic Memory Controller. The driver provides support for dynamic frequency and voltage scaling for DMC and DRAM. It supports changing timings of DRAM running with different frequency. The patch also contains needed MAINTAINERS file update. CC: MyungJoo Ham CC: Kyungmin Park CC: Chanwoo Choi CC: Kukjin Kim CC: Krzysztof Kozlowski CC: linux-kernel@vger.kernel.org CC: linux-pm@vger.kernel.org CC: linux-samsung-soc@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org Signed-off-by: Lukasz Luba --- MAINTAINERS | 7 + drivers/devfreq/Kconfig | 13 + drivers/devfreq/Makefile | 1 + drivers/devfreq/exynos5422-dmc.c | 1274 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 1295 insertions(+) create mode 100644 drivers/devfreq/exynos5422-dmc.c diff --git a/MAINTAINERS b/MAINTAINERS index 9f64f8d..e81dfbf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3310,6 +3310,13 @@ S: Maintained F: drivers/devfreq/exynos-bus.c F: Documentation/devicetree/bindings/devfreq/exynos-bus.txt +DMC FREQUENCY DRIVER FOR SAMSUNG EXYNOS5422 +M: Lukasz Luba +L: linux-pm@vger.kernel.org +L: linux-samsung-soc@vger.kernel.org +S: Maintained +F: drivers/devfreq/exynos5422-dmc.c + BUSLOGIC SCSI DRIVER M: Khalid Aziz L: linux-scsi@vger.kernel.org diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig index 6a172d3..2a876ad 100644 --- a/drivers/devfreq/Kconfig +++ b/drivers/devfreq/Kconfig @@ -113,6 +113,19 @@ config ARM_RK3399_DMC_DEVFREQ It sets the frequency for the memory controller and reads the usage counts from hardware. +config ARM_EXYNOS5422_DMC_DEVFREQ + tristate "ARM EXYNOS5422 DMC DEVFREQ Driver" + depends on ARCH_EXYNOS || COMPILE_TEST + select DEVFREQ_GOV_SIMPLE_ONDEMAND + select DEVFREQ_GOV_PASSIVE + select PM_DEVFREQ_EVENT + select PM_OPP + help + This adds DEVFREQ driver for Exynos5422 DMC (Dynamic Memory Controller). + The driver provides support for Dynamic Voltage and Frequency Scaling in + DMC and DRAM. It also supports changing timings of DRAM running with + different frequency. + source "drivers/devfreq/event/Kconfig" endif # PM_DEVFREQ diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile index 32b8d4d..d011835 100644 --- a/drivers/devfreq/Makefile +++ b/drivers/devfreq/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra-devfreq.o +obj-$(CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ) += exynos5422-dmc.o # DEVFREQ Event Drivers obj-$(CONFIG_PM_DEVFREQ_EVENT) += event/ diff --git a/drivers/devfreq/exynos5422-dmc.c b/drivers/devfreq/exynos5422-dmc.c new file mode 100644 index 0000000..8a19281 --- /dev/null +++ b/drivers/devfreq/exynos5422-dmc.c @@ -0,0 +1,1274 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2019 Samsung Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DRIVER_DESC "Driver for Exynos5422 Dynamic Memory Controller dynamic frequency and voltage change" + +#define EXYNOS5422_REV_0 (0x1) +#define EXYNOS5422_PROD_REV_MAIN_MASK (0xf0) +#define EXYNOS5422_PROD_REV_SUB_MASK (0xf) + +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGROW0 (0x0034) +#define EXYNOS5_DREXI_TIMINGDATA0 (0x0038) +#define EXYNOS5_DREXI_TIMINGPOWER0 (0x003C) +#define EXYNOS5_DREXI_TIMINGROW1 (0x00E4) +#define EXYNOS5_DREXI_TIMINGDATA1 (0x00E8) +#define EXYNOS5_DREXI_TIMINGPOWER1 (0x00EC) + +#define EXYNOS5_DREXI_MEMCTRL (0x0004) +#define EXYNOS5_DREXI_DIRECTCMD (0x0010) +#define EXYNOS5_DREXI_TIMINGAREF (0x0030) +#define EXYNOS5_DREXI_TIMINGSETSW (0x00E0) +#define EXYNOS5_DREXI_MRSTATUS (0x0054) +#define EXYNOS5_DREXI_QOSCONTROL8 (0x00A0) +#define EXYNOS5_DREXI_BRBRSVCONTROL (0x0100) +#define EXYNOS5_DREXI_BP_CONTROL0 (0x0210) +#define EXYNOS5_DREXI_BP_CONTROL1 (0x0220) +#define EXYNOS5_DREXI_BP_CONTROL2 (0x0230) +#define EXYNOS5_DREXI_BP_CONTROL3 (0x0240) + +#define EXYNOS5_LPDDR3PHY_CON3 (0x0A20) +#define EXYNOS5_TIMING_SET_SWI (1UL << 28) + +#define AREF_NORMAL (0x2e) + +#define EXYNOS5_TIMING_USE_SET (1UL << 4) +#define EXYNOS5_TIMING_SET_SW_CON (1UL) + +#define EXYNOS5_CLK_MUX_STAT_CDREX (0x400) +#define EXYNOS5_MCLK_CDREX_SEL_BPLL (1UL) +#define EXYNOS5_MCLK_CDREX_SEL_MX_MSPLL (2UL) +#define EXYNOS5_CLKSRC_CDREX_SEL_SHIFT (4) +#define EXYNOS5_MCLK_CDREX_MASK (0x7) + +#define EXYNOS5_CLK_SRC_CDREX (0x200) +#define DMC_PAUSE_CTRL (0x91C) +#define DMC_PAUSE_ENABLE (1UL) +#define SELF_REFRESH_MASK (0x20UL) +#define SR_CMD_EXIT_CHIP0 (0x08000000) +#define SR_CMD_EXIT_CHIP1 (0x08100000) +#define CMD_SR_ENTER (0x04000000) +#define CMD_SR_EXIT (0x08000000) +#define CMD_CHIP0 (0x00000000) +#define CMD_CHIP1 (0x00100000) +#define USE_MX_MSPLL_TIMINGS (1) +#define USE_BPLL_TIMINGS (0) + +#define DMC_REG_VOLT_STEP 0 + +#define IS_MEM_2GB(val) \ + ( \ + (((val) & 0xf0) & 0x20) ? 1 : \ + (((val) & 0xf0) & 0x30) ? 1 : 0 \ + ) + +#define EXYNOS5_POP_OPTIONS(val) \ + (((val >> 4) & 0x3UL) << 4) +#define EXYNOS5_DDR_TYPE(val) \ + (((val >> 14) & 0x1UL)) + +#define CHIP_PROD_ID (0) +#define CHIP_PKG_ID (4) + +#define PMCNT_CONST_RATIO_MUL 15 +#define PMCNT_CONST_RATIO_DIV 10 + +/** + * enum dmc_slot_id - An enum with slots in DMC + */ +enum dmc_slot_id { + DMC0_0, + DMC0_1, + DMC1_0, + DMC1_1, + DMC_SLOTS_END +}; + +/** + * struct dmc_slot_info - Describes DMC's slot + * + * The structure holds DMC's slot name which is part of the device name + * provided in DT. Each slot has particular share of the DMC bandwidth. + * To abstract the model performance and values in performance counters, + * fields 'ratio_mul' and 'ratio_div' are used in calculation algorithm + * for each slot. Please check the corresponding function with the algorithm, + * to see how these variables are used. + */ +struct dmc_slot_info { + char *name; + int id; + int ratio_mul; + int ratio_div; +}; + +/** + * struct dmc_opp_table - Operating level desciption + * + * Covers frequency and voltage settings of the DMC operating mode. + */ +struct dmc_opp_table { + unsigned long freq_khz; + unsigned long volt_uv; +}; + +/** + * struct dram_param - Parameters for the external memory chip + * + * Covers timings settings for a particular memory chip's operating frequency. + */ +struct dram_param { + unsigned int timing_row; + unsigned int timing_data; + unsigned int timing_power; +}; + +/** + * struct exynos5_dmc - main structure describing DMC device + * + * The main structure for the Dynamic Memory Controller which covers clocks, + * memory regions, HW information, parameters and current operating mode. + */ +struct exynos5_dmc { + struct device *dev; + struct devfreq *df; + struct devfreq_simple_ondemand_data gov_data; + void __iomem *base_drexi0; + void __iomem *base_drexi1; + void __iomem *base_clk; + void __iomem *chip_id; + struct mutex lock; + unsigned long curr_rate; + unsigned long curr_volt; + const struct dmc_opp_table *opp; + const struct dmc_opp_table *opp_bypass; + int opp_count; + const struct dram_param *dram_param; + const struct dram_param *dram_bypass_param; + int dram_param_count; + unsigned int prod_rev; + unsigned int pkg_rev; + unsigned int mem_info; + struct regulator *vdd_mif; + struct clk *fout_spll; + struct clk *fout_bpll; + struct clk *mout_spll; + struct clk *mout_bpll; + struct clk *mout_mclk_cdrex; + struct clk *dout_clk2x_phy0; + struct clk *mout_mx_mspll_ccore; + struct clk *mx_mspll_ccore_phy; + struct clk *mout_mx_mspll_ccore_phy; + struct devfreq_event_dev **counter; + int num_counters; + bool counters_enabled; +}; + +/** + * exynos5_counters_fname() - Macro generating function for event devices + * @f: function name suffix + * + * Macro which generates needed function for manipulation of event devices. + * It aims to avoid code duplication relaying on similar prefix and function + * parameters in the devfreq event device framework functions. + */ +#define exynos5_counters_fname(f) \ +static int exynos5_counters_##f(struct exynos5_dmc *dmc) \ +{ \ + int i, ret; \ + \ + for (i = 0; i < dmc->num_counters; i++) { \ + if (!dmc->counter[i]) \ + continue; \ + ret = devfreq_event_##f(dmc->counter[i]); \ + if (ret < 0) \ + return ret; \ + } \ + return 0; \ +} +exynos5_counters_fname(set_event); +exynos5_counters_fname(enable_edev); +exynos5_counters_fname(disable_edev); + +/** + * dmc_opp_exynos5422 - Array with frequency and voltage values + * + * Operating points for Exynos5422 SoC revisions. + * The order and sizeof the array has a meaning and is tightly connected with + * DRAM parameters in arrays bellow. + */ +static const struct dmc_opp_table dmc_opp_exynos5422[] = { + {825000, 1050000}, + {728000, 1037500}, + {633000, 1012500}, + {543000, 937500}, + {413000, 887500}, + {275000, 875000}, + {206000, 875000}, + {165000, 875000}, +}; + +/** + * dmc_opp_bypass_exynos5422 - frequency and voltage level for temporary mode + */ +static const struct dmc_opp_table dmc_opp_bypass_exynos5422 = {400000, 887500}; + +/** + * dram_param_exynos5422 - DRAM timings for particular HW setup + * + * Operating parameters for DRAM memory running with different clock frequency. + * The order is the same as in 'dmc_opp_table' above, the highest frequency + * is first. + * These settings are needed for proper operation of the DRAM memory with + * corresponding frequency. They are calculated for Exynos5422 revision 0 + * with 2GB LPDDR3 memory chip. + */ +static const struct dram_param dram_param_exynos5422[] = { + {0x365A9713, 0x4740085E, 0x543A0446}, + {0x30598651, 0x3730085E, 0x4C330336}, + {0x2A48758F, 0x3730085E, 0x402D0335}, + {0x244764CD, 0x3730085E, 0x38270335}, + {0x1B35538A, 0x2720085E, 0x2C1D0225}, + {0x12244287, 0x2720085E, 0x1C140225}, + {0x112331C6, 0x2720085E, 0x180F0225}, + {0x11223185, 0x2720085E, 0x140C0225}, +}; + + +/** + * Operating parameters for DRAM memory running on temporary clock 400MHz during + * switching frequency on the main clock. This variable provides timings for + * Exynos5422 SoC revision 0 and DRAM 2GB chip. + */ +static const struct dram_param dram_bypass_param_exynos5422 = { + 0x365a9713, 0x4740085e, 0x543a0446 +}; + +/** + * dmc_slot - An array which holds DMC's slots information + * + * The array is used in algorithm calculating slots performance and usage + * based on performance counters' values. The values i.e. 15/10=1.5 correspond + * to slot share in the DMC channel, which has 2.0 abstract width. + */ +static const struct dmc_slot_info dmc_slot[] = { + {"dmc0_0", DMC0_0, 15, 10}, + {"dmc0_1", DMC0_1, 5, 10}, + {"dmc1_0", DMC1_0, 10, 10}, + {"dmc1_1", DMC1_0, 10, 10}, +}; + +/** + * find_target_freq_id() - Finds requested frequency in local DMC configuration + * @dmc: device for which the information is checked + * @target_rate: requested frequency in KHz + * + * Seeks in the local DMC driver structure for the requested frequency value + * and returns index or error value. + */ +static int find_target_freq_idx(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int i; + + for (i = 0; i < dmc->opp_count; i++) + if (dmc->opp[i].freq_khz <= target_rate) + return i; + + return -EINVAL; +} + +/** + * exynos5_get_chip_info() - Gets chip ID information + * @dmc: device for which the information is checked + * + * Function wrapper for getting the chip ID information. + */ +static void exynos5_get_chip_info(struct exynos5_dmc *dmc) +{ + unsigned int val; + + val = readl(dmc->chip_id + CHIP_PROD_ID); + dmc->prod_rev = val; + + val = readl(dmc->chip_id + CHIP_PKG_ID); + dmc->pkg_rev = val; + + dmc->mem_info = EXYNOS5_POP_OPTIONS(val); + dmc->mem_info |= EXYNOS5_DDR_TYPE(val); +} + +/** + * exynos5_dmc_pause_on_switching() - Controls a pause feature in DMC + * @dmc: device which is used for changing this feature + * @set: a boolean state passing enable/disable request + * + * There is a need of pausing DREX DMC when divider or MUX in clock tree + * changes its configuration. In such situation access to the memory is blocked + * in DMC automatically. This feature is used when clock frequency change + * request appears and touches clock tree. + */ +static int exynos5_dmc_pause_on_switching(struct exynos5_dmc *dmc, bool set) +{ + unsigned int val; + + val = readl(dmc->base_clk + DMC_PAUSE_CTRL); + if (set) + val |= DMC_PAUSE_ENABLE; + else + val &= ~DMC_PAUSE_ENABLE; + writel(val, dmc->base_clk + DMC_PAUSE_CTRL); + + return 0; +} + +/** + * exynos5_dmc_chip_revision_settings() - Chooses proper DMC's configuration + * @dmc: device for which is going to be checked and configured + * + * Function checks the HW product information in order to choose proper + * configuration for DMC frequency, voltage and DRAM timings. + */ +static int exynos5_dmc_chip_revision_settings(struct exynos5_dmc *dmc) +{ + exynos5_get_chip_info(dmc); + + if (!IS_MEM_2GB(dmc->mem_info)) { + dev_warn(dmc->dev, "DRAM memory type not supported\n"); + return -EINVAL; + } + + dmc->dram_param = dram_param_exynos5422; + + dmc->dram_param_count = ARRAY_SIZE(dram_param_exynos5422); + + dmc->dram_bypass_param = &dram_bypass_param_exynos5422; + + dmc->opp = dmc_opp_exynos5422; + dmc->opp_count = ARRAY_SIZE(dmc_opp_exynos5422); + + dmc->opp_bypass = &dmc_opp_bypass_exynos5422; + + return 0; +} + +/** + * exynos5_init_freq_table() - Initialized PM OPP framework + * @dev: devfreq device for which the OPP table is going to be + * initialized + * @dmc: DMC device for which the frequencies are used for OPP init + * @profile: devfreq device's profile + * + * Populate the devfreq device's OPP table based on current frequency, voltage. + */ +static int exynos5_init_freq_table(struct device *dev, struct exynos5_dmc *dmc, + struct devfreq_dev_profile *profile) +{ + int i, ret; + + for (i = 0; i < dmc->opp_count; i++) { + ret = dev_pm_opp_add(dev, dmc->opp[i].freq_khz, + dmc->opp[i].volt_uv); + if (ret) { + dev_warn(dev, "failed to add opp %uHz %umV\n", 1, 1); + while (i-- > 0) + dev_pm_opp_remove(dev, dmc->opp[i].freq_khz); + return ret; + } + } + + return 0; +} + +/** + * exynos5_set_bypass_dram_timings() - Low-level changes of the DRAM timings + * @dmc: device for which the new settings is going to be applied + * @param: DRAM parameters which passes timing data + * + * Low-level function for changing timings for DRAM memory clocking from + * 'bypass' clock source (fixed frequency @400MHz). + * It uses timing bank registers set 1. + */ +static void exynos5_set_bypass_dram_timings(struct exynos5_dmc *dmc, + const struct dram_param *param) +{ + + writel(AREF_NORMAL, dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(param->timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW1); + writel(param->timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW1); + writel(param->timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA1); + writel(param->timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA1); + writel(param->timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER1); + writel(param->timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER1); +} + + +/** + * exynos5_dram_change_timings() - Low-level changes of the DRAM final timings + * @dmc: device for which the new settings is going to be applied + * @target_rate: target frequency of the DMC + * + * Low-level function for changing timings for DRAM memory operating from main + * clock source (BPLL), which can have different frequencies. Thus, each + * frequency must have corresponding timings register values in order to keep + * the needed delays. + * It uses timing bank registers set 0. + */ +static int exynos5_dram_change_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx; + + + for (idx = 0; idx < dmc->dram_param_count; idx++) + if (dmc->opp[idx].freq_khz <= target_rate) + break; + + if (idx >= dmc->dram_param_count) + return -EINVAL; + + writel(AREF_NORMAL, dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGAREF); + + writel(dmc->dram_param[idx].timing_row, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->dram_param[idx].timing_row, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGROW0); + writel(dmc->dram_param[idx].timing_data, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->dram_param[idx].timing_data, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGDATA0); + writel(dmc->dram_param[idx].timing_power, + dmc->base_drexi0 + EXYNOS5_DREXI_TIMINGPOWER0); + writel(dmc->dram_param[idx].timing_power, + dmc->base_drexi1 + EXYNOS5_DREXI_TIMINGPOWER0); + + return 0; +} + +/** + * exynos5_switch_timing_regs() - Changes bank register set for DRAM timings + * @dmc: device for which the new settings is going to be applied + * @set: boolean variable passing set value + * + * Changes the register set, which holds timing parameters. + * There is two register sets: 0 and 1. The register set 0 + * is used in normal operation when the clock is provided from main PLL. + * The bank register set 1 is used when the main PLL frequency is going to be + * changed and the clock is taken from alternative, stable source. + * This function switches between these banks according to the + * currently used clock source. + */ +static void exynos5_switch_timing_regs(struct exynos5_dmc *dmc, bool set) +{ + unsigned int reg; + + reg = readl(dmc->base_clk + EXYNOS5_LPDDR3PHY_CON3); + + if (set) + reg |= EXYNOS5_TIMING_SET_SWI; + else + reg &= ~EXYNOS5_TIMING_SET_SWI; + + writel(reg, dmc->base_clk + EXYNOS5_LPDDR3PHY_CON3); +} + +/* + * Change clock parent for MUX_CORE_SEL and the main clock for DMC. + * The mux takes two clock sources: main BPLL and mx_mspll ('bypass'). + */ +static int exynos5_dmc_change_clock_parent(struct exynos5_dmc *dmc, + struct clk *parent, + unsigned int parent_selection_id) +{ + unsigned int reg = 0; + + reg = readl(dmc->base_clk + EXYNOS5_CLK_SRC_CDREX); + if (clk_set_parent(dmc->mout_mclk_cdrex, parent)) { + dev_err(dmc->dev, "Couldn't change parent of mclk_cdrex\n"); + return -EINVAL; + } + + for ( ; reg != parent_selection_id; ) { + cpu_relax(); + reg = readl(dmc->base_clk + EXYNOS5_CLK_MUX_STAT_CDREX); + reg >>= EXYNOS5_CLKSRC_CDREX_SEL_SHIFT; + reg &= EXYNOS5_MCLK_CDREX_MASK; + } + + return 0; +} + + +/** + * exynos5_dmc_change_voltage() - Changes the voltage regulator value + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Main function for changing voltage on the VDD_MIF regulator. + */ +static int exynos5_dmc_change_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret; + + ret = regulator_set_voltage(dmc->vdd_mif, target_volt, + target_volt + DMC_REG_VOLT_STEP); + + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + return 0; +} + +/** + * exynos5_dmc_align_target_voltage() - Sets the final voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for 'normal' mode. + * It checks the need of higher voltage and changes the value. The target + * voltage might be lower that currently set and still the system will be + * stable. + */ +static int exynos5_dmc_align_target_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + + if (dmc->curr_volt > target_volt) + ret = exynos5_dmc_change_voltage(dmc, target_volt); + + return ret; +} + +/** + * exynos5_dmc_align_bypass_voltage() - Sets the voltage for the DMC + * @dmc: device for which it is going to be set + * @target_volt: new voltage which is chosen to be final + * + * Function tries to align voltage to the safe level for the 'bypass' mode. + * It checks the need of higher voltage and changes the value. + * The target voltage must not be less than currently needed, because + * for current frequency the device might become unstable. + */ +static int exynos5_dmc_align_bypass_voltage(struct exynos5_dmc *dmc, + unsigned long target_volt) +{ + int ret = 0; + unsigned long bypass_volt = dmc->opp_bypass->volt_uv; + + target_volt = max(bypass_volt, target_volt); + + if (dmc->curr_volt >= target_volt) + return 0; + + ret = exynos5_dmc_change_voltage(dmc, target_volt); + + return ret; +} + +/** + * exynos5_dmc_align_bypass_dram_timings() - Chooses and sets DRAM timings + * @dmc: device for which it is going to be set + * @target_rate: new frequency which is chosen to be final + * + * Function changes the DRAM timings for the temporary 'bypass' mode. + */ +static int exynos5_dmc_align_bypass_dram_timings(struct exynos5_dmc *dmc, + unsigned long target_rate) +{ + int idx = find_target_freq_idx(dmc, target_rate); + + if (idx < 0) + return -EINVAL; + + exynos5_set_bypass_dram_timings(dmc, dmc->dram_bypass_param); + + return 0; +} + +/** + * exynos5_dmc_switch_to_bypass_configuration() - Switching to temporary clock + * @dmc: DMC device for which the switching is going to happen + * @target_rate: new frequency which is going to be set as a final + * @target_volt: new voltage which is going to be set as a final + * + * Function configures DMC and clocks for operating in temporary 'bypass' mode. + * This mode is used only temporary but if required, changes voltage and timings + * for DRAM chips. It switches the main clock to stable clock source for the + * period of the main PLL reconfiguration. + */ +static int exynos5_dmc_switch_to_bypass_configuration(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + /* + * Having higher voltage for a particular frequency does not harm + * the chip. Use it for the temporary frequency change when one + * voltage manipulation might be avoided. + */ + ret = exynos5_dmc_align_bypass_voltage(dmc, target_volt); + if (ret) + return ret; + + /* + * Longer delays for DRAM does not cause crash, the opposite does. + */ + ret = exynos5_dmc_align_bypass_dram_timings(dmc, target_rate); + if (ret) + return ret; + + /* + * Delays are long enough, so use them for the new coming clock. + */ + exynos5_switch_timing_regs(dmc, USE_MX_MSPLL_TIMINGS); + + /* + * Voltage is set at least to a level needed for this frequency, + * so switching clock source is safe now. + */ + clk_prepare_enable(dmc->fout_spll); + clk_prepare_enable(dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + ret = exynos5_dmc_change_clock_parent(dmc, dmc->mout_mx_mspll_ccore, + EXYNOS5_MCLK_CDREX_SEL_MX_MSPLL); + return ret; +} + +/** + * exynos5_dmc_change_freq_and_volt() - Changes voltage and frequency of the DMC + * using safe procedure + * @dmc: device for which the frequency is going to be changed + * @target_rate: requested new frequency + * @target_volt: requested voltage which corresponds to the new frequency + * + * The DMC frequency change procedure requires a few steps. + * The main requirement is to change the clock source in the clk mux + * for the time of main clock PLL locking. The assumption is that the + * alternative clock source set as parent is stable. + * The second parent's clock frequency is fixed to 400MHz, it is named 'bypass' + * clock. This requires alignment in DRAM timing parameters for the new + * T-period. There is two bank sets for keeping DRAM + * timings: set 0 and set 1. The set 0 is used when main clock source is + * chosen. The 2nd set of regs is used for 'bypass' clock. Switching between + * the two bank sets is part of the process. + * The voltage must also be aligned to the minimum required level. There is + * this intermediate step with switching to 'bypass' parent clock source. + * if the old voltage is lower, it requires an increase of the voltage level. + * The complexity of the voltage manipulation is hidden in low level function. + * In this function there is last alignment of the voltage level at the end. + */ +static int +exynos5_dmc_change_freq_and_volt(struct exynos5_dmc *dmc, + unsigned long target_rate, + unsigned long target_volt) +{ + int ret; + + ret = exynos5_dmc_switch_to_bypass_configuration(dmc, target_rate, + target_volt); + if (ret) + return ret; + + /* We are safe to increase the timings for current bypass frequency. + * Thanks to this the settings we be ready for the upcoming clock source + * change. + */ + exynos5_dram_change_timings(dmc, target_rate); + + clk_set_rate(dmc->fout_bpll, target_rate * 1000); + + exynos5_switch_timing_regs(dmc, USE_BPLL_TIMINGS); + + ret = exynos5_dmc_change_clock_parent(dmc, dmc->mout_bpll, + EXYNOS5_MCLK_CDREX_SEL_BPLL); + if (ret) + return ret; + + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + clk_disable_unprepare(dmc->fout_spll); + /* Make sure if the voltage is not from 'bypass' settings and align to + * the right level for power efficiency. + */ + ret = exynos5_dmc_align_target_voltage(dmc, target_volt); + + return ret; +} + +/** + * exynos5_dmc_get_volt_freq() - Gets the frequency and voltage from the OPP + * table. + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @target_rate: returned frequency which is the same or lower than + * requested + * @target_volt: returned voltage which corresponds to the returned + * frequency + * + * Function gets requested frequency and checks OPP framework for needed + * frequency and voltage. It populates the values 'target_rate' and + * 'target_volt' or returns error value when OPP framework fails. + */ +static int exynos5_dmc_get_volt_freq(struct device *dev, unsigned long *freq, + unsigned long *target_rate, + unsigned long *target_volt, u32 flags) +{ + struct dev_pm_opp *opp; + + opp = devfreq_recommended_opp(dev, freq, flags); + if (IS_ERR(opp)) + return PTR_ERR(opp); + + *target_rate = dev_pm_opp_get_freq(opp); + *target_volt = dev_pm_opp_get_voltage(opp); + dev_pm_opp_put(opp); + + return 0; +} + +/** + * exynos5_dmc_target() - Function responsible for changing frequency of DMC + * @dev: device for which the frequency is going to be changed + * @freq: requested frequency in KHz + * @flags: flags provided for this frequency change request + * + * An entry function provided to the devfreq framework which provides frequency + * change of the DMC. The function gets the possible rate from OPP table based + * on requested frequency. It calls the next function responsible for the + * frequency and voltage change. In case of failure, does not set 'curr_rate' + * and returns error value to the framework. + */ +static int exynos5_dmc_target(struct device *dev, unsigned long *freq, + u32 flags) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long target_rate = 0; + unsigned long target_volt = 0; + int ret; + + ret = exynos5_dmc_get_volt_freq(dev, freq, &target_rate, &target_volt, + flags); + if (ret) + return ret; + + if (target_rate == dmc->curr_rate) + return 0; + + mutex_lock(&dmc->lock); + + ret = exynos5_dmc_change_freq_and_volt(dmc, target_rate, target_volt); + + if (ret) { + mutex_unlock(&dmc->lock); + return ret; + } + + dmc->curr_rate = target_rate; + + mutex_unlock(&dmc->lock); + return 0; +} + +/** + * exynos5_cnt_name_match() - Tries to match 'edev' with the right device index + * @edev: event device for which the name is going to be matched + * + * Function matches the name of the 'edev' counter device with known devices + * with configured ratios and shares of the DMC channels. + * When the name is matched, it returns the index for the proper device. + */ +static int exynos5_cnt_name_match(struct devfreq_event_dev *edev) +{ + int i; + int id = -ENODEV; + + for (i = 0; i < ARRAY_SIZE(dmc_slot); i++) { + if (strstr(edev->desc->name, dmc_slot[i].name)) + return i; + } + + return id; +} + +/** + * exynos5_cnt_calculate() - Calculates the values of performance counters. + * @edev: event device for which the counter is used for calculation + * @cnt: raw counter value + * @cnt_norm: counter value normalized to DMC performance ratio for a proper + * channel or virtual channel + * + * Function calculates normalized value for the raw counter. The raw counter + * value does not show real channel usage. The DMC splits not equally the + * bandwidth for the channels. The function checks the type of the 'edev' + * counter and calculates the normalized value based on the 'shares' of the + * bandwidth set in the controller. + */ +static int exynos5_cnt_calculate(struct devfreq_event_dev *edev, + unsigned long cnt, u64 *cnt_norm) +{ + int idx; + + idx = exynos5_cnt_name_match(edev); + if (idx < 0) + return idx; + + *cnt_norm = cnt; + + if (!(dmc_slot[idx].ratio_mul == dmc_slot[idx].ratio_div)) { + *cnt_norm = *cnt_norm * dmc_slot[idx].ratio_mul; + *cnt_norm = div_u64(*cnt_norm, dmc_slot[idx].ratio_div); + } + + *cnt_norm = *cnt_norm * PMCNT_CONST_RATIO_MUL; + *cnt_norm = div_u64(*cnt_norm, PMCNT_CONST_RATIO_DIV); + + return idx; +} + +/** + * exynos5_counters_get() - Gets the performance counters values. + * @dmc: device for which the counters are going to be checked + * @load_count: variable which is populated with counter value + * @total_count: variable which is used as 'wall clock' reference + * + * Function which provides performance counters values. It sums up counters for + * two DMC channels. The 'total_count' is used as a reference and max value. + * The ratio 'load_count/total_count' shows the busy percentage [0%, 100%]. + */ +static int exynos5_counters_get(struct exynos5_dmc *dmc, + unsigned long *load_count, + unsigned long *total_count) +{ + unsigned long load_dmc[2] = {0, 0}; + unsigned long total = 0; + u64 load = 0; + struct devfreq_event_data event; + int ret, i, idx; + + for (i = 0; i < dmc->num_counters; i++) { + if (!dmc->counter[i]) + continue; + + ret = devfreq_event_get_event(dmc->counter[i], &event); + if (ret < 0) + return ret; + + idx = exynos5_cnt_calculate(dmc->counter[i], event.load_count, + &load); + if (idx < 0) + continue; + + if (idx == DMC0_0 || idx == DMC0_1) + load_dmc[0] += load; + else + load_dmc[1] += load; + + if (total < event.total_count) + total = event.total_count; + } + + *load_count = load_dmc[0] + load_dmc[1]; + *total_count = total; + + return 0; +} + +/** + * exynos5_dmc_get_status() - Read current DMC performance statistics. + * @dev: device for which the statistics are requested + * @stat: structure which has statistic fields + * + * Function reads the DMC performance counters and calculates 'busy_time' + * and 'total_time'. To protect from overflow, the values are shifted right + * by 10. After read out the counters are setup to count again. + */ +static int exynos5_dmc_get_status(struct device *dev, + struct devfreq_dev_status *stat) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + unsigned long load, total; + int ret; + bool cnt_en; + + mutex_lock(&dmc->lock); + cnt_en = dmc->counters_enabled; + mutex_unlock(&dmc->lock); + if (!cnt_en) { + dev_warn(dev, "performance counters needed, but not present\n"); + return -EAGAIN; + } + + ret = exynos5_counters_get(dmc, &load, &total); + if (ret < 0) + return -EINVAL; + + /* To protect from overflow in calculation ratios, divide by 1024 */ + stat->busy_time = load >> 10; + stat->total_time = total >> 10; + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not set event counter\n"); + return ret; + } + + return 0; +} + +/** + * exynos5_dmc_get_cur_freq() - Function returns current DMC frequency + * @dev: device for which the framework checks operating frequency + * @freq: returned frequency value + * + * It returns the currently used frequency of the DMC. The real operating + * frequency might be lower when the clock source value could not be divided + * to the requested value. + */ +static int exynos5_dmc_get_cur_freq(struct device *dev, unsigned long *freq) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(dev); + + mutex_lock(&dmc->lock); + *freq = dmc->curr_rate; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_df_profile - Devfreq governor's profile structure + * + * It provides to the devfreq framework needed functions and polling period. + */ +static struct devfreq_dev_profile exynos5_dmc_df_profile = { + .polling_ms = 500, + .target = exynos5_dmc_target, + .get_dev_status = exynos5_dmc_get_status, + .get_cur_freq = exynos5_dmc_get_cur_freq, +}; + +/** + * exynos5_dmc_align_initial_frequency() - Align initial frequency value + * @dmc: device for which the frequency is going to be set + * @bootloader_init_freq: initial frequency set by the bootloader in KHz + * + * The initial bootloader frequency, which is present during boot, might be + * different that supported frequency values in the driver. It is possible + * due to different PLL settings or used PLL as a source. + * This function provides the 'initial_freq' for the devfreq framework + * statistics engine which supports only registered values. Thus, some alignment + * must be made. + */ +unsigned long +exynos5_dmc_align_init_freq(struct exynos5_dmc *dmc, + unsigned long bootloader_init_freq) +{ + unsigned long aligned_freq; + int idx; + + idx = find_target_freq_idx(dmc, bootloader_init_freq); + if (idx >= 0) + aligned_freq = dmc->opp[idx].freq_khz; + else + aligned_freq = dmc->opp[dmc->opp_count - 1].freq_khz; + + return aligned_freq; +} + +/** + * exynos5_dmc_init_clks() - Initialize clocks needed for DMC operation. + * @dev: device for which the clocks are setup + * @dmc: DMC structure containing needed fields + * + * Get the needed clocks defined in DT device, enable and set the right parents. + * Read current frequency and initialize the initial rate for governor. + */ +static int exynos5_dmc_init_clks(struct device *dev, struct exynos5_dmc *dmc) +{ + int ret; + unsigned long target_volt = 0; + unsigned long target_rate = 0; + + dmc->fout_spll = devm_clk_get(dev, "fout_spll"); + if (IS_ERR(dmc->fout_spll)) + return PTR_ERR(dmc->fout_spll); + + dmc->fout_bpll = devm_clk_get(dev, "fout_bpll"); + if (IS_ERR(dmc->fout_bpll)) + return PTR_ERR(dmc->fout_bpll); + + dmc->mout_mclk_cdrex = devm_clk_get(dev, "mout_mclk_cdrex"); + if (IS_ERR(dmc->mout_mclk_cdrex)) + return PTR_ERR(dmc->mout_mclk_cdrex); + + dmc->mout_bpll = devm_clk_get(dev, "mout_bpll"); + if (IS_ERR(dmc->mout_bpll)) + return PTR_ERR(dmc->mout_bpll); + + dmc->mout_mx_mspll_ccore = devm_clk_get(dev, "mout_mx_mspll_ccore"); + if (IS_ERR(dmc->mout_mx_mspll_ccore)) + return PTR_ERR(dmc->mout_mx_mspll_ccore); + + dmc->dout_clk2x_phy0 = devm_clk_get(dev, "dout_clk2x_phy0"); + if (IS_ERR(dmc->dout_clk2x_phy0)) + return PTR_ERR(dmc->dout_clk2x_phy0); + + dmc->mout_spll = devm_clk_get(dev, "ff_dout_spll2"); + if (IS_ERR(dmc->mout_spll)) + return PTR_ERR(dmc->mout_spll); + + /* + * Convert frequency to KHz values and set it for the governor. + */ + dmc->curr_rate = clk_get_rate(dmc->mout_mclk_cdrex) / 1000; + dmc->curr_rate = exynos5_dmc_align_init_freq(dmc, dmc->curr_rate); + exynos5_dmc_df_profile.initial_freq = dmc->curr_rate; + + ret = exynos5_dmc_get_volt_freq(dev, &dmc->curr_rate, &target_rate, + &target_volt, 0); + if (ret) + return ret; + + dmc->curr_volt = target_volt; + + clk_prepare_enable(dmc->mout_spll); + clk_set_parent(dmc->mout_mx_mspll_ccore, dmc->mout_spll); + clk_prepare_enable(dmc->mout_mx_mspll_ccore); + + clk_prepare_enable(dmc->fout_bpll); + clk_prepare_enable(dmc->mout_bpll); + + return 0; +} + +/** + * exynos5_performance_counters_init() - Initializes performance DMC's counters + * @dmc: DMC for which it does the setup + * + * Initialization of performance counters in DMC for estimating usage. + * The counter's values are used for calculation of a memory bandwidth and based + * on that the governor changes the frequency. + * The counters are not used when the governor is GOVERNOR_USERSPACE. + */ +static int exynos5_performance_counters_init(struct exynos5_dmc *dmc) +{ + int counters_size; + int ret, i; + + dmc->num_counters = devfreq_event_get_edev_count(dmc->dev); + if (dmc->num_counters < 0) { + dev_err(dmc->dev, "could not get devfreq-event counters\n"); + return dmc->num_counters; + } + + counters_size = sizeof(struct devfreq_event_dev) * dmc->num_counters; + dmc->counter = devm_kzalloc(dmc->dev, counters_size, GFP_KERNEL); + if (!dmc->counter) + return -ENOMEM; + + for (i = 0; i < dmc->num_counters; i++) { + dmc->counter[i] = + devfreq_event_get_edev_by_phandle(dmc->dev, i); + if (IS_ERR_OR_NULL(dmc->counter[i])) + return -EPROBE_DEFER; + } + + ret = exynos5_counters_enable_edev(dmc); + if (ret < 0) { + dev_err(dmc->dev, "could not enable event counter\n"); + return ret; + } + + ret = exynos5_counters_set_event(dmc); + if (ret < 0) { + dev_err(dmc->dev, "counld not set event counter\n"); + return ret; + } + + mutex_lock(&dmc->lock); + dmc->counters_enabled = true; + mutex_unlock(&dmc->lock); + + return 0; +} + +/** + * exynos5_dmc_probe() - Probe function for the DMC driver + * @pdev: platform device for which the driver is going to be initialized + * + * Initialize basic components: clocks, regulators, performance counters, etc. + * Read out product version and based on the information setup + * internal structures for the controller (frequency and voltage) and for DRAM + * memory parameters: timings for each operating frequency. + * Register new devfreq device for controlling DVFS of the DMC. + */ +static int exynos5_dmc_probe(struct platform_device *pdev) +{ + int ret = 0; + struct exynos5_dmc *dmc; + struct device *dev = &pdev->dev; + struct resource *res; + + dmc = devm_kzalloc(dev, sizeof(*dmc), GFP_KERNEL); + if (!dmc) + return -ENOMEM; + + mutex_init(&dmc->lock); + + dmc->dev = dev; + platform_set_drvdata(pdev, dmc); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + dmc->base_drexi0 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi0)) + return PTR_ERR(dmc->base_drexi0); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 1); + dmc->base_drexi1 = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_drexi1)) + return PTR_ERR(dmc->base_drexi1); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 2); + dmc->base_clk = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->base_clk)) + return PTR_ERR(dmc->base_clk); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 3); + dmc->chip_id = devm_ioremap_resource(dev, res); + if (IS_ERR(dmc->chip_id)) + return PTR_ERR(dmc->chip_id); + + ret = exynos5_dmc_chip_revision_settings(dmc); + if (ret) + return ret; + + ret = exynos5_init_freq_table(dev, dmc, &exynos5_dmc_df_profile); + if (ret) + return ret; + + dmc->vdd_mif = devm_regulator_get(dev, "vdd_mif"); + if (IS_ERR(dmc->vdd_mif)) { + ret = PTR_ERR(dmc->vdd_mif); + dev_warn(dev, "couldn't get regulator\n"); + goto remove_opp_table; + } + + ret = exynos5_dmc_init_clks(dev, dmc); + if (ret) { + dev_warn(dev, "couldn't initialize clocks\n"); + goto remove_opp_table; + } + + ret = exynos5_dmc_pause_on_switching(dmc, 1); + if (ret) { + dev_warn(dev, "couldn't setup pause on switching\n"); + goto remove_clocks; + } + + ret = exynos5_performance_counters_init(dmc); + if (ret) { + dev_warn(dev, "couldn't probe performance counters\n"); + goto remove_clocks; + } + /* + * Setup default thresholds for the devfreq governor. + * The values are chosen based on experiments. + */ + dmc->gov_data.upthreshold = 30; + dmc->gov_data.downdifferential = 5; + + dmc->df = devm_devfreq_add_device(dev, &exynos5_dmc_df_profile, + DEVFREQ_GOV_USERSPACE, + &dmc->gov_data); + + if (IS_ERR(dmc->df)) { + ret = PTR_ERR(dmc->df); + goto err_devfreq_add; + } + + dev_info(&pdev->dev, "DMC init for prod_id=0x%08x pkg_id=0x%08x\n", + dmc->prod_rev, dmc->pkg_rev); + + return 0; + +err_devfreq_add: + exynos5_counters_disable_edev(dmc); +remove_clocks: + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); +remove_opp_table: + while (dmc->opp_count-- > 0) + dev_pm_opp_remove(dev, dmc->opp[dmc->opp_count].freq_khz); + + return ret; +} + +/** + * exynos5_dmc_remove() - Remove function for the platform device + * @pdev: platform device which is going to be removed + * + * The function relies on 'devm' framework function which automatically + * clean the device's resources. It just calls explicitly disable function for + * the performance counters. + */ +static int exynos5_dmc_remove(struct platform_device *pdev) +{ + struct exynos5_dmc *dmc = dev_get_drvdata(&pdev->dev); + + exynos5_counters_disable_edev(dmc); + + clk_disable_unprepare(dmc->mout_mx_mspll_ccore); + clk_disable_unprepare(dmc->mout_spll); + + dev_pm_opp_remove_table(&pdev->dev); + + dev_info(&pdev->dev, "DMC removed\n"); + + return 0; +} + +static const struct of_device_id exynos5_dmc_of_match[] = { + { .compatible = "samsung,exynos5422-dmc", }, + { }, +}; +MODULE_DEVICE_TABLE(of, exynos5_dmc_of_match); + +static struct platform_driver exynos5_dmc_platdrv = { + .probe = exynos5_dmc_probe, + .remove = exynos5_dmc_remove, + .driver = { + .name = "exynos5-dmc", + .of_match_table = exynos5_dmc_of_match, + }, +}; +module_platform_driver(exynos5_dmc_platdrv); +MODULE_DESCRIPTION(DRIVER_DESC); +MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Samsung"); From patchwork Thu Jan 31 08:49:51 2019 Content-Type: text/plain; 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Thu, 31 Jan 2019 08:50:07 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 5/8] dt-bindings: devfreq: add Exynos5422 DMC device description Date: Thu, 31 Jan 2019 09:49:51 +0100 Message-Id: <1548924594-19084-6-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJKsWRmVeSWpSXmKPExsWy7djP87oHtwXFGMybrmmxccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbdY ev0ik8XtxhVsFq17j7BbHH7Tzuog4LFm3hpGj02rOtk8Ni+p9zj4bg+TR9+WVYwenzfJBbBF cdmkpOZklqUW6dslcGXsuLCCraBLreL4/72sDYxN8l2MnBwSAiYS0/9/ZAKxhQRWMEocueII YX9hlJjTpNvFyAVkf2aU+LWigRGmYfGEV6wQieWMEg3LvrJDOEAdv9q2s3UxcnCwCehJ7FhV CNIgIlAtcef6fmaQGmaBO0wSe2cuZQFJCAuESlzu/MYKYrMIqErc/nYZ7AxeAS+JHUc+sUNs k5O4ea6TGcTmFPCWWNL1F2yQhMA2dol1jzZDneQicX13I5QtLPHq+BaoZhmJ/zvnM0HYxRJn O1axQdg1Eu0nd0DVWEscPn6RFeRoZgFNifW79CHCjhL/ly1kBglLCPBJ3HgrCBJmBjInbZsO FeaV6GgTgqjWkNjScwFqkZjE8jXToIZ7SLxesgsaVvMYJdZsPMM0gVF+FsKyBYyMqxjFU0uL c9NTi43yUsv1ihNzi0vz0vWS83M3MQIT0Ol/x7/sYNz1J+kQowAHoxIP74O1gTFCrIllxZW5 hxglOJiVRHgNf/vHCPGmJFZWpRblxxeV5qQWH2KU5mBREuetZngQLSSQnliSmp2aWpBaBJNl 4uCUamCcqCvd0vrsYxe72fzrP309W849ehX3y8w61fbMXelDIfMsmLfmHek+e0ba9uPqXd3P XCUa594t8JU7o3XoQFsp1xVJ+fOi7sG7RQ7JTuNeai4n+St7z+SjmhvNlPfFFGYaR1pPiPr5 YcsdzVMGRqn/f7z8sfeDq89kL4+DDp99NTsupDlo7n+lxFKckWioxVxUnAgANFTaFzwDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42I5/e/4Xd0D24JiDDZO0bbYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslss vX6RyeJ24wo2i9a9R9gtDr9pZ3UQ8Fgzbw2jx6ZVnWwem5fUexx8t4fJo2/LKkaPz5vkAtii 9GyK8ktLUhUy8otLbJWiDS2M9AwtLfSMTCz1DI3NY62MTJX07WxSUnMyy1KL9O0S9DJ2XFjB VtClVnH8/17WBsYm+S5GTg4JAROJxRNesXYxcnEICSxllNjVOZMVIiEmMWnfdnYIW1jiz7Uu NoiiT4wSfxfeAnI4ONgE9CR2rCoEqRERqJfof3OJDcRmFnjFJNHwXgPEFhYIljj58QVYnEVA VeL2t8tMIDavgJfEjiOfoObLSdw818kMYnMKeEss6foLZgsB1fz495FxAiPfAkaGVYwiqaXF uem5xUZ6xYm5xaV56XrJ+bmbGIExse3Yzy07GLveBR9iFOBgVOLhfbA2MEaINbGsuDL3EKME B7OSCK/hb/8YId6UxMqq1KL8+KLSnNTiQ4ymQEdNZJYSTc4HxmteSbyhqaG5haWhubG5sZmF kjjveYPKKCGB9MSS1OzU1ILUIpg+Jg5OqQZGWYvb7F9Y36odmN9h+PSgY6Ze1R/nm19OSv4K U3wzeWPxXJNdtf9/SPNfn5dd5pE10Z87QTAuSPjm/oMn6+K6nL5Hp8zri83aGJPrbrnpnfXe D5FlKt0LVLxqF+6smMUf4Jzru3XhIR9GXjFrw7PLI/SzWxQqpmRWZNeIPW3/yvejPYbt6S4l luKMREMt5qLiRADEVGnKnwIAAA== X-CMS-MailID: 20190131085009eucas1p14c96bc345bc4c414e6c4d7506f14e69c X-Msg-Generator: CA X-RootMTR: 20190131085009eucas1p14c96bc345bc4c414e6c4d7506f14e69c X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085009eucas1p14c96bc345bc4c414e6c4d7506f14e69c References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The patch adds description for DT binding for a new Exynos5422 Dynamic Memory Controller device. It also contains needed MAINTAINERS file update. CC: MyungJoo Ham CC: Kyungmin Park CC: Chanwoo Choi CC: Rob Herring CC: Mark Rutland CC: Kukjin Kim CC: Krzysztof Kozlowski CC: linux-pm@vger.kernel.org CC: linux-samsung-soc@vger.kernel.org CC: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-kernel@vger.kernel.org Signed-off-by: Lukasz Luba --- .../devicetree/bindings/devfreq/exynos5422-dmc.txt | 106 +++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 107 insertions(+) create mode 100644 Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt diff --git a/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt new file mode 100644 index 0000000..229efba --- /dev/null +++ b/Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt @@ -0,0 +1,106 @@ +* Exynos5422 frequency and voltage scaling for Dynamic Memory Controller device + +The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the DRAM +memory chips are connected. The driver is to monitor the controller in runtime +and switch frequency and voltage. To monitor the usage of the controller in +runtime, the driver uses the PPMU (Platform Performance Monitoring Unit), which +is able to measure the current load of the memory. +When 'userspace' governor is used for the driver, an application is able to +switch the DMC frequency. + +Required properties for DMC device for Exynos5422: +- compatible: Should be "samsung,exynos5422-bus". +- clock-names : the name of clock used by the bus, "bus". +- clocks : phandles for clock specified in "clock-names" property. +- devfreq-events : phandles for PPMU devices connected to this DMC. + +The example definition of a DMC and PPMU devices declared in DT is shown below: + + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + status = "okay"; + events { + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>, + <0x10030000 0x1000>, <0x10000000 0x1000>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_DOUT_CLK2X_PHY0>, + <&clock CLK_CLKM_PHY0>, + <&clock CLK_CLKM_PHY1>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + "dout_clk2x_phy0", + "clkm_phy0", + "clkm_phy1"; + + status = "okay"; + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>, + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>; + }; + + diff --git a/MAINTAINERS b/MAINTAINERS index e81dfbf..ab0d8a5 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3316,6 +3316,7 @@ L: linux-pm@vger.kernel.org L: linux-samsung-soc@vger.kernel.org S: Maintained F: drivers/devfreq/exynos5422-dmc.c +F: Documentation/devicetree/bindings/devfreq/exynos5422-dmc.txt BUSLOGIC SCSI DRIVER M: Khalid Aziz From patchwork Thu Jan 31 08:49:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10790051 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 9D36C746 for ; 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Thu, 31 Jan 2019 08:50:08 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Rob Herring , Mark Rutland , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 6/8] DT: arm: exynos: add DMC device for exynos5422 Date: Thu, 31 Jan 2019 09:49:52 +0100 Message-Id: <1548924594-19084-7-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrJKsWRmVeSWpSXmKPExsWy7djPc7qHtgXFGLx5LmexccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbdY ev0ik8XtxhVsFq17j7BbHH7Tzuog4LFm3hpGj02rOtk8Ni+p9zj4bg+TR9+WVYwenzfJBbBF cdmkpOZklqUW6dslcGU8m7yNtWCFQsWzDc/YGxi7JbsYOTgkBEwk/ky37WLk4hASWMEo8Xrb ViYI5wujxLo/v1ghnM+MEqv/b2XrYuQE6/h6dhobRGI5o8T7mR2scC0HOg+zgcxlE9CT2LGq EKRBRKBa4s71/cwgNcwCd5gk9s5cygKSEBZwk/h2Yg/YVBYBVYmP9yazgti8Al4S05dOY4XY Jidx81wnM4jNKeAtsaTrL9ggCYFt7BJ7L9xlgnjCRWJifxVEvbDEq+Nb2CFsGYn/O+czQdjF Emc7VkF9UCPRfnIHVI21xOHjF1lBxjALaEqs36UPEXaUmL3tDDPEdD6JG28FQcLMQOakbdOh wrwSHW1CENUaElt6LkAtEpNYvmYa1HAPiRnr7kCDah6jxMqfbawTGOVnISxbwMi4ilE8tbQ4 Nz212DgvtVyvODG3uDQvXS85P3cTIzABnf53/OsOxn1/kg4xCnAwKvHwPlgbGCPEmlhWXJl7 iFGCg1lJhNfwt3+MEG9KYmVValF+fFFpTmrxIUZpDhYlcd5qhgfRQgLpiSWp2ampBalFMFkm Dk6pBka5m9tvd79wuCYawGP8mteLY+fJ7+a7P5ud+q5rPp9t8rPcS4HqjTobH+3yfPnh9qlU runRCafKt/6Kn/XXwSTp7rkNx/xjzdSZxBfNfHggbR7Hwub2RpW7l1j/TqwyyP4x55rIj36h vHs5exlMog+WyZ1MsldqVtox8XtE4DVOv7d1Z4LXrRdUYinOSDTUYi4qTgQAvx2d2zwDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFuphkeLIzCtJLcpLzFFi42I5/e/4Xd2D24JiDBb0SllsnLGe1eL6l+es FvOPnGO16H/8mtni/PkN7BZnm96wW9xqkLHY9Pgaq8XlXXPYLD73HmG0mHF+H5PF2iN32S2W Xr/IZHG7cQWbReveI+wWh9+0szoIeKyZt4bRY9OqTjaPzUvqPQ6+28Pk0bdlFaPH501yAWxR ejZF+aUlqQoZ+cUltkrRhhZGeoaWFnpGJpZ6hsbmsVZGpkr6djYpqTmZZalF+nYJehnPJm9j LVihUPFswzP2BsZuyS5GTg4JAROJr2ensXUxcnEICSxllPi+bTsrREJMYtK+7ewQtrDEn2td UEWfGCV+3VvC0sXIwcEmoCexY1UhSI2IQL1E/5tLbCA2s8ArJomG9xogtrCAm8S3E3vA4iwC qhIf700Gm88r4CUxfek0qF1yEjfPdTKD2JwC3hJLuv6C2UJANT/+fWScwMi3gJFhFaNIamlx bnpusZFecWJucWleul5yfu4mRmBMbDv2c8sOxq53wYcYBTgYlXh4H6wNjBFiTSwrrsw9xCjB wawkwmv42z9GiDclsbIqtSg/vqg0J7X4EKMp0FETmaVEk/OB8ZpXEm9oamhuYWlobmxubGah JM573qAySkggPbEkNTs1tSC1CKaPiYNTqoGx482S+r79z/qPPbg1/1AqN0tQ/rJ7Ih3VS20+ 3dx57WSfkNmckMW1R9l38/5gO2HX9dmpbNn5V5PUy49rCzbtnXBmnfADoRdTrmf58B9dN1t+ bk3+A2ufOq1TCg8mPZ30mt3izBq5C8+0Qngz1HcFHkldEyHnw9Z+pmqL57ZFTzbqv6xMiejd qsRSnJFoqMVcVJwIAIJtK9efAgAA X-CMS-MailID: 20190131085009eucas1p166467551006e54130905ebb5eefdefab X-Msg-Generator: CA X-RootMTR: 20190131085009eucas1p166467551006e54130905ebb5eefdefab X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085009eucas1p166467551006e54130905ebb5eefdefab References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add description of Dynamic Memory Controller and PPMU counters. They are used by exynos5422-dmc driver. CC: Rob Herring CC: Mark Rutland CC: Kukjin Kim CC: Krzysztof Kozlowski CC: devicetree@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-samsung-soc@vger.kernel.org CC: linux-kernel@vger.kernel.org Signed-off-by: Lukasz Luba --- arch/arm/boot/dts/exynos5420.dtsi | 78 +++++++++++++++++++++++++++ arch/arm/boot/dts/exynos5422-odroid-core.dtsi | 22 ++++++++ 2 files changed, 100 insertions(+) diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index aaff158..574d398 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -235,6 +235,36 @@ status = "disabled"; }; + dmc: memory-controller@10c20000 { + compatible = "samsung,exynos5422-dmc"; + reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>, + <0x10030000 0x1000>, <0x10000000 0x1000>; + clocks = <&clock CLK_FOUT_SPLL>, + <&clock CLK_MOUT_SCLK_SPLL>, + <&clock CLK_FF_DOUT_SPLL2>, + <&clock CLK_FOUT_BPLL>, + <&clock CLK_MOUT_BPLL>, + <&clock CLK_SCLK_BPLL>, + <&clock CLK_MOUT_MX_MSPLL_CCORE>, + <&clock CLK_MOUT_MX_MSPLL_CCORE_PHY>, + <&clock CLK_MOUT_MCLK_CDREX>, + <&clock CLK_DOUT_CLK2X_PHY0>, + <&clock CLK_CLKM_PHY0>, + <&clock CLK_CLKM_PHY1>; + clock-names = "fout_spll", + "mout_sclk_spll", + "ff_dout_spll2", + "fout_bpll", + "mout_bpll", + "sclk_bpll", + "mout_mx_mspll_ccore", + "mout_mx_mspll_ccore_phy", + "mout_mclk_cdrex", + "dout_clk2x_phy0", + "clkm_phy0", + "clkm_phy1"; + }; + nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; reg = <0x10CA1000 0x200>; @@ -271,6 +301,54 @@ status = "disabled"; }; + ppmu_dmc0_0: ppmu@10d00000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d00000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_0: ppmu-event3-dmc0_0 { + event-name = "ppmu-event3-dmc0_0"; + }; + }; + }; + + ppmu_dmc0_1: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d10000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX0_1>; + clock-names = "ppmu"; + events { + ppmu_event_dmc0_1: ppmu-event3-dmc0_1 { + event-name = "ppmu-event3-dmc0_1"; + }; + }; + }; + + ppmu_dmc1_0: ppmu@10d10000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d60000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_0>; + clock-names = "ppmu"; + events { + ppmu_event_dmc1_0: ppmu-event3-dmc1_0 { + event-name = "ppmu-event3-dmc1_0"; + }; + }; + }; + + ppmu_dmc1_1: ppmu@10d70000 { + compatible = "samsung,exynos-ppmu"; + reg = <0x10d70000 0x2000>; + clocks = <&clock CLK_PCLK_PPMU_DREX1_1>; + clock-names = "ppmu"; + events { + ppmu_event_dmc1_1: ppmu-event3-dmc1_1 { + event-name = "ppmu-event3-dmc1_1"; + }; + }; + }; + gsc_pd: power-domain@10044000 { compatible = "samsung,exynos4210-pd"; reg = <0x10044000 0x20>; diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index bf09eab..e2b59e9 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -127,6 +127,12 @@ cpu-supply = <&buck2_reg>; }; +&dmc { + devfreq-events = <&ppmu_dmc0_0>, <&ppmu_dmc0_1>, + <&ppmu_dmc1_0>, <&ppmu_dmc1_1>; + status = "okay"; +}; + &hsi2c_4 { status = "okay"; @@ -535,6 +541,22 @@ }; }; +&ppmu_dmc0_0 { + status = "okay"; +}; + +&ppmu_dmc0_1 { + status = "okay"; +}; + +&ppmu_dmc1_0 { + status = "okay"; +}; + +&ppmu_dmc1_1 { + status = "okay"; +}; + &tmu_cpu0 { vtmu-supply = <&ldo7_reg>; }; From patchwork Thu Jan 31 08:49:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10790057 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id EDC1C13B5 for ; Thu, 31 Jan 2019 08:50:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EE867301EB for ; Thu, 31 Jan 2019 08:50:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E2ED7303B0; Thu, 31 Jan 2019 08:50:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,MAILING_LIST_MULTI,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5FD0930221 for ; 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Thu, 31 Jan 2019 08:50:09 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 7/8] drivers: devfreq: events: add Exynos PPMU new events Date: Thu, 31 Jan 2019 09:49:53 +0100 Message-Id: <1548924594-19084-8-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprNKsWRmVeSWpSXmKPExsWy7djPc7qHtwXFGOxcIG6xccZ6VovrX56z Wsw/co7Vov/xa2aL8+c3sFucbXrDbnGrQcZi0+NrrBaXd81hs/jce4TRYsb5fUwWa4/cZbe4 3biCzeLwm3ZWBz6PTas62Tw2L6n3OPhuD5NH35ZVjB6fN8kFsEZx2aSk5mSWpRbp2yVwZRyY OIWl4DJnxdIvb9gaGNdzdDFyckgImEhcbu9j7GLk4hASWMEo8ejfBzYI5wujxJbT65khnM+M Em1P5rLBtNzpXsACkVjOKLH6/A9GuJZpV54wdTFycLAJ6EnsWFUI0iAiUC1x5/p+sEnMApOZ JBad7mYCSQgL+Eh0rzrAAmKzCKhK3Ln1EyzOK+Al8XfnZnaIbXISN891MoPYnALeEku6/oIN khBYxC6xcOVtFogiF4kDz/uhzhOWeHV8C1SzjMT/nfOZIOxiibMdq6BqaiTaT+6AqrGWOHz8 IivI0cwCmhLrd+lDhB0l5l8+wwYSlhDgk7jxVhAkzAxkTto2nRkizCvR0SYEUa0hsaXnAtQi MYnla6ZBDfeQOLD0Ktj1QgLzgIHYVz+BUX4Wwq4FjIyrGMVTS4tz01OLjfNSy/WKE3OLS/PS 9ZLzczcxApPM6X/Hv+5g3Pcn6RCjAAejEg/vg7WBMUKsiWXFlbmHGCU4mJVEeA1/+8cI8aYk VlalFuXHF5XmpBYfYpTmYFES561meBAtJJCeWJKanZpakFoEk2Xi4JRqYJx5YHrXpUzzxyu3 JelfKbmx/qXqzn03Z60qPvgpLafu/xJP/ea1i6d9OO6+OSThSG1kbMa9q6odX9VM9tlybQo8 EbWhQdFmTcG1RAXu51baFVNmf9ztsOVabxqT/4rPP65HeH+fM/WQWpvG/ZjOlZvt1a4084gf VSxXX/pj90yXn+Kzddcu37RSiaU4I9FQi7moOBEACmvLYC4DAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrHLMWRmVeSWpSXmKPExsVy+t/xu7qHtgXFGDR9ZLXYOGM9q8X1L89Z LeYfOcdq0f/4NbPF+fMb2C3ONr1ht7jVIGOx6fE1VovLu+awWXzuPcJoMeP8PiaLtUfuslvc blzBZnH4TTurA5/HplWdbB6bl9R7HHy3h8mjb8sqRo/Pm+QCWKP0bIryS0tSFTLyi0tslaIN LYz0DC0t9IxMLPUMjc1jrYxMlfTtbFJSczLLUov07RL0Mg5MnMJScJmzYumXN2wNjOs5uhg5 OSQETCTudC9g6WLk4hASWMooMa3xPCtEQkxi0r7t7BC2sMSfa11sEEWfGCVO35wG5HBwsAno SexYVQhSIyJQL9H/5hJYDbPAfCaJ/ilzwQYJC/hIdK86wAJiswioSty59ZMJxOYV8JL4u3Mz 1AI5iZvnOplBbE4Bb4klXX/BbCGgmh//PjJOYORbwMiwilEktbQ4Nz232EivODG3uDQvXS85 P3cTIzDstx37uWUHY9e74EOMAhyMSjy8D9YGxgixJpYVV+YeYpTgYFYS4TX87R8jxJuSWFmV WpQfX1Sak1p8iNEU6KiJzFKiyfnAmMwriTc0NTS3sDQ0NzY3NrNQEuc9b1AZJSSQnliSmp2a WpBaBNPHxMEp1cCoHbf9yDvfS3/tj254LjGvUFx/I3/nJeuET7bH9iVFlMT7TuIJOfQvNmiy 2/olvWvLv4icEMpi8BLduE999x1dU+fIaGbp5c+79lbHlazeYb79VuezT6bnrwkk3T7g+u/J l9W2Th7WKpv+HrAI0dsnfjGfKZ7x+57dZhI6+QwT1Jnkcg5lpFopsRRnJBpqMRcVJwIApfer V5ECAAA= X-CMS-MailID: 20190131085010eucas1p2b2bdc90be27dfd73f13d41ed0d725bb2 X-Msg-Generator: CA X-RootMTR: 20190131085010eucas1p2b2bdc90be27dfd73f13d41ed0d725bb2 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085010eucas1p2b2bdc90be27dfd73f13d41ed0d725bb2 References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Define new performance events supported by Exynos5422 SoC counters. The counters are built-in in Dynamic Memory Controller and provide information regarding memory utilization. CC: Chanwoo Choi CC: MyungJoo Ham CC: Kyungmin Park CC: Kukjin Kim CC: Krzysztof Kozlowski CC: linux-pm@vger.kernel.org CC: linux-arm-kernel@lists.infradead.org CC: linux-samsung-soc@vger.kernel.org CC: linux-kernel@vger.kernel.org Signed-off-by: Lukasz Luba --- drivers/devfreq/event/exynos-ppmu.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/devfreq/event/exynos-ppmu.c b/drivers/devfreq/event/exynos-ppmu.c index c61de0b..67d6674 100644 --- a/drivers/devfreq/event/exynos-ppmu.c +++ b/drivers/devfreq/event/exynos-ppmu.c @@ -89,6 +89,12 @@ static struct __exynos_ppmu_events { PPMU_EVENT(d1-cpu), PPMU_EVENT(d1-general), PPMU_EVENT(d1-rt), + + /* For Exynos5422 SoC */ + PPMU_EVENT(dmc0_0), + PPMU_EVENT(dmc0_1), + PPMU_EVENT(dmc1_0), + PPMU_EVENT(dmc1_1), }; static int exynos_ppmu_find_ppmu_id(struct devfreq_event_dev *edev) From patchwork Thu Jan 31 08:49:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lukasz Luba X-Patchwork-Id: 10790029 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6CCFD746 for ; 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Thu, 31 Jan 2019 08:50:10 +0000 (GMT) From: Lukasz Luba To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-samsung-soc@vger.kernel.org Cc: b.zolnierkie@samsung.com, krzk@kernel.org, kgene@kernel.org, cw00.choi@samsung.com, kyungmin.park@samsung.com, m.szyprowski@samsung.com, s.nawrocki@samsung.com, myungjoo.ham@samsung.com, Lukasz Luba , Russell King , Guenter Roeck , Benson Leung , linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 8/8] ARM: exynos_defconfig: enable DMC driver Date: Thu, 31 Jan 2019 09:49:54 +0100 Message-Id: <1548924594-19084-9-git-send-email-l.luba@partner.samsung.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0VSe0hTcRTut3vvdh2urlP0oKa0MLKHD7D4gSEWBpceWFoUZdjKi4lu6m5a ptKU8pWWGGqopYVOG4o511KzNF2ZDjUT1KxEKog0I3yRiJV7WP995zvfd75z4NCEVE+50jHK i5xKKY+TCcWk4dXSwM5uQ1iE3/ST7bjpTiOFS78Mk3h0/iuFK40DFO6b0hD41udpAg8OPhLh /szvIjyudse6zyMUHm6rEOK5AiPCdwafC3BX8TOEG4wfRfh9Rp0Qd3/PpoId2OGRIYItVw+R rE6bK2Sbq6+yL360C9ibei1i53QeR0SnxHuiuLiYZE7lG3RWfGFpVkcmGOnL32r0AjV6KcpD djQwATBTdZ3MQ2JaytQh+Ln4VGAt5hGsmMoIazGHoGyiiVqz1M+/tllqETzVlBP/LBWFk6t+ mhYyPtCiTTQbnJhU+DDaYdEQTBYBDYu9AnPDkQmGsfYC0oxJxgs+FHdYeAlzAFoftiNrmge8 G8glzNiOOQjVeSuWQcD0iWBWM2lbKQQ+fm22XeQIUz16G3aHP62VAivmoT9HK7TiNMjubbFp AqG7Z4gyL00w3tDY5mul98Kza+8tNDDrYWzGwUwTq7DIUEpYaQnkZEmt6q2gz39jC3KG2voS 23AWappvWS6RMvcQjDyBQuRZ9j+rCiEtcuGSeEU0x/sruUs+vFzBJymjfc7HK3Ro9ZdMv3tm W9DC23NdiKGRzF4y2XA0QkrJk/kURRcCmpA5SfyXQyOkkih5yhVOFR+pSorj+C7kRpMyF0nq usnTUiZafpGL5bgETrXWFdB2rmrkvUFRbmeKK443hCs1J25wCUWG5BG3ps1RvhLP2MOdkWTi guOQOjLdOLwYybql5o0HHusucSzLvy/+dHB++cGuiZUz+7bfzZyoDt+2+9ftkDSvTVvEpo3G 2iz+kF+oJExas3O5kzJl2CvqT46VP96friGOB6cHebnIdc7GzIAdCzKSvyD330aoePlfVwvN 3EcDAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprGIsWRmVeSWpSXmKPExsVy+t/xu7qHtgXFGBy6bWqxccZ6VovpTy6z WFz/8pzVYv6Rc6wWp14tY7bof/ya2eL8+Q3sFmeb3rBb3GqQsdj0+BqrxeVdc9gsPvceYbSY cX4fk8WhqXsZLdYeuctucbtxBZvF4TftrA6CHpevXWT2mN1wkcVj06pONo/NS+o9Dr7bw+TR t2UVo8fnTXIB7FF6NkX5pSWpChn5xSW2StGGFkZ6hpYWekYmlnqGxuaxVkamSvp2NimpOZll qUX6dgl6GT8/bWIpOMJR8XLpFqYGxqPsXYycHBICJhJrvpxg6WLk4hASWMoocbD/CyNEQkxi 0r7tUEXCEn+udbGB2EICnxglvu6U6mLk4GAT0JPYsaoQJCwiUC/R/+YSG8gcZoEpzBKL599h BUkICzhI3NjTywJiswioStyZup8JxOYV8JLYuXIP1C45iZvnOplBbE4Bb4klXX+ZIXZ5Sfz4 95FxAiPfAkaGVYwiqaXFuem5xYZ6xYm5xaV56XrJ+bmbGIFxsu3Yz807GC9tDD7EKMDBqMTD +2BtYIwQa2JZcWXuIUYJDmYlEV7D3/4xQrwpiZVVqUX58UWlOanFhxhNgY6ayCwlmpwPjOG8 knhDU0NzC0tDc2NzYzMLJXHe8waVUUIC6YklqdmpqQWpRTB9TBycUg2M+Vlmmo4KkyRX/V6R 2rwpXTmHv2zRTtadQTM8X72ee2ABQ/6Xdp1/HH2Hpr3+knfrqm0Gp2GRipjLjtL23VO6iru7 mG1+5fxtfxGym5e9nbNm4W1Hn6Tv+bm//KZlFz76di3p16X1f26/z+o9Z/+w9vrLSkb1mnNt 75f8v6IztahT9afjIctlSizFGYmGWsxFxYkAxGpN0qkCAAA= X-CMS-MailID: 20190131085011eucas1p2c315d69c8902fbceff689f3a92e0c5d9 X-Msg-Generator: CA X-RootMTR: 20190131085011eucas1p2c315d69c8902fbceff689f3a92e0c5d9 X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20190131085011eucas1p2c315d69c8902fbceff689f3a92e0c5d9 References: <1548924594-19084-1-git-send-email-l.luba@partner.samsung.com> Sender: linux-pm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Enable driver for Dynamic Memory Controller dynamic frequency and voltage scaling in Exynos5422 SoCs. CC: Russell King CC: Kukjin Kim CC: Krzysztof Kozlowski CC: Marek Szyprowski CC: Guenter Roeck CC: Benson Leung CC: linux-arm-kernel@lists.infradead.org CC: linux-samsung-soc@vger.kernel.org CC: linux-kernel@vger.kernel.org Signed-off-by: Lukasz Luba --- arch/arm/configs/exynos_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index d635edf..b5dddcc 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -291,6 +291,7 @@ CONFIG_DEVFREQ_GOV_PERFORMANCE=y CONFIG_DEVFREQ_GOV_POWERSAVE=y CONFIG_DEVFREQ_GOV_USERSPACE=y CONFIG_ARM_EXYNOS_BUS_DEVFREQ=y +CONFIG_ARM_EXYNOS5422_DMC_DEVFREQ=y CONFIG_DEVFREQ_EVENT_EXYNOS_NOCP=y CONFIG_EXYNOS_IOMMU=y CONFIG_EXTCON=y