From patchwork Tue Apr 18 18:10:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216053 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B696AC77B7E for ; Tue, 18 Apr 2023 18:11:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232603AbjDRSLb (ORCPT ); Tue, 18 Apr 2023 14:11:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231218AbjDRSL3 (ORCPT ); Tue, 18 Apr 2023 14:11:29 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 345031025C for ; Tue, 18 Apr 2023 11:11:19 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id v20-20020a05600c471400b003ed8826253aso1333645wmo.0 for ; Tue, 18 Apr 2023 11:11:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681841477; x=1684433477; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=PGEdXpbrAB9bzKbGp8NO/2PlgF61Tq+sqmR873iY16o=; b=D4+RUrwcyPbffPe96qXZM1OWA60iapoCnOWjcS2FRRhNKxyTVmbDZFyPOGFDlvS41B NaEp1CWtDkz2lg+YIFqA+hTg+m9DSJuCRsYtBmchmafvQ/JN7UhNaKBFdX+DyhkzoBNP +UlgkNx2WJmuP40tu7XV+TxFZEXO0QJM9M4jD3zAwGMJxqc8KGeJRPE2DNLUwUPSMknS CKTgzsJgnIspqlNzBqPPhcWr809jbKgsCbshYWJOuVeCy4fEGM8rsn632zoZaqf+5AiM 5S62y01rtBGlV8cadAgJKkjkzMC+KuH3BdvWjKVkjFxQHlYWTye29h3iF+SdqY0WeSg6 m24Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681841477; x=1684433477; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PGEdXpbrAB9bzKbGp8NO/2PlgF61Tq+sqmR873iY16o=; b=lsNFgwQ73X9oDjg0jQVtR4yBvj28U5MamiYbSy80iGD43Tio+/cxkkKFG6J/pjEJO2 Q63dvUSd1jI8UJeoxIUELf9AhDFCYYOkhFyZxpOKpQGlFAc8Sak5gcU41k+B68kN7MhK Pnr5dOC5jK2kogD5WJs6iSLURYzIZOUcs/sjBal7ZpLY6BOCb1qCB5HHO6L7XOIeRyUp pEBkKyk8hRqIZNjKdccNXEPNSZrutZKVuf4lNCmz3FA4dFJbAKLvgRzZwy0zl+bG0eTH n+EQi5fViJbQWL/T9jdEOAxLWLrBGUpz6grF2bV/MiJY5Iz8l8Wr+Cw8ZJTzl1mKkN9u 4C4Q== X-Gm-Message-State: AAQBX9d56hRTKzORNXsSbqwnf3ZnyAb2rUTwYwnitgLSW1vC22BWYlKz zMJoJMSVjLzA5Iu5Sasptfbg X-Google-Smtp-Source: AKy350bYnn4jHS5URPe6bTfBxOdYvUUb4URy+ztI9QdK6i3OqnYsarUufClbfvVtyqskp5G8whGoPQ== X-Received: by 2002:a05:600c:22c7:b0:3f0:5887:bea3 with SMTP id 7-20020a05600c22c700b003f05887bea3mr14377190wmg.27.1681841477500; Tue, 18 Apr 2023 11:11:17 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id r17-20020a5d4e51000000b002f01e181c4asm13727898wrt.5.2023.04.18.11.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 11:11:17 -0700 (PDT) From: Arnaud Vrac Date: Tue, 18 Apr 2023 20:10:43 +0200 Subject: [PATCH 1/4] drm/msm: add some cec register bitfield details MIME-Version: 1.0 Message-Id: <20230418-msm8998-hdmi-cec-v1-1-176479fb2fce@freebox.fr> References: <20230418-msm8998-hdmi-cec-v1-0-176479fb2fce@freebox.fr> In-Reply-To: <20230418-msm8998-hdmi-cec-v1-0-176479fb2fce@freebox.fr> To: Rob Clark , Hans Verkuil , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: David Airlie , Daniel Vetter , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3874; i=avrac@freebox.fr; h=from:subject:message-id; bh=SVkTAlMIdLXUuPBcPdMnLFItEApcr9xvliEg/2oQQDY=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkPt05Q2xMOypajlyQfFQFeWvrZ5qZzytnpP01G 0Ea1IIjyGiJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD7dOQAKCRBxA//ZuzQ0 q+irEACiYxpnV98wcf5XF7eYxq5xeg08MigztVevneCvbFlJhTBa53k32OD0Cvu+Igd9/tTFnzE 0ELuJXyNi7TCcdwwMbWmMO7Yg1Z5ufFbXoKmMc1bHwAi8oykgRjkwZ6NE+oH3QQBbEDfTS+Jk/7 LBa2Kfwahyu4SvV7RcPv7WOIZ7p5IxTjbQ9bwKDQ4vWtI4eqXbCh+boiF8PgbgR1kYMy2P0lW9K C2aMQkiH3HC2/rsqsrBPOYqpNkB/iqnG7Sh88WaQuy/1ZL1gkpWRSihfLaF9O8egBZx9LjIsVli in2HnbYmGN/krwEUGaCwF0AgPSMcBKnbS7PrIlc83Il6uJyIxzMGuRcbekcNyi3+gondeuFghXV MYDHrsNK1D2PJokeGcp++f4ZT8MbSnQFg88x2RB3RUiJVC+uNn3viu0RAesPPS/DMaHB1KjtYmO k6t4vb9s6GXaY3smXw1n0uZ+MhDdKpgAokm3vTZRnqFaYHMmaj78/ALi/qXawrOHCQs431UYQ4n +mZGUkOJjIb6BUDHYOWexiU0E1G1FUbuEzeh6aCFgGmoKSM58cf1pf9V9fd/MY95GzjmvJVmCng A2doa8zHKLGwtZJXoaQMZ0GTQguao9U1/1toAbMoLknuTtIjxYVP8HeH34g84rAJ3Ae/ea46uLt 0PEO+UPzt2WVtMA== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The register names and bitfields were determined from the downstream msm-4.4 driver. Signed-off-by: Arnaud Vrac Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/hdmi/hdmi.xml.h | 62 ++++++++++++++++++++++++++++++++++++- 1 file changed, 61 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h index 973b460486a5a..b4dd6e8cba6b7 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.xml.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.xml.h @@ -76,6 +76,13 @@ enum hdmi_acr_cts { ACR_48 = 3, }; +enum hdmi_cec_tx_status { + CEC_TX_OK = 0, + CEC_TX_NACK = 1, + CEC_TX_ARB_LOSS = 2, + CEC_TX_MAX_RETRIES = 3, +}; + #define REG_HDMI_CTRL 0x00000000 #define HDMI_CTRL_ENABLE 0x00000001 #define HDMI_CTRL_HDMI 0x00000002 @@ -476,20 +483,73 @@ static inline uint32_t HDMI_DDC_REF_REFTIMER(uint32_t val) #define REG_HDMI_HDCP_SW_LOWER_AKSV 0x00000288 #define REG_HDMI_CEC_CTRL 0x0000028c +#define HDMI_CEC_CTRL_ENABLE 0x00000001 +#define HDMI_CEC_CTRL_SEND_TRIGGER 0x00000002 +#define HDMI_CEC_CTRL_FRAME_SIZE__MASK 0x000001f0 +#define HDMI_CEC_CTRL_FRAME_SIZE__SHIFT 4 +static inline uint32_t HDMI_CEC_CTRL_FRAME_SIZE(uint32_t val) +{ + return ((val) << HDMI_CEC_CTRL_FRAME_SIZE__SHIFT) & HDMI_CEC_CTRL_FRAME_SIZE__MASK; +} +#define HDMI_CEC_CTRL_LINE_OE 0x00000200 #define REG_HDMI_CEC_WR_DATA 0x00000290 +#define HDMI_CEC_WR_DATA_BROADCAST 0x00000001 +#define HDMI_CEC_WR_DATA_DATA__MASK 0x0000ff00 +#define HDMI_CEC_WR_DATA_DATA__SHIFT 8 +static inline uint32_t HDMI_CEC_WR_DATA_DATA(uint32_t val) +{ + return ((val) << HDMI_CEC_WR_DATA_DATA__SHIFT) & HDMI_CEC_WR_DATA_DATA__MASK; +} -#define REG_HDMI_CEC_CEC_RETRANSMIT 0x00000294 +#define REG_HDMI_CEC_RETRANSMIT 0x00000294 +#define HDMI_CEC_RETRANSMIT_ENABLE 0x00000001 +#define HDMI_CEC_RETRANSMIT_COUNT__MASK 0x000000fe +#define HDMI_CEC_RETRANSMIT_COUNT__SHIFT 1 +static inline uint32_t HDMI_CEC_RETRANSMIT_COUNT(uint32_t val) +{ + return ((val) << HDMI_CEC_RETRANSMIT_COUNT__SHIFT) & HDMI_CEC_RETRANSMIT_COUNT__MASK; +} #define REG_HDMI_CEC_STATUS 0x00000298 +#define HDMI_CEC_STATUS_BUSY 0x00000001 +#define HDMI_CEC_STATUS_TX_FRAME_DONE 0x00000008 +#define HDMI_CEC_STATUS_TX_STATUS__MASK 0x000000f0 +#define HDMI_CEC_STATUS_TX_STATUS__SHIFT 4 +static inline uint32_t HDMI_CEC_STATUS_TX_STATUS(enum hdmi_cec_tx_status val) +{ + return ((val) << HDMI_CEC_STATUS_TX_STATUS__SHIFT) & HDMI_CEC_STATUS_TX_STATUS__MASK; +} #define REG_HDMI_CEC_INT 0x0000029c +#define HDMI_CEC_INT_TX_DONE 0x00000001 +#define HDMI_CEC_INT_TX_DONE_MASK 0x00000002 +#define HDMI_CEC_INT_TX_ERROR 0x00000004 +#define HDMI_CEC_INT_TX_ERROR_MASK 0x00000008 +#define HDMI_CEC_INT_MONITOR 0x00000010 +#define HDMI_CEC_INT_MONITOR_MASK 0x00000020 +#define HDMI_CEC_INT_RX_DONE 0x00000040 +#define HDMI_CEC_INT_RX_DONE_MASK 0x00000080 #define REG_HDMI_CEC_ADDR 0x000002a0 #define REG_HDMI_CEC_TIME 0x000002a4 +#define HDMI_CEC_TIME_ENABLE 0x00000001 +#define HDMI_CEC_TIME_SIGNAL_FREE_TIME__MASK 0x0000ff80 +#define HDMI_CEC_TIME_SIGNAL_FREE_TIME__SHIFT 7 +static inline uint32_t HDMI_CEC_TIME_SIGNAL_FREE_TIME(uint32_t val) +{ + return ((val) << HDMI_CEC_TIME_SIGNAL_FREE_TIME__SHIFT) & HDMI_CEC_TIME_SIGNAL_FREE_TIME__MASK; +} #define REG_HDMI_CEC_REFTIMER 0x000002a8 +#define HDMI_CEC_REFTIMER_ENABLE 0x00010000 +#define HDMI_CEC_REFTIMER_REFTIMER__MASK 0x0000ffff +#define HDMI_CEC_REFTIMER_REFTIMER__SHIFT 0 +static inline uint32_t HDMI_CEC_REFTIMER_REFTIMER(uint32_t val) +{ + return ((val) << HDMI_CEC_REFTIMER_REFTIMER__SHIFT) & HDMI_CEC_REFTIMER_REFTIMER__MASK; +} #define REG_HDMI_CEC_RD_DATA 0x000002ac From patchwork Tue Apr 18 18:10:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 750CCC7EE20 for ; Tue, 18 Apr 2023 18:11:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232594AbjDRSLe (ORCPT ); Tue, 18 Apr 2023 14:11:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45542 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232576AbjDRSLa (ORCPT ); Tue, 18 Apr 2023 14:11:30 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9CCC118CD for ; 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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id r17-20020a5d4e51000000b002f01e181c4asm13727898wrt.5.2023.04.18.11.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 11:11:17 -0700 (PDT) From: Arnaud Vrac Date: Tue, 18 Apr 2023 20:10:44 +0200 Subject: [PATCH 2/4] drm/msm: add hdmi cec support MIME-Version: 1.0 Message-Id: <20230418-msm8998-hdmi-cec-v1-2-176479fb2fce@freebox.fr> References: <20230418-msm8998-hdmi-cec-v1-0-176479fb2fce@freebox.fr> In-Reply-To: <20230418-msm8998-hdmi-cec-v1-0-176479fb2fce@freebox.fr> To: Rob Clark , Hans Verkuil , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: David Airlie , Daniel Vetter , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=12091; i=avrac@freebox.fr; h=from:subject:message-id; bh=oUde66qHUtY/Iy3OeVfYl6UO61Y9HAsr6+CW5la4fOA=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkPt0+4eICf2235GeN+nmVx5Dd/f5/DEem6xSyZ Pa50jBvKLmJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD7dPgAKCRBxA//ZuzQ0 q+oOEACI77yKyXBZt7FRVV6trtAwNFceM4Njls+01wXXn6Ik7YgRTlaLF6DGEomowTF8FKQ0b6u PfQqSBBqL+VF6eJlEF+gPv5k22Rl41WyuBVA9Dw36uvCvkRCua94XXG5ATW1qnhGlOB9yDyybuf J8Lv5FU8fypvd+WmSJocznV8qETUu19lujOglUDho+DF8QB9gohFj+2Fe9VM10qB5FGuYdd5HHh wXDpuQFCpYMbCq/kIehIx459IJROgQYxkymowwFTRjYw5hiC5id18MgyAktsMTX/6wVw3fidJD0 ACRk7YM1EzI3+NyAQlEVKP4QYKjseanHCWClNQclnmGITAJg/FO4NyQhB+8aCgGG5ilEHysBAS6 71oPjkD770sQN/rfHeyfkdeqXPKlSaY9+NwRrVa11O0nouMOuNEAwg/+FOgEUe9c5jOLJ+iGQcR Br9453fims+VYbuaFRUit8uZNjSnWInVlN0nyyBK/LQynzNwlRNCMwhIzcbQ0XbhXmQnXDDHGm3 q4OCTkOCbSf9FYkYBDsaqqRDAX7rYNJnoNzJK19HD13OFmFbF+VfIvkVMPposKPjplzOOoJAtFP DhHpJR8y+jiIPQRr8PGcupWQjgD7HJq+yO9sj4YpfU0KchOPw0xURQZKHiV2cSp+gPcMXJVxwy5 4DTLPUwC+h6lL4Q== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Some Qualcomm SoCs that support HDMI also support CEC, including MSM8996 and MSM8998. The hardware block can handle a single CEC logical address and broadcast messages. Port the CEC driver from downstream msm-4.4 kernel. It has been tested on MSM8998 and passes the cec-compliance tool tests. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/Kconfig | 8 ++ drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/hdmi/hdmi.c | 15 ++ drivers/gpu/drm/msm/hdmi/hdmi.h | 18 +++ drivers/gpu/drm/msm/hdmi/hdmi_cec.c | 280 ++++++++++++++++++++++++++++++++++++ 5 files changed, 322 insertions(+) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 85f5ab1d552c4..2a02c74207935 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -165,3 +165,11 @@ config DRM_MSM_HDMI_HDCP default y help Choose this option to enable HDCP state machine + +config DRM_MSM_HDMI_CEC + bool "Enable HDMI CEC support in MSM DRM driver" + depends on DRM_MSM && DRM_MSM_HDMI + select CEC_CORE + default y + help + Choose this option to enable CEC support diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7274c41228ed9..0237a2f219ac2 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -131,6 +131,7 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o +msm-$(CONFIG_DRM_MSM_HDMI_CEC) += hdmi/hdmi_cec.o msm-$(CONFIG_DRM_MSM_HDMI_HDCP) += hdmi/hdmi_hdcp.o msm-$(CONFIG_DRM_MSM_DSI) += dsi/dsi.o \ diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.c b/drivers/gpu/drm/msm/hdmi/hdmi.c index 3132105a2a433..1dde3890e25c0 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi.c @@ -11,6 +11,8 @@ #include #include +#include + #include #include "hdmi.h" @@ -53,6 +55,9 @@ static irqreturn_t msm_hdmi_irq(int irq, void *dev_id) if (hdmi->hdcp_ctrl) msm_hdmi_hdcp_irq(hdmi->hdcp_ctrl); + /* Process CEC: */ + msm_hdmi_cec_irq(hdmi); + /* TODO audio.. */ return IRQ_HANDLED; @@ -66,6 +71,8 @@ static void msm_hdmi_destroy(struct hdmi *hdmi) */ if (hdmi->workq) destroy_workqueue(hdmi->workq); + + msm_hdmi_cec_exit(hdmi); msm_hdmi_hdcp_destroy(hdmi); if (hdmi->i2c) @@ -139,6 +146,8 @@ static int msm_hdmi_init(struct hdmi *hdmi) hdmi->hdcp_ctrl = NULL; } + msm_hdmi_cec_init(hdmi); + return 0; fail: @@ -198,6 +207,12 @@ int msm_hdmi_modeset_init(struct hdmi *hdmi, drm_connector_attach_encoder(hdmi->connector, hdmi->encoder); + if (hdmi->cec_adap) { + struct cec_connector_info conn_info; + cec_fill_conn_info_from_drm(&conn_info, hdmi->connector); + cec_s_conn_info(hdmi->cec_adap, &conn_info); + } + ret = devm_request_irq(dev->dev, hdmi->irq, msm_hdmi_irq, IRQF_TRIGGER_HIGH, "hdmi_isr", hdmi); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi.h b/drivers/gpu/drm/msm/hdmi/hdmi.h index e8dbee50637fa..c639bd87f4b8f 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi.h +++ b/drivers/gpu/drm/msm/hdmi/hdmi.h @@ -29,6 +29,7 @@ struct hdmi_audio { }; struct hdmi_hdcp_ctrl; +struct cec_adapter; struct hdmi { struct drm_device *dev; @@ -73,6 +74,7 @@ struct hdmi { struct workqueue_struct *workq; struct hdmi_hdcp_ctrl *hdcp_ctrl; + struct cec_adapter *cec_adap; /* * spinlock to protect registers shared by different execution @@ -261,4 +263,20 @@ static inline void msm_hdmi_hdcp_off(struct hdmi_hdcp_ctrl *hdcp_ctrl) {} static inline void msm_hdmi_hdcp_irq(struct hdmi_hdcp_ctrl *hdcp_ctrl) {} #endif +/* + * cec + */ +#ifdef CONFIG_DRM_MSM_HDMI_CEC +int msm_hdmi_cec_init(struct hdmi *hdmi); +void msm_hdmi_cec_exit(struct hdmi *hdmi); +void msm_hdmi_cec_irq(struct hdmi *hdmi); +#else +static inline int msm_hdmi_cec_init(struct hdmi *hdmi) +{ + return -ENXIO; +} +static inline void msm_hdmi_cec_exit(struct hdmi *hdmi) {} +static inline void msm_hdmi_cec_irq(struct hdmi *hdmi) {} +#endif + #endif /* __HDMI_CONNECTOR_H__ */ diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_cec.c b/drivers/gpu/drm/msm/hdmi/hdmi_cec.c new file mode 100644 index 0000000000000..51326e493e5da --- /dev/null +++ b/drivers/gpu/drm/msm/hdmi/hdmi_cec.c @@ -0,0 +1,280 @@ +#include +#include + +#include "hdmi.h" + +#define HDMI_CEC_INT_MASK ( \ + HDMI_CEC_INT_TX_DONE_MASK | \ + HDMI_CEC_INT_TX_ERROR_MASK | \ + HDMI_CEC_INT_RX_DONE_MASK) + +struct hdmi_cec_ctrl { + struct hdmi *hdmi; + struct work_struct work; + spinlock_t lock; + u32 irq_status; + u32 tx_status; + u32 tx_retransmits; +}; + +static int msm_hdmi_cec_adap_enable(struct cec_adapter *adap, bool enable) +{ + struct hdmi_cec_ctrl *cec_ctrl = adap->priv; + struct hdmi *hdmi = cec_ctrl->hdmi; + + if (enable) { + /* timer frequency, 19.2Mhz * 0.05ms / 1000ms = 960 */ + hdmi_write(hdmi, REG_HDMI_CEC_REFTIMER, + HDMI_CEC_REFTIMER_REFTIMER(960) | + HDMI_CEC_REFTIMER_ENABLE); + + /* read and write timings */ + hdmi_write(hdmi, REG_HDMI_CEC_RD_RANGE, 0x30AB9888); + hdmi_write(hdmi, REG_HDMI_CEC_WR_RANGE, 0x888AA888); + hdmi_write(hdmi, REG_HDMI_CEC_RD_START_RANGE, 0x88888888); + hdmi_write(hdmi, REG_HDMI_CEC_RD_TOTAL_RANGE, 0x99); + + /* start bit low pulse duration, 3.7ms */ + hdmi_write(hdmi, REG_HDMI_CEC_RD_ERR_RESP_LO, 74); + + /* signal free time, 7 * 2.4ms */ + hdmi_write(hdmi, REG_HDMI_CEC_TIME, + HDMI_CEC_TIME_SIGNAL_FREE_TIME(7 * 48) | + HDMI_CEC_TIME_ENABLE); + + hdmi_write(hdmi, REG_HDMI_CEC_COMPL_CTL, 0xF); + hdmi_write(hdmi, REG_HDMI_CEC_WR_CHECK_CONFIG, 0x4); + hdmi_write(hdmi, REG_HDMI_CEC_RD_FILTER, BIT(0) | (0x7FF << 4)); + + hdmi_write(hdmi, REG_HDMI_CEC_INT, HDMI_CEC_INT_MASK); + hdmi_write(hdmi, REG_HDMI_CEC_CTRL, HDMI_CEC_CTRL_ENABLE); + } else { + hdmi_write(hdmi, REG_HDMI_CEC_INT, 0); + hdmi_write(hdmi, REG_HDMI_CEC_CTRL, 0); + cancel_work_sync(&cec_ctrl->work); + } + + return 0; +} + +static int msm_hdmi_cec_adap_log_addr(struct cec_adapter *adap, u8 logical_addr) +{ + struct hdmi_cec_ctrl *cec_ctrl = adap->priv; + struct hdmi *hdmi = cec_ctrl->hdmi; + + hdmi_write(hdmi, REG_HDMI_CEC_ADDR, logical_addr & 0xF); + + return 0; +} + +static int msm_hdmi_cec_adap_transmit(struct cec_adapter *adap, u8 attempts, + u32 signal_free_time, struct cec_msg *msg) +{ + struct hdmi_cec_ctrl *cec_ctrl = adap->priv; + struct hdmi *hdmi = cec_ctrl->hdmi; + u8 retransmits; + u32 broadcast; + u32 status; + int i; + + /* toggle cec in order to flush out bad hw state, if any */ + hdmi_write(hdmi, REG_HDMI_CEC_CTRL, 0); + hdmi_write(hdmi, REG_HDMI_CEC_CTRL, HDMI_CEC_CTRL_ENABLE); + + /* flush register writes */ + wmb(); + + retransmits = attempts ? (attempts - 1) : 0; + hdmi_write(hdmi, REG_HDMI_CEC_RETRANSMIT, + HDMI_CEC_RETRANSMIT_ENABLE | + HDMI_CEC_RETRANSMIT_COUNT(retransmits)); + + broadcast = cec_msg_is_broadcast(msg) ? HDMI_CEC_WR_DATA_BROADCAST : 0; + for (i = 0; i < msg->len; i++) { + hdmi_write(hdmi, REG_HDMI_CEC_WR_DATA, + HDMI_CEC_WR_DATA_DATA(msg->msg[i]) | broadcast); + } + + /* check line status */ + if (read_poll_timeout(hdmi_read, status, !(status & HDMI_CEC_STATUS_BUSY), + 5, 1000, false, hdmi, REG_HDMI_CEC_STATUS)) { + pr_err("CEC line is busy. Retry failed\n"); + return -EBUSY; + } + + cec_ctrl->tx_retransmits = retransmits; + + /* start transmission */ + hdmi_write(hdmi, REG_HDMI_CEC_CTRL, + HDMI_CEC_CTRL_ENABLE | + HDMI_CEC_CTRL_SEND_TRIGGER | + HDMI_CEC_CTRL_FRAME_SIZE(msg->len) | + HDMI_CEC_CTRL_LINE_OE); + + return 0; +} + +static void msm_hdmi_cec_adap_free(struct cec_adapter *adap) +{ + struct hdmi_cec_ctrl *cec_ctrl = adap->priv; + + cec_ctrl->hdmi->cec_adap = NULL; + kfree(cec_ctrl); +} + +static const struct cec_adap_ops msm_hdmi_cec_adap_ops = { + .adap_enable = msm_hdmi_cec_adap_enable, + .adap_log_addr = msm_hdmi_cec_adap_log_addr, + .adap_transmit = msm_hdmi_cec_adap_transmit, + .adap_free = msm_hdmi_cec_adap_free, +}; + +#define CEC_IRQ_FRAME_WR_DONE 0x01 +#define CEC_IRQ_FRAME_RD_DONE 0x02 + +static void msm_hdmi_cec_handle_rx_done(struct hdmi_cec_ctrl *cec_ctrl) +{ + struct hdmi *hdmi = cec_ctrl->hdmi; + struct cec_msg msg = {}; + u32 data; + int i; + + data = hdmi_read(hdmi, REG_HDMI_CEC_RD_DATA); + msg.len = (data & 0x1f00) >> 8; + if (msg.len < 1 || msg.len > CEC_MAX_MSG_SIZE) + return; + + msg.msg[0] = data & 0xff; + for (i = 1; i < msg.len; i++) + msg.msg[i] = hdmi_read(hdmi, REG_HDMI_CEC_RD_DATA) & 0xff; + + cec_received_msg(hdmi->cec_adap, &msg); +} + +static void msm_hdmi_cec_handle_tx_done(struct hdmi_cec_ctrl *cec_ctrl) +{ + struct hdmi *hdmi = cec_ctrl->hdmi; + u32 tx_status; + + tx_status = (cec_ctrl->tx_status & HDMI_CEC_STATUS_TX_STATUS__MASK) >> + HDMI_CEC_STATUS_TX_STATUS__SHIFT; + + switch (tx_status) { + case 0: + cec_transmit_done(hdmi->cec_adap, + CEC_TX_STATUS_OK, 0, 0, 0, 0); + break; + case 1: + cec_transmit_done(hdmi->cec_adap, + CEC_TX_STATUS_NACK, 0, 1, 0, 0); + break; + case 2: + cec_transmit_done(hdmi->cec_adap, + CEC_TX_STATUS_ARB_LOST, 1, 0, 0, 0); + break; + case 3: + cec_transmit_done(hdmi->cec_adap, + CEC_TX_STATUS_MAX_RETRIES | + CEC_TX_STATUS_NACK, + 0, cec_ctrl->tx_retransmits + 1, 0, 0); + break; + default: + cec_transmit_done(hdmi->cec_adap, + CEC_TX_STATUS_ERROR, 0, 0, 0, 1); + break; + } +} + +static void msm_hdmi_cec_work(struct work_struct *work) +{ + struct hdmi_cec_ctrl *cec_ctrl = + container_of(work, struct hdmi_cec_ctrl, work); + unsigned long flags; + + spin_lock_irqsave(&cec_ctrl->lock, flags); + + if (cec_ctrl->irq_status & CEC_IRQ_FRAME_WR_DONE) + msm_hdmi_cec_handle_tx_done(cec_ctrl); + + if (cec_ctrl->irq_status & CEC_IRQ_FRAME_RD_DONE) + msm_hdmi_cec_handle_rx_done(cec_ctrl); + + cec_ctrl->irq_status = 0; + cec_ctrl->tx_status = 0; + + spin_unlock_irqrestore(&cec_ctrl->lock, flags); +} + +void msm_hdmi_cec_irq(struct hdmi *hdmi) +{ + struct hdmi_cec_ctrl *cec_ctrl; + unsigned long flags; + u32 int_status; + + if (!hdmi->cec_adap) + return; + + cec_ctrl = hdmi->cec_adap->priv; + + int_status = hdmi_read(hdmi, REG_HDMI_CEC_INT); + if (!(int_status & HDMI_CEC_INT_MASK)) + return; + + spin_lock_irqsave(&cec_ctrl->lock, flags); + + if (int_status & (HDMI_CEC_INT_TX_DONE | HDMI_CEC_INT_TX_ERROR)) { + cec_ctrl->tx_status = hdmi_read(hdmi, REG_HDMI_CEC_STATUS); + cec_ctrl->irq_status |= CEC_IRQ_FRAME_WR_DONE; + } + + if (int_status & HDMI_CEC_INT_RX_DONE) + cec_ctrl->irq_status |= CEC_IRQ_FRAME_RD_DONE; + + spin_unlock_irqrestore(&cec_ctrl->lock, flags); + + hdmi_write(hdmi, REG_HDMI_CEC_INT, int_status); + queue_work(hdmi->workq, &cec_ctrl->work); +} + +int msm_hdmi_cec_init(struct hdmi *hdmi) +{ + struct platform_device *pdev = hdmi->pdev; + struct hdmi_cec_ctrl *cec_ctrl; + struct cec_adapter *cec_adap; + int ret; + + cec_ctrl = kzalloc(sizeof (*cec_ctrl), GFP_KERNEL); + if (!cec_ctrl) + return -ENOMEM; + + cec_ctrl->hdmi = hdmi; + INIT_WORK(&cec_ctrl->work, msm_hdmi_cec_work); + + cec_adap = cec_allocate_adapter(&msm_hdmi_cec_adap_ops, + cec_ctrl, "msm", + CEC_CAP_DEFAULTS | + CEC_CAP_CONNECTOR_INFO, 1); + ret = PTR_ERR_OR_ZERO(cec_adap); + if (ret < 0) { + kfree(cec_ctrl); + return ret; + } + + /* Set the logical address to Unregistered */ + hdmi_write(hdmi, REG_HDMI_CEC_ADDR, 0xf); + + ret = cec_register_adapter(cec_adap, &pdev->dev); + if (ret < 0) { + cec_delete_adapter(cec_adap); + return ret; + } + + hdmi->cec_adap = cec_adap; + + return 0; +} + +void msm_hdmi_cec_exit(struct hdmi *hdmi) +{ + cec_unregister_adapter(hdmi->cec_adap); +} From patchwork Tue Apr 18 18:10:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216056 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA704C7EE23 for ; Tue, 18 Apr 2023 18:11:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232579AbjDRSLf (ORCPT ); Tue, 18 Apr 2023 14:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45540 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232585AbjDRSLa (ORCPT ); Tue, 18 Apr 2023 14:11:30 -0400 Received: from mail-wm1-x329.google.com (mail-wm1-x329.google.com [IPv6:2a00:1450:4864:20::329]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43661125AF for ; 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[213.36.7.13]) by smtp.gmail.com with ESMTPSA id r17-20020a5d4e51000000b002f01e181c4asm13727898wrt.5.2023.04.18.11.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 11:11:18 -0700 (PDT) From: Arnaud Vrac Date: Tue, 18 Apr 2023 20:10:45 +0200 Subject: [PATCH 3/4] drm/msm: expose edid to hdmi cec adapter MIME-Version: 1.0 Message-Id: <20230418-msm8998-hdmi-cec-v1-3-176479fb2fce@freebox.fr> References: <20230418-msm8998-hdmi-cec-v1-0-176479fb2fce@freebox.fr> In-Reply-To: <20230418-msm8998-hdmi-cec-v1-0-176479fb2fce@freebox.fr> To: Rob Clark , Hans Verkuil , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: David Airlie , Daniel Vetter , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2444; i=avrac@freebox.fr; h=from:subject:message-id; bh=yMD8mdwL4UzuJ4urozm6hkE+ei92Sv5WQC0tT/4Y284=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkPt1Au6G3IkSntJhVUGBaSFWYzjeSj1NkCTBEJ 2uswfMwbxeJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD7dQAAKCRBxA//ZuzQ0 q/Z5D/oD2ynykDobHdfCHo4jJyvHCyzcEClszedW90E66HWQkHzocu8iInucyPKIJBw7jwUVhu/ 5QEH1stGvm4psJzhRZygTYp97ZWaowMkkFU8cQ2E36mNkHkd4UnYgzd7Zu/Fb64tk9IkY0DalVa FeKCUacXpHz8jfU5VUB6gV+XgzwIO0aCvoFhuDqbNuNbedlPBUPne1lU5rDGxQexvcrc7YV8vUg vOVy0F81ppX3Na5k/bZvjz30L2QV4dWmLryMcKi5PbmbhWme611xnledh7sA6TVc4VZNGjM9A0M tGrf6azq2/otDOPSD7zXSPcbPcTf2lXdIhGyI+m9g/zAsNEFkCwSGsbUyBN8b/b90tCipeEaiXD ZBZk3oooZvtcOVlDEzequ2KxNBWSPhV+czQR4C7ijyveRip2uneKEUgcSLfwrIRO6ikTA0lp1+L sTjOrepDFAGt4dlju9+ej+U/aWuFpuhFxK15g6utEIW2E9SPChSRN+NjEVpjpZe0Q/1leOUK8EK QNpdvPpH0WEohlEqexojwNpRXzzZqBiTo9btswZygERbRAYL2q39XWq153dce1yMPxd9lfK2wkz hCGPnxV2izV69PTzbAiRAcJGQuMBphx5uROUM7YpUGXkQsT1jxouQLe9aIaQ8vY+kaWZR9xSiy2 XXqaMH2SFM4z3EQ== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org When edid has been read after hpd, pass it to the cec adapter so that it can extract the physical address of the device on the cec bus. Invalidate the physical address when hpd is low. Signed-off-by: Arnaud Vrac --- drivers/gpu/drm/msm/hdmi/hdmi_bridge.c | 2 ++ drivers/gpu/drm/msm/hdmi/hdmi_hpd.c | 17 +++++++++++++---- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c index 9b1391d27ed39..efc3bd4908e83 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "msm_kms.h" #include "hdmi.h" @@ -256,6 +257,7 @@ static struct edid *msm_hdmi_bridge_get_edid(struct drm_bridge *bridge, hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); edid = drm_get_edid(connector, hdmi->i2c); + cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c index bfa827b479897..cb3eb2625ff63 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_hpd.c @@ -7,6 +7,7 @@ #include #include #include +#include #include "msm_kms.h" #include "hdmi.h" @@ -230,15 +231,17 @@ enum drm_connector_status msm_hdmi_bridge_detect( { struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); struct hdmi *hdmi = hdmi_bridge->hdmi; - enum drm_connector_status stat_gpio, stat_reg; + enum drm_connector_status status, stat_gpio, stat_reg; int retry = 20; /* * some platforms may not have hpd gpio. Rely only on the status * provided by REG_HDMI_HPD_INT_STATUS in this case. */ - if (!hdmi->hpd_gpiod) - return detect_reg(hdmi); + if (!hdmi->hpd_gpiod) { + status = detect_reg(hdmi); + goto out; + } do { stat_gpio = detect_gpio(hdmi); @@ -259,5 +262,11 @@ enum drm_connector_status msm_hdmi_bridge_detect( DBG("hpd gpio tells us: %d", stat_gpio); } - return stat_gpio; + status = stat_gpio; + +out: + if (!status) + cec_phys_addr_invalidate(hdmi->cec_adap); + + return status; } From patchwork Tue Apr 18 18:10:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arnaud Vrac X-Patchwork-Id: 13216055 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6D7E0C77B7D for ; Tue, 18 Apr 2023 18:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232588AbjDRSLh (ORCPT ); Tue, 18 Apr 2023 14:11:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45584 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232597AbjDRSLa (ORCPT ); Tue, 18 Apr 2023 14:11:30 -0400 Received: from mail-wm1-x335.google.com (mail-wm1-x335.google.com [IPv6:2a00:1450:4864:20::335]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 647F6125B7 for ; Tue, 18 Apr 2023 11:11:20 -0700 (PDT) Received: by mail-wm1-x335.google.com with SMTP id q5so15959295wmo.4 for ; Tue, 18 Apr 2023 11:11:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebox-fr.20221208.gappssmtp.com; s=20221208; t=1681841479; x=1684433479; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GNLIbIkfDv+9349rG8wTY2HZ2mEpz3z6lx+72T5OpbY=; b=SUTeE+ozxQY5RhTCnjTwf3vRx8fch7xurY/TcHvAu3mvNTADJdpe04DhRsrbBXQUqe IW5NMdyiwDKQg6xbyZnXi2/jI6AfE450oll3yfEuSqowh3vgLAu8N2rbIrh8ETBv71Lr ZX1wXDk1J2+JxCKeDZayNPH7+ROzgquwXBi7tCBwk8CdnXs06GeZaj01b/PN1+nzXREH XMoE4qd9GbrjLG2Pkw7zE4V6W4/TUEcG/ThdniegBfyPwhqd/WyWs2NyhMr4kY1tvdTq /UUcAo9G65h+3NKUBY/VpgUiEsPNph5iPaivWo9/Kx6O5XgA2Oq94hCaOd/fW+eSVX4l Muzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1681841479; x=1684433479; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GNLIbIkfDv+9349rG8wTY2HZ2mEpz3z6lx+72T5OpbY=; b=RKupM7D8v+tL4Dbk88C3ducxl48vYTE+UsNvv6impQx/4HCreDvb2EbJx0imeH56VR TcIdp6uFpS0FvjeOejjjvZYGOYcG9PD77DIkRm3v5+KnpLS9ofJH7HEC2xWDSUJffIzz uGXTFu584S4hcW6aOtQsjOx2fW0Ii+CyMbXb+st9leB4xYslFpixXrAnnLtfKLIyUFnh 67hnqyhX6CkWVQrPLc6Zz/HuQy5o328O75V/yjwpF8Y8UW1KLQprN80AptbmAQeEkwwP jvuVcRZVlH5AfFwXPAXKG6Pyu1/ct/Hv2yd3gF2xym8VFKWM7e6XLpvbaN2uUCiq+3PT T/JA== X-Gm-Message-State: AAQBX9fm91ht06TFvbmlFd/Fd6XASXaDb8URZjKaEc3uBDrk30DKF8rS fZrU2hD7By29ndxoI/r/Oe4HZQ38bI4B7QAztg== X-Google-Smtp-Source: AKy350Y5K0w4P5Hu/xmAlBYeiNvJQgzuQzVozBZ6pzBvgykN4f1OfOXSepZHQfDqZzGBeqIzYvE8iQ== X-Received: by 2002:a05:600c:378b:b0:3f1:7aff:e14a with SMTP id o11-20020a05600c378b00b003f17affe14amr1848693wmr.39.1681841478783; Tue, 18 Apr 2023 11:11:18 -0700 (PDT) Received: from [127.0.1.1] (freebox.vlq16.iliad.fr. [213.36.7.13]) by smtp.gmail.com with ESMTPSA id r17-20020a5d4e51000000b002f01e181c4asm13727898wrt.5.2023.04.18.11.11.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 18 Apr 2023 11:11:18 -0700 (PDT) From: Arnaud Vrac Date: Tue, 18 Apr 2023 20:10:46 +0200 Subject: [PATCH 4/4] arm64: dts: qcom: msm8998: add hdmi cec pinctrl nodes MIME-Version: 1.0 Message-Id: <20230418-msm8998-hdmi-cec-v1-4-176479fb2fce@freebox.fr> References: <20230418-msm8998-hdmi-cec-v1-0-176479fb2fce@freebox.fr> In-Reply-To: <20230418-msm8998-hdmi-cec-v1-0-176479fb2fce@freebox.fr> To: Rob Clark , Hans Verkuil , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: David Airlie , Daniel Vetter , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, Arnaud Vrac X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=951; i=avrac@freebox.fr; h=from:subject:message-id; bh=fhrPgtytI/VRf0IiIxFCjsL95vuhTLfx4rQMFZjeLTM=; b=owEBbQKS/ZANAwAIAXED/9m7NDSrAcsmYgBkPt1CWxkNDZ9xyVgrYUSeHM9gk5iCCYafwuF5k Ek74p4mhkuJAjMEAAEIAB0WIQSUwb/ndwkXHdZ/QQZxA//ZuzQ0qwUCZD7dQgAKCRBxA//ZuzQ0 qxTREACDQikHrhslKZwbsvjGDHuH/n8bR1jRpYMGyyM42c2rXK72uLu+mE2oinXZKGo4ge4GyFs Vs10d4qYZ+ai2tO0sPWS3VqfH+aV3EUa/45uSnINhdHDCix1v55ns/ct7OIrhqze65zXnFWjBn4 rIpTwZZD8ptnfu3PD75W/4ednMa5qv4Cq5A+6iTWTDb4SoXJozQhASgIg6s8rw01fkBNnn8Tj3J ZTxhXe425Um/gVIvv9kIY22q+WbFunBHcVCgaNn2KxKENqjrr85J+lTHp1/Q7f5GxEE9zAQdmlR OO8OQoaWgPrTFdbm0Nif9zIBKJSwhcqUWEkYnwqGQozK+XTvpBH1lAOzw0jmP0yoq2/O1gtPQGK 8O3MgBGaAjW5WmijllyFMueqo/jxNdQY6CKTwECS0qAt5mhQR+DJHeUNjxQnP/Zco32SE1l+iV9 gFP2eJe54nL1JTRpGIFwaQtggunIoXcQ6gHIq7+J+G8wDLYQWXgDPEHFrWLRKhgxRJAKYmjefZj +zA8frDDKGIihpD46oo0E2Rl5E/CXKB0c8RBPup1sCCjUYsbzucmyn80FAX+c+O5L1QRAKkeM4P /6hS1LEt3R4s5hLh04mmfmoNM9eoA+6hSHyyotiVLyOlGnbSji/sVGQiAx80aQvNaMaNqS1Sh3h QBWinVFanysKJWw== X-Developer-Key: i=avrac@freebox.fr; a=openpgp; fpr=6225092072BB58E3CEEC091E75392A176D952DB4 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org HDMI is not enabled yet on msm8998 so the pinctrl nodes are not used. Signed-off-by: Arnaud Vrac --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index b150437a83558..fb4aa376ef117 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -1312,6 +1312,20 @@ blsp2_i2c6_sleep: blsp2-i2c6-sleep-state { drive-strength = <2>; bias-pull-up; }; + + hdmi_cec_default: hdmi-cec-default-state { + pins = "gpio31"; + function = "hdmi_cec"; + drive-strength = <2>; + bias-pull-up; + }; + + hdmi_cec_sleep: hdmi-cec-sleep-state { + pins = "gpio31"; + function = "hdmi_cec"; + drive-strength = <2>; + bias-pull-up; + }; }; remoteproc_mss: remoteproc@4080000 {