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Wed, 19 Apr 2023 16:41:42 +0000 From: Frank Li To: helgaas@kernel.org Cc: imx@lists.linux.dev, bhelgaas@google.com, devicetree@vger.kernel.org, frank.li@nxp.com, gustavo.pimentel@synopsys.com, kw@linux.com, leoyang.li@nxp.com, linux-arm-kernel@lists.infradead.org, linux-imx@nxp.com, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lorenzo.pieralisi@arm.com, minghuan.lian@nxp.com, mingkai.hu@nxp.com, robh+dt@kernel.org, roy.zang@nxp.com, shawnguo@kernel.org, zhiqiang.hou@nxp.com Subject: [PATCH v3 1/2] PCI: dwc: Implement general suspend/resume functionality for L2/L3 transitions Date: Wed, 19 Apr 2023 12:41:17 -0400 Message-Id: <20230419164118.596300-1-Frank.Li@nxp.com> X-Mailer: git-send-email 2.34.1 X-ClientProxiedBy: SJ0PR13CA0163.namprd13.prod.outlook.com (2603:10b6:a03:2c7::18) To AM6PR04MB4838.eurprd04.prod.outlook.com (2603:10a6:20b:4::16) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM6PR04MB4838:EE_|PA4PR04MB7535:EE_ X-MS-Office365-Filtering-Correlation-Id: 9cbf5b88-9d24-4602-48bf-08db40f4f463 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Added API pme_turn_off and exit_from_l2 for managing L2/L3 state transitions. Typical L2 entry workflow: 1. Transmit PME turn off signal to PCI devices. 2. Await link entering L2_IDLE state. 3. Transition Root complex to D3 state. Typical L2 exit workflow: 1. Transition Root complex to D0 state. 2. Issue exit from L2 command. 3. Reinitialize PCI host. 4. Wait for link to become active. Signed-off-by: Frank Li --- Change from v2 to v3: - Basic rewrite whole patch according rob herry suggestion. put common function into dwc, so more soc can share the same logic. .../pci/controller/dwc/pcie-designware-host.c | 80 +++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.h | 28 +++++++ 2 files changed, 108 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 9952057c8819..ef6869488bde 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -8,6 +8,7 @@ * Author: Jingoo Han */ +#include #include #include #include @@ -807,3 +808,82 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) return 0; } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); + +/* + * There are for configuring host controllers, which are bridges *to* PCI devices + * but are not PCI devices themselves. + */ +static void dw_pcie_set_dstate(struct dw_pcie *pci, u32 dstate) +{ + u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_PM); + u32 val; + + val = dw_pcie_readw_dbi(pci, offset + PCI_PM_CTRL); + val &= ~PCI_PM_CTRL_STATE_MASK; + val |= dstate; + dw_pcie_writew_dbi(pci, offset + PCI_PM_CTRL, val); +} + +int dw_pcie_suspend_noirq(struct dw_pcie *pci) +{ + u32 val; + int ret; + + if (dw_pcie_get_ltssm(pci) <= DW_PCIE_LTSSM_DETECT_ACT) + return 0; + + pci->pp.ops->pme_turn_off(&pci->pp); + + /* + * PCI Express Base Specification Rev 4.0 + * 5.3.3.2.1 PME Synchronization + * Recommand 1ms to 10ms timeout to check L2 ready + */ + ret = read_poll_timeout(dw_pcie_get_ltssm, val, val == DW_PCIE_LTSSM_L2_IDLE, + 100, 10000, false, pci); + if (ret) { + dev_err(pci->dev, "PCIe link enter L2 timeout! ltssm = 0x%x\n", val); + return ret; + } + + dw_pcie_set_dstate(pci, 0x3); + + pci->suspended = true; + + return ret; +} +EXPORT_SYMBOL_GPL(dw_pcie_suspend_noirq); + +int dw_pcie_resume_noirq(struct dw_pcie *pci) +{ + int ret; + + if (!pci->suspended) + return 0; + + pci->suspended = false; + + dw_pcie_set_dstate(pci, 0x0); + + pci->pp.ops->exit_from_l2(&pci->pp); + + /* delay 10 ms to access EP */ + mdelay(10); + + ret = pci->pp.ops->host_init(&pci->pp); + if (ret) { + dev_err(pci->dev, "ls_pcie_host_init failed! ret = 0x%x\n", ret); + return ret; + } + + dw_pcie_setup_rc(&pci->pp); + + ret = dw_pcie_wait_for_link(pci); + if (ret) { + dev_err(pci->dev, "wait link up timeout! ret = 0x%x\n", ret); + return ret; + } + + return ret; +} +EXPORT_SYMBOL_GPL(dw_pcie_resume_noirq); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 79713ce075cc..effb07a506e4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -288,10 +288,21 @@ enum dw_pcie_core_rst { DW_PCIE_NUM_CORE_RSTS }; +enum dw_pcie_ltssm { + DW_PCIE_LTSSM_UNKNOWN = 0xFFFFFFFF, + /* Need align PCIE_PORT_DEBUG0 bit0:5 */ + DW_PCIE_LTSSM_DETECT_QUIET = 0x0, + DW_PCIE_LTSSM_DETECT_ACT = 0x1, + DW_PCIE_LTSSM_L0 = 0x11, + DW_PCIE_LTSSM_L2_IDLE = 0x15, +}; + struct dw_pcie_host_ops { int (*host_init)(struct dw_pcie_rp *pp); void (*host_deinit)(struct dw_pcie_rp *pp); int (*msi_host_init)(struct dw_pcie_rp *pp); + void (*pme_turn_off)(struct dw_pcie_rp *pp); + void (*exit_from_l2)(struct dw_pcie_rp *pp); }; struct dw_pcie_rp { @@ -364,6 +375,7 @@ struct dw_pcie_ops { void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); int (*link_up)(struct dw_pcie *pcie); + enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); void (*stop_link)(struct dw_pcie *pcie); }; @@ -393,6 +405,7 @@ struct dw_pcie { struct reset_control_bulk_data app_rsts[DW_PCIE_NUM_APP_RSTS]; struct reset_control_bulk_data core_rsts[DW_PCIE_NUM_CORE_RSTS]; struct gpio_desc *pe_rst; + bool suspended; }; #define to_dw_pcie_from_pp(port) container_of((port), struct dw_pcie, pp) @@ -430,6 +443,9 @@ void dw_pcie_iatu_detect(struct dw_pcie *pci); int dw_pcie_edma_detect(struct dw_pcie *pci); void dw_pcie_edma_remove(struct dw_pcie *pci); +int dw_pcie_suspend_noirq(struct dw_pcie *pci); +int dw_pcie_resume_noirq(struct dw_pcie *pci); + static inline void dw_pcie_writel_dbi(struct dw_pcie *pci, u32 reg, u32 val) { dw_pcie_write_dbi(pci, reg, 0x4, val); @@ -501,6 +517,18 @@ static inline void dw_pcie_stop_link(struct dw_pcie *pci) pci->ops->stop_link(pci); } +static inline enum dw_pcie_ltssm dw_pcie_get_ltssm(struct dw_pcie *pci) +{ + u32 val; + + if (pci->ops && pci->ops->get_ltssm) + return pci->ops->get_ltssm(pci); + + val = dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0); + + return (enum dw_pcie_ltssm)FIELD_GET(PORT_LOGIC_LTSSM_STATE_MASK, val); +} + #ifdef CONFIG_PCIE_DW_HOST irqreturn_t dw_handle_msi_irq(struct dw_pcie_rp *pp); int dw_pcie_setup_rc(struct dw_pcie_rp *pp); From patchwork Wed Apr 19 16:41:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 13217140 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DFA2C77B78 for ; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MGZISI2TuvIhJ6wl1Tq41UCIDQaT1+un4CCqENtVD1/we3cwpJUyipraegFVGLVvPxnaS39I5oFK4pMM4wd8YnjPrUksZ4KaOTutsvWmBJrqkrPZhS93jEZOUrkRDrPWuI7Mi6SeJ1k/xUWGwYBffnAHZ8o+jffjfoDsLnR4s/z1kZpUy8IcaDHhXV4SKrAdtYs0l3vHnKGey+Rt0DS6fNeKdz6f9254Q6L/wuTKYbcvjBuF82CictWg+E9use+0sfSReUOlAWZm7urhpxPOXrWwGrv49oF+OTWATpix5q1auF0W6/cmWv9ERVNESQg9ayc4nOUvnd4Hh2x/DcRXB/cTzZ6/2rzkyQjgJxNiyzHpNvxgRS5Sa91v6306bX5SeHiSTtQlSbN9UQLJEukw84VdVhPIAF0d/PTMdUhUDhwME+s0QKSJVDqJyhLLl3rW6MaG+UMph8SLJji44qEmkIAOVyyUjNqtbE+IsS0PGoL/uOlUXbFu2E58psRjXQ3Ir9NN3iEsR/eTe6Rp48QGjf0QrbhN4N9t9Qrsv4pSM31K1CUi5u+TSFjkfz+GSQ70mwuYvMcfrkuA+PPVyi3ldkMfdE0TJ9omOGptShZJZwMMQ8Bo69Kegg561gcIZKqsn1hYZ3pKfZc4nCG51OFDRQN3q1m62ts6/aYn2Wn2mr8mDUdjHhcAMkfhwvrb9P+JdI0mzNM2tQhaEuAnv7EcxkVIoYXSi7Pz1CheAEgWpayFBj7ByXmTncg4PId8FXFNJ90Rg3C/FnW++IMJe8sZQwHFjcTdcMOKF63xQPgFxmRVYpgiYODxjwtuGFZOxmPFiLWHeLamsP7+EX12/WNpv6JfdKpmVFYW5XRnpXzM7TSJm24ndBAH7nvYc0Ddwx+dmLT6QxQpL9spFQ8j+5cJXyjdAQa2k5KIuPTka0z+yYEOG8fjuDeSBZ8zm3cAFUlkICUEeSln1cCGeKYwlYDheF6xm6RV/HOlFsPRdByLK5VbG57Nf1H/0J1G51GzhGrBDlY6BNq7avKrqe7m+TB0NfB+A9ntzn1W+GHRkNuJFVu0K0kkYBAwp11IKyRniL7VqsxrDTKmeq2NYDV6cetlNshMZkJuHRk1bWOC3gPNfzJdJxHIucRYxcLBxvJfIng70WGkk0vmA5Q5JXXq7rRX7yroCVfm4b4RphgZpPZmhLzA5/u7851Vv27ywNS2LJyDnCugbMzXA0x52G9HC2nS53FtSOVqngn7OzBLxkcdQos+N8kN5+u2EQe78D1q8vxjB2GLUMps3XMaQ434tIJ1QPcHk7vEqs4AZXjmvne9ilUP7NAZkDImj1cy1gDeXyj1RyGULD33hnfKkGBgsXFR0tq45KPZbVMQp8lpNG0Xc7xv7Halvrj9lCjsGXpuI+bISZ9xDzt0cWyuqXXnn9ReXUWBWcdZTw9qh7qkKlIu+kFGzZcL+njEBBa6nEgetNML9dehlzwND/u39NEFTHHiCZ8lnkqjheYd8gAFqDRK1zUYRM+Y2IOUh9vXSeznfXp2kA8uzIRsjauEtxwqnwnYYcxBlzu9oG6OHp5fUF9+DvM9o3jVnLPrAa1R9eUCPdVh X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7af25212-e5ae-4870-b685-08db40f4f748 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4838.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Apr 2023 16:41:47.1355 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: WNxNMi82DKeoSz/lGPNjO0Fmz3GoSL//H6Y4HIAtX6Rd8rtebmHyyT+fQYOx0EbjpCgomzdDBlHS4DrynTuIQw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR04MB7535 Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org From: Hou Zhiqiang Add PME_Turn_Off/PME_TO_Ack handshake sequence, and finally put the PCIe controller into D3 state after the L2/L3 ready state transition process completion. Signed-off-by: Hou Zhiqiang Signed-off-by: Frank Li --- - Basic rewrite whole patch according rob herry suggestion. put common function into dwc, so more soc can share the same logic. drivers/pci/controller/dwc/pci-layerscape.c | 148 ++++++++++++++++++-- 1 file changed, 139 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pci-layerscape.c b/drivers/pci/controller/dwc/pci-layerscape.c index ed5fb492fe08..32832d74a074 100644 --- a/drivers/pci/controller/dwc/pci-layerscape.c +++ b/drivers/pci/controller/dwc/pci-layerscape.c @@ -8,9 +8,11 @@ * Author: Minghuan Lian */ +#include #include #include #include +#include #include #include #include @@ -27,12 +29,33 @@ #define PCIE_ABSERR 0x8d0 /* Bridge Slave Error Response Register */ #define PCIE_ABSERR_SETTING 0x9401 /* Forward error of non-posted request */ +/* PF Message Command Register */ +#define LS_PCIE_PF_MCR 0x2c +#define PF_MCR_PTOMR BIT(0) +#define PF_MCR_EXL2S BIT(1) + #define PCIE_IATU_NUM 6 +struct ls_pcie; + +struct ls_pcie_drvdata { + const u32 pf_off; + const u32 lut_off; + bool pm_support; +}; + struct ls_pcie { struct dw_pcie *pci; + const struct ls_pcie_drvdata *drvdata; + void __iomem *pf_base; + void __iomem *lut_base; + bool big_endian; + bool ep_presence; + struct regmap *scfg; + int index; }; +#define ls_pcie_pf_readl_addr(addr) ls_pcie_pf_readl(pcie, addr) #define to_ls_pcie(x) dev_get_drvdata((x)->dev) static bool ls_pcie_is_bridge(struct ls_pcie *pcie) @@ -73,6 +96,57 @@ static void ls_pcie_fix_error_response(struct ls_pcie *pcie) iowrite32(PCIE_ABSERR_SETTING, pci->dbi_base + PCIE_ABSERR); } +static u32 ls_pcie_pf_readl(struct ls_pcie *pcie, u32 off) +{ + if (pcie->big_endian) + return ioread32be(pcie->pf_base + off); + + return ioread32(pcie->pf_base + off); +} + +static void ls_pcie_pf_writel(struct ls_pcie *pcie, u32 off, u32 val) +{ + if (pcie->big_endian) + return iowrite32be(val, pcie->pf_base + off); + + return iowrite32(val, pcie->pf_base + off); + +} + +static void ls_pcie_send_turnoff_msg(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + int ret; + + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val |= PF_MCR_PTOMR; + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + val, !(val & PF_MCR_PTOMR), 100, 10000); + if (ret) + dev_info(pcie->pci->dev, "poll turn off message timeout\n"); +} + +static void ls_pcie_exit_from_l2(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); + struct ls_pcie *pcie = to_ls_pcie(pci); + u32 val; + int ret; + + val = ls_pcie_pf_readl(pcie, LS_PCIE_PF_MCR); + val |= PF_MCR_EXL2S; + ls_pcie_pf_writel(pcie, LS_PCIE_PF_MCR, val); + + ret = readx_poll_timeout(ls_pcie_pf_readl_addr, LS_PCIE_PF_MCR, + val, !(val & PF_MCR_EXL2S), 100, 10000); + if (ret) + dev_info(pcie->pci->dev, "poll exit L2 state timeout\n"); +} + static int ls_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -91,18 +165,33 @@ static int ls_pcie_host_init(struct dw_pcie_rp *pp) static const struct dw_pcie_host_ops ls_pcie_host_ops = { .host_init = ls_pcie_host_init, + .pme_turn_off = ls_pcie_send_turnoff_msg, + .exit_from_l2 = ls_pcie_exit_from_l2, +}; + +static const struct ls_pcie_drvdata ls1021a_drvdata = { +}; + +static const struct ls_pcie_drvdata ls1043a_drvdata = { + .lut_off = 0x10000, +}; + +static const struct ls_pcie_drvdata layerscape_drvdata = { + .lut_off = 0x80000, + .pf_off = 0xc0000, + .pm_support = true, }; static const struct of_device_id ls_pcie_of_match[] = { - { .compatible = "fsl,ls1012a-pcie", }, - { .compatible = "fsl,ls1021a-pcie", }, - { .compatible = "fsl,ls1028a-pcie", }, - { .compatible = "fsl,ls1043a-pcie", }, - { .compatible = "fsl,ls1046a-pcie", }, - { .compatible = "fsl,ls2080a-pcie", }, - { .compatible = "fsl,ls2085a-pcie", }, - { .compatible = "fsl,ls2088a-pcie", }, - { .compatible = "fsl,ls1088a-pcie", }, + { .compatible = "fsl,ls1012a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1021a-pcie", .data = &ls1021a_drvdata }, + { .compatible = "fsl,ls1028a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1043a-pcie", .data = &ls1043a_drvdata }, + { .compatible = "fsl,ls1046a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2080a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2085a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls2088a-pcie", .data = &layerscape_drvdata }, + { .compatible = "fsl,ls1088a-pcie", .data = &layerscape_drvdata }, { }, }; @@ -121,6 +210,8 @@ static int ls_pcie_probe(struct platform_device *pdev) if (!pci) return -ENOMEM; + pcie->drvdata = of_device_get_match_data(dev); + pci->dev = dev; pci->pp.ops = &ls_pcie_host_ops; @@ -131,6 +222,14 @@ static int ls_pcie_probe(struct platform_device *pdev) if (IS_ERR(pci->dbi_base)) return PTR_ERR(pci->dbi_base); + pcie->big_endian = of_property_read_bool(dev->of_node, "big-endian"); + + if (pcie->drvdata->lut_off) + pcie->lut_base = pci->dbi_base + pcie->drvdata->lut_off; + + if (pcie->drvdata->pf_off) + pcie->pf_base = pci->dbi_base + pcie->drvdata->pf_off; + if (!ls_pcie_is_bridge(pcie)) return -ENODEV; @@ -139,12 +238,43 @@ static int ls_pcie_probe(struct platform_device *pdev) return dw_pcie_host_init(&pci->pp); } +#ifdef CONFIG_PM_SLEEP +static int ls_pcie_suspend_noirq(struct device *dev) +{ + struct ls_pcie *pcie = dev_get_drvdata(dev); + struct dw_pcie *pci = pcie->pci; + + if (!pcie->drvdata->pm_support) + return 0; + + return dw_pcie_suspend_noirq(pci); +} + +static int ls_pcie_resume_noirq(struct device *dev) +{ + + struct ls_pcie *pcie = dev_get_drvdata(dev); + struct dw_pcie *pci = pcie->pci; + + if (!pcie->drvdata->pm_support) + return 0; + + return dw_pcie_resume_noirq(pci); +} +#endif /* CONFIG_PM_SLEEP */ + +static const struct dev_pm_ops ls_pcie_pm_ops = { + SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(ls_pcie_suspend_noirq, + ls_pcie_resume_noirq) +}; + static struct platform_driver ls_pcie_driver = { .probe = ls_pcie_probe, .driver = { .name = "layerscape-pcie", .of_match_table = ls_pcie_of_match, .suppress_bind_attrs = true, + .pm = &ls_pcie_pm_ops, }, }; builtin_platform_driver(ls_pcie_driver);