From patchwork Fri Apr 21 12:02:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219900 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 650E8C7618E for ; Fri, 21 Apr 2023 12:03:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 92F7310E0A2; Fri, 21 Apr 2023 12:03:15 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id D10F410E0A2 for ; Fri, 21 Apr 2023 12:03:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078593; x=1713614593; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=hCrFFtCIFN1RSR6RhFdnYV47vH4yhu3fZSMmBkuXrp8=; b=ltODIoO94NvcaI1J0us3m0tgVfOon12g6Rd3+545mriOjv/PcxjY+oRv 847zItsy9YCSILGTTr89mEOBo+l1AlCf9xPbzdPhRmkQbe/XG6pWWeJzR UT/ZpUxxVcsXYugNyiNzzVa44kobTI7GtBWtQLyfDbg/LNojrKlT+d0bG q4A6rQhZUGpr/rF4u662zrleeRg3UvYL5Wh7RjPzNIvuRcSbgtykxEUOX w/NMR47qfYrB+7uHasG7k/MPILASuFYh3HuYW6lzcU9D64H98sFaZOgm2 Ih8Qpe6BLKhMO1dgftrVOxJlc4ypqjChMhkBEolIkAfAw+ViL3XsibCyB g==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900053" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900053" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725404" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725404" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:10 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:10 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:02:55 +0300 Message-Id: <20230421120307.24793-2-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 01/13] drm/i915: Re-init clock gating on coming out of PC8+ X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä PC8+ clobbers a bunch of displays registers which need to be restored by hand or else we lost a bunch of workarounds. The important ones for us are at least CHICKEN_PAR2* and CHICKEN_PIPESL*. Curiously at least some CHICKEN_PAR1* registers are preserved by the hardware/firmware. Unfortunately Bspec doens't really specify what gets clobbered vs. preserved so further reverse engieering might be warranted to figure out the specifics. Note that PCH_LP_PARTITION_LEVEL_DISABLE is also set by lpt_init_clock_gating() so the rmw in hsw_disable_pc8() is now redundant. Remove it. TODO: I suspect most gt stuff doesn't need this and we should finish moving all of them from init_clock_gating() to a more appropriate place... Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display_power.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c index 5150069f3f82..83c44ec3f5ea 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power.c +++ b/drivers/gpu/drm/i915/display/intel_display_power.c @@ -10,6 +10,7 @@ #include "i915_reg.h" #include "intel_backlight_regs.h" #include "intel_cdclk.h" +#include "intel_clock_gating.h" #include "intel_combo_phy.h" #include "intel_de.h" #include "intel_display_power.h" @@ -1366,9 +1367,8 @@ static void hsw_disable_pc8(struct drm_i915_private *dev_priv) hsw_restore_lcpll(dev_priv); intel_init_pch_refclk(dev_priv); - if (HAS_PCH_LPT_LP(dev_priv)) - intel_de_rmw(dev_priv, SOUTH_DSPCLK_GATE_D, - 0, PCH_LP_PARTITION_LEVEL_DISABLE); + /* Many display registers don't survive PC8+ */ + intel_clock_gating_init(dev_priv); } static void intel_pch_reset_handshake(struct drm_i915_private *dev_priv, From patchwork Fri Apr 21 12:02:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64CF5C77B75 for ; Fri, 21 Apr 2023 12:03:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4A7A488C3D; Fri, 21 Apr 2023 12:03:19 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id E984B10EDF6 for ; Fri, 21 Apr 2023 12:03:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078596; x=1713614596; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=B6h245Q9l+cbrCYMmfg/dvAvNVwQZNoaCA9aH/A2h4g=; b=nGCfP1KL/FpOLqLdteyOSj41gJ9s1OHQgUnHWME6a/4qZkjdFJ5WqF6n hdnv30jRDfsXwZyjDFCzmew7FFapfpaZVLpBWidZusM8XzGdbblO6vhZJ rnNidD84j+zdrIvJIO2hn2KeAU23N/9Gfi9omeb5NlfH5BJvnMdioPu0Y RwqzUD9eihnbse+5pdf2Vo7gV5k7gbQSbY4glv25GYj92mxnuLrR0tfZc fgf+9T/6Xo0BdVDa2SZmIp1CZcKfL1X0+XMaF+6KLJC6pJfINFtsdT+ol NkqWSkf0TcTaUIAnPypsJ2MIsEZeeMJK3a2N13Tz+Q9jI6YdZwfADJV2v g==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900063" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900063" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:16 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725412" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725412" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:14 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:13 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:02:56 +0300 Message-Id: <20230421120307.24793-3-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 02/13] drm/i915/psr: Fix BDW PSR AUX CH data register offsets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä The multiplication got replaced by an addition in some cleanup. This means we never write the correct data to some of the BDW PSR data registers and thus we fail to actually wake up the panel from PSR. Fixes: 4ab4fa103217 ("drm/i915/psr: Make PSR registers relative to transcoders") Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 0f7db617425a..8750cb0d8d9d 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -81,7 +81,7 @@ #define _SRD_AUX_DATA_A 0x60814 #define _SRD_AUX_DATA_EDP 0x6f814 -#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */ +#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ #define _SRD_STATUS_A 0x60840 #define _SRD_STATUS_EDP 0x6f840 From patchwork Fri Apr 21 12:02:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219902 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D71C1C7618E for ; Fri, 21 Apr 2023 12:03:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CF8A910EDF6; Fri, 21 Apr 2023 12:03:21 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 037A910EDF6 for ; Fri, 21 Apr 2023 12:03:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078599; x=1713614599; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=8AM8d4VjrB47uW9sBXS+hUJRFiafwBu6s7+Ff90NHRs=; b=i/+eHPAsij+/jahH7sY2Sg6KFkuwiX5jwLr2JdNNYzNgGVsjv7ZllXdr fdIDLBaPNk7MqAYCcQ0kH57cHN4NDw5h5+jOpW9ozfVV31NoD0hxCbsXl cRhz2Co/N4xTL+fPGiP2fdG3CImcE6r2RVhRR4tnNqUyPaPopf4K/1/o9 EBiswQIUMCIoFVu1hO/CPy08RjxwEU8nNADZuiU4C3dc8yH8jY4fLLVTZ 4VF4q9FaWViqVdwHRX03AHiRQCU1M97t4v0f6tkUQEnmdjf27Rwuq1fFK dEfYztECKMQi3cTM81GhiIL9ZOSb3elrkGkvRoPNl8jDxoto9vKTqmF3A g==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900076" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900076" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725425" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725425" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:17 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:17 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:02:57 +0300 Message-Id: <20230421120307.24793-4-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/13] drm/i915/psr: Wrap PSR1 register with functions X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä In preparation for re-introducing HSW's different PSR1 register offeets let's just wrap all the registers into functions. Avoids having to make the register macros more complex. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr.c | 99 ++++++++++++++++-------- 1 file changed, 65 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index ea0389c5f656..60518d5d0c4e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -234,23 +234,61 @@ static u32 psr_irq_mask_get(struct intel_dp *intel_dp) EDP_PSR_MASK(intel_dp->psr.transcoder); } +static i915_reg_t psr_ctl_reg(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) +{ + return EDP_PSR_CTL(cpu_transcoder); +} + +static i915_reg_t psr_debug_reg(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) +{ + return EDP_PSR_DEBUG(cpu_transcoder); +} + +static i915_reg_t psr_perf_cnt_reg(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) +{ + return EDP_PSR_PERF_CNT(cpu_transcoder); +} + +static i915_reg_t psr_status_reg(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) +{ + return EDP_PSR_STATUS(cpu_transcoder); +} + +static i915_reg_t psr_imr_reg(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) +{ + if (DISPLAY_VER(dev_priv) >= 12) + return TRANS_PSR_IMR(cpu_transcoder); + else + return EDP_PSR_IMR; +} + +static i915_reg_t psr_iir_reg(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) +{ + if (DISPLAY_VER(dev_priv) >= 12) + return TRANS_PSR_IIR(cpu_transcoder); + else + return EDP_PSR_IIR; +} + static void psr_irq_control(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); - i915_reg_t imr_reg; + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 mask; - if (DISPLAY_VER(dev_priv) >= 12) - imr_reg = TRANS_PSR_IMR(intel_dp->psr.transcoder); - else - imr_reg = EDP_PSR_IMR; - mask = psr_irq_psr_error_bit_get(intel_dp); if (intel_dp->psr.debug & I915_PSR_DEBUG_IRQ) mask |= psr_irq_post_exit_bit_get(intel_dp) | psr_irq_pre_entry_bit_get(intel_dp); - intel_de_rmw(dev_priv, imr_reg, psr_irq_mask_get(intel_dp), ~mask); + intel_de_rmw(dev_priv, psr_imr_reg(dev_priv, cpu_transcoder), + psr_irq_mask_get(intel_dp), ~mask); } static void psr_event_print(struct drm_i915_private *i915, @@ -296,12 +334,6 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; ktime_t time_ns = ktime_get(); - i915_reg_t imr_reg; - - if (DISPLAY_VER(dev_priv) >= 12) - imr_reg = TRANS_PSR_IMR(cpu_transcoder); - else - imr_reg = EDP_PSR_IMR; if (psr_iir & psr_irq_pre_entry_bit_get(intel_dp)) { intel_dp->psr.last_entry_attempt = time_ns; @@ -339,7 +371,8 @@ void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir) * again so we don't care about unmask the interruption * or unset irq_aux_error. */ - intel_de_rmw(dev_priv, imr_reg, 0, psr_irq_psr_error_bit_get(intel_dp)); + intel_de_rmw(dev_priv, psr_imr_reg(dev_priv, cpu_transcoder), + 0, psr_irq_psr_error_bit_get(intel_dp)); schedule_work(&intel_dp->psr.work); } @@ -577,7 +610,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp) if (DISPLAY_VER(dev_priv) >= 8) val |= EDP_PSR_CRC_ENABLE; - intel_de_rmw(dev_priv, EDP_PSR_CTL(cpu_transcoder), + intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), ~EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK, val); } @@ -685,7 +718,7 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) * PSR2 HW is incorrectly using EDP_PSR_TP1_TP3_SEL and BSpec is * recommending keep this bit unset while PSR2 is enabled. */ - intel_de_write(dev_priv, EDP_PSR_CTL(cpu_transcoder), 0); + intel_de_write(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), 0); intel_de_write(dev_priv, EDP_PSR2_CTL(cpu_transcoder), val); } @@ -1201,13 +1234,15 @@ static void intel_psr_activate(struct intel_dp *intel_dp) struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - if (transcoder_has_psr2(dev_priv, cpu_transcoder)) - drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)) & EDP_PSR2_ENABLE); + drm_WARN_ON(&dev_priv->drm, + transcoder_has_psr2(dev_priv, cpu_transcoder) && + intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)) & EDP_PSR2_ENABLE); drm_WARN_ON(&dev_priv->drm, - intel_de_read(dev_priv, EDP_PSR_CTL(cpu_transcoder)) & EDP_PSR_ENABLE); + intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)) & EDP_PSR_ENABLE); + drm_WARN_ON(&dev_priv->drm, intel_dp->psr.active); + lockdep_assert_held(&intel_dp->psr.lock); /* psr1 and psr2 are mutually exclusive.*/ @@ -1285,8 +1320,7 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (DISPLAY_VER(dev_priv) < 11) mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; - intel_de_write(dev_priv, EDP_PSR_DEBUG(cpu_transcoder), - mask); + intel_de_write(dev_priv, psr_debug_reg(dev_priv, cpu_transcoder), mask); psr_irq_control(intel_dp); @@ -1352,10 +1386,7 @@ static bool psr_interrupt_error_check(struct intel_dp *intel_dp) * first time that PSR HW tries to activate so lets keep PSR disabled * to avoid any rendering problems. */ - if (DISPLAY_VER(dev_priv) >= 12) - val = intel_de_read(dev_priv, TRANS_PSR_IIR(cpu_transcoder)); - else - val = intel_de_read(dev_priv, EDP_PSR_IIR); + val = intel_de_read(dev_priv, psr_iir_reg(dev_priv, cpu_transcoder)); val &= psr_irq_psr_error_bit_get(intel_dp); if (val) { intel_dp->psr.sink_not_reliable = true; @@ -1418,7 +1449,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp) drm_WARN_ON(&dev_priv->drm, val & EDP_PSR2_ENABLE); } - val = intel_de_read(dev_priv, EDP_PSR_CTL(cpu_transcoder)); + val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)); drm_WARN_ON(&dev_priv->drm, val & EDP_PSR_ENABLE); return; @@ -1432,7 +1463,7 @@ static void intel_psr_exit(struct intel_dp *intel_dp) drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR2_ENABLE)); } else { - val = intel_de_rmw(dev_priv, EDP_PSR_CTL(cpu_transcoder), + val = intel_de_rmw(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder), EDP_PSR_ENABLE, 0); drm_WARN_ON(&dev_priv->drm, !(val & EDP_PSR_ENABLE)); @@ -1451,7 +1482,7 @@ static void intel_psr_wait_exit_locked(struct intel_dp *intel_dp) psr_status = EDP_PSR2_STATUS(cpu_transcoder); psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; } else { - psr_status = EDP_PSR_STATUS(cpu_transcoder); + psr_status = psr_status_reg(dev_priv, cpu_transcoder); psr_status_mask = EDP_PSR_STATUS_STATE_MASK; } @@ -2151,7 +2182,7 @@ static int _psr1_ready_for_pipe_update_locked(struct intel_dp *intel_dp) * defensive enough to cover everything. */ return intel_de_wait_for_clear(dev_priv, - EDP_PSR_STATUS(cpu_transcoder), + psr_status_reg(dev_priv, cpu_transcoder), EDP_PSR_STATUS_STATE_MASK, 50); } @@ -2205,7 +2236,7 @@ static bool __psr_wait_for_idle_locked(struct intel_dp *intel_dp) reg = EDP_PSR2_STATUS(cpu_transcoder); mask = EDP_PSR2_STATUS_STATE_MASK; } else { - reg = EDP_PSR_STATUS(cpu_transcoder); + reg = psr_status_reg(dev_priv, cpu_transcoder); mask = EDP_PSR_STATUS_STATE_MASK; } @@ -2823,7 +2854,7 @@ psr_source_status(struct intel_dp *intel_dp, struct seq_file *m) "SRDOFFACK", "SRDENT_ON", }; - val = intel_de_read(dev_priv, EDP_PSR_STATUS(cpu_transcoder)); + val = intel_de_read(dev_priv, psr_status_reg(dev_priv, cpu_transcoder)); status_val = REG_FIELD_GET(EDP_PSR_STATUS_STATE_MASK, val); if (status_val < ARRAY_SIZE(live_status)) status = live_status[status_val]; @@ -2870,7 +2901,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) val = intel_de_read(dev_priv, EDP_PSR2_CTL(cpu_transcoder)); enabled = val & EDP_PSR2_ENABLE; } else { - val = intel_de_read(dev_priv, EDP_PSR_CTL(cpu_transcoder)); + val = intel_de_read(dev_priv, psr_ctl_reg(dev_priv, cpu_transcoder)); enabled = val & EDP_PSR_ENABLE; } seq_printf(m, "Source PSR ctl: %s [0x%08x]\n", @@ -2882,7 +2913,7 @@ static int intel_psr_status(struct seq_file *m, struct intel_dp *intel_dp) /* * SKL+ Perf counter is reset to 0 everytime DC state is entered */ - val = intel_de_read(dev_priv, EDP_PSR_PERF_CNT(cpu_transcoder)); + val = intel_de_read(dev_priv, psr_perf_cnt_reg(dev_priv, cpu_transcoder)); seq_printf(m, "Performance counter: %u\n", REG_FIELD_GET(EDP_PSR_PERF_CNT_MASK, val)); From patchwork Fri Apr 21 12:02:58 2023 Content-Type: text/plain; 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21 Apr 2023 05:03:20 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:20 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:02:58 +0300 Message-Id: <20230421120307.24793-5-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 04/13] drm/i915/psr: Reintroduce HSW PSR1 registers X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add back hsw'w special SRD/PSR1 registers. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr.c | 20 +++++++++++++++---- drivers/gpu/drm/i915/display/intel_psr_regs.h | 4 ++++ 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 60518d5d0c4e..7f748c7a71f3 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -237,25 +237,37 @@ static u32 psr_irq_mask_get(struct intel_dp *intel_dp) static i915_reg_t psr_ctl_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { - return EDP_PSR_CTL(cpu_transcoder); + if (DISPLAY_VER(dev_priv) >= 8) + return EDP_PSR_CTL(cpu_transcoder); + else + return HSW_SRD_CTL; } static i915_reg_t psr_debug_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { - return EDP_PSR_DEBUG(cpu_transcoder); + if (DISPLAY_VER(dev_priv) >= 8) + return EDP_PSR_DEBUG(cpu_transcoder); + else + return HSW_SRD_DEBUG; } static i915_reg_t psr_perf_cnt_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { - return EDP_PSR_PERF_CNT(cpu_transcoder); + if (DISPLAY_VER(dev_priv) >= 8) + return EDP_PSR_PERF_CNT(cpu_transcoder); + else + return HSW_SRD_PERF_CNT; } static i915_reg_t psr_status_reg(struct drm_i915_private *dev_priv, enum transcoder cpu_transcoder) { - return EDP_PSR_STATUS(cpu_transcoder); + if (DISPLAY_VER(dev_priv) >= 8) + return EDP_PSR_STATUS(cpu_transcoder); + else + return HSW_SRD_STATUS; } static i915_reg_t psr_imr_reg(struct drm_i915_private *dev_priv, diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 8750cb0d8d9d..998f638ee182 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -19,6 +19,7 @@ * HSW PSR registers are relative to DDIA(_DDI_BUF_CTL_A + 0x800) with just one * instance of it */ +#define HSW_SRD_CTL _MMIO(0x64800) #define _SRD_CTL_A 0x60800 #define _SRD_CTL_EDP 0x6f800 #define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) @@ -83,6 +84,7 @@ #define _SRD_AUX_DATA_EDP 0x6f814 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ +#define HSW_SRD_STATUS _MMIO(0x64840) #define _SRD_STATUS_A 0x60840 #define _SRD_STATUS_EDP 0x6f840 #define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) @@ -107,12 +109,14 @@ #define EDP_PSR_STATUS_SENDING_TP1 REG_BIT(4) #define EDP_PSR_STATUS_IDLE_MASK REG_GENMASK(3, 0) +#define HSW_SRD_PERF_CNT _MMIO(0x64844) #define _SRD_PERF_CNT_A 0x60844 #define _SRD_PERF_CNT_EDP 0x6f844 #define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) #define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0) /* PSR_MASK on SKL+ */ +#define HSW_SRD_DEBUG _MMIO(0x64860) #define _SRD_DEBUG_A 0x60860 #define _SRD_DEBUG_EDP 0x6f860 #define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) From patchwork Fri Apr 21 12:02:59 2023 Content-Type: text/plain; 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21 Apr 2023 05:03:23 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:23 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:02:59 +0300 Message-Id: <20230421120307.24793-6-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/13] drm/i915/psr: Bring back HSW/BDW PSR AUX CH registers/setup X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Reintroduce the special PSR AUX CH setup for hsw/bdw. Not all of it was even removed (BDW AUX data registers were left behind). Update the code to use REG_BIT() & co. while at it. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp_aux.c | 2 +- drivers/gpu/drm/i915/display/intel_dp_aux.h | 4 ++ drivers/gpu/drm/i915/display/intel_psr.c | 61 +++++++++++++++++++ drivers/gpu/drm/i915/display/intel_psr_regs.h | 11 ++++ 4 files changed, 77 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.c b/drivers/gpu/drm/i915/display/intel_dp_aux.c index abf77ba76972..847fd6bfa7e4 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.c +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.c @@ -14,7 +14,7 @@ #include "intel_pps.h" #include "intel_tc.h" -static u32 intel_dp_aux_pack(const u8 *src, int src_bytes) +u32 intel_dp_aux_pack(const u8 *src, int src_bytes) { int i; u32 v = 0; diff --git a/drivers/gpu/drm/i915/display/intel_dp_aux.h b/drivers/gpu/drm/i915/display/intel_dp_aux.h index 138e340f94ee..3bc529a23dd6 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_aux.h +++ b/drivers/gpu/drm/i915/display/intel_dp_aux.h @@ -6,6 +6,8 @@ #ifndef __INTEL_DP_AUX_H__ #define __INTEL_DP_AUX_H__ +#include + enum aux_ch; struct intel_dp; struct intel_encoder; @@ -15,4 +17,6 @@ void intel_dp_aux_init(struct intel_dp *intel_dp); enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder); +u32 intel_dp_aux_pack(const u8 *src, int src_bytes); + #endif /* __INTEL_DP_AUX_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 7f748c7a71f3..2ff6f75c2bee 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -288,6 +288,24 @@ static i915_reg_t psr_iir_reg(struct drm_i915_private *dev_priv, return EDP_PSR_IIR; } +static i915_reg_t psr_aux_ctl_reg(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder) +{ + if (DISPLAY_VER(dev_priv) >= 8) + return EDP_PSR_AUX_CTL(cpu_transcoder); + else + return HSW_SRD_AUX_CTL; +} + +static i915_reg_t psr_aux_data_reg(struct drm_i915_private *dev_priv, + enum transcoder cpu_transcoder, int i) +{ + if (DISPLAY_VER(dev_priv) >= 8) + return EDP_PSR_AUX_DATA(cpu_transcoder, i); + else + return HSW_SRD_AUX_DATA(i); +} + static void psr_irq_control(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -512,6 +530,42 @@ void intel_psr_init_dpcd(struct intel_dp *intel_dp) } } +static void hsw_psr_setup_aux(struct intel_dp *intel_dp) +{ + struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); + enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + u32 aux_clock_divider, aux_ctl; + static const u8 aux_msg[] = { + [0] = (DP_AUX_NATIVE_WRITE << 4) | ((DP_SET_POWER >> 16) & 0xf), + [1] = (DP_SET_POWER >> 8) & 0xff, + [2] = DP_SET_POWER & 0xff, + [3] = 1 - 1, + [4] = DP_SET_POWER_D0, + }; + int i; + + BUILD_BUG_ON(sizeof(aux_msg) > 20); + for (i = 0; i < sizeof(aux_msg); i += 4) + intel_de_write(dev_priv, + psr_aux_data_reg(dev_priv, cpu_transcoder, i >> 2), + intel_dp_aux_pack(&aux_msg[i], sizeof(aux_msg) - i)); + + aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0); + + /* Start with bits set for DDI_AUX_CTL register */ + aux_ctl = intel_dp->get_aux_send_ctl(intel_dp, sizeof(aux_msg), + aux_clock_divider); + + /* Select only valid bits for SRD_AUX_CTL */ + aux_ctl &= EDP_PSR_AUX_CTL_TIME_OUT_MASK | + EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK | + EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK | + EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK; + + intel_de_write(dev_priv, psr_aux_ctl_reg(dev_priv, cpu_transcoder), + aux_ctl); +} + static void intel_psr_enable_sink(struct intel_dp *intel_dp) { struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); @@ -1318,6 +1372,13 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, enum transcoder cpu_transcoder = intel_dp->psr.transcoder; u32 mask; + /* + * Only HSW and BDW have PSR AUX registers that need to be setup. + * SKL+ use hardcoded values PSR AUX transactions + */ + if (DISPLAY_VER(dev_priv) < 9) + hsw_psr_setup_aux(intel_dp); + /* * Per Spec: Avoid continuous PSR exit by masking MEMUP and HPD also * mask LPSP to avoid dependency on other drivers that might block diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index 998f638ee182..5e54817b6a0f 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -80,6 +80,17 @@ #define EDP_PSR_PRE_ENTRY(trans) (TGL_PSR_PRE_ENTRY << \ _EDP_PSR_TRANS_SHIFT(trans)) +#define HSW_SRD_AUX_CTL _MMIO(0x64810) +#define _SRD_AUX_CTL_A 0x60810 +#define _SRD_AUX_CTL_EDP 0x6f810 +#define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(tran, _SRD_AUX_CTL_A) +#define EDP_PSR_AUX_CTL_TIME_OUT_MASK REG_GENMASK(27, 26) +#define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK REG_GENMASK(24, 20) +#define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK REG_GENMASK(19, 16) +#define EDP_PSR_AUX_CTL_ERROR_INTERRUPT REG_BIT(11) +#define EDP_PSR_AUX_CTL_BIT_CLOCK_2X_MASK REG_GENMASK(10, 0) + +#define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */ #define _SRD_AUX_DATA_A 0x60814 #define _SRD_AUX_DATA_EDP 0x6f814 #define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ From patchwork Fri Apr 21 12:03:00 2023 Content-Type: text/plain; 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21 Apr 2023 05:03:26 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:26 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:03:00 +0300 Message-Id: <20230421120307.24793-7-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/13] drm/i915/psr: HSW/BDW have no PSR2 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Deal with HSW/BDW in transcoder_has_psr2(). Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 2ff6f75c2bee..f5089565e800 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -796,8 +796,10 @@ transcoder_has_psr2(struct drm_i915_private *dev_priv, enum transcoder cpu_trans return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; else if (DISPLAY_VER(dev_priv) >= 12) return cpu_transcoder == TRANSCODER_A; - else + else if (DISPLAY_VER(dev_priv) >= 9) return cpu_transcoder == TRANSCODER_EDP; + else + return false; } static u32 intel_get_frame_time_us(const struct intel_crtc_state *cstate) From patchwork Fri Apr 21 12:03:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219906 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4550BC77B75 for ; Fri, 21 Apr 2023 12:03:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A536810EE11; Fri, 21 Apr 2023 12:03:34 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2551510EE0E for ; Fri, 21 Apr 2023 12:03:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078612; x=1713614612; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=f1bt7UAh1SjmLvSQcDXFj4MJVl4KBjzGlz+bVwnbLnc=; b=l77pHtDVEN8QrX2zL2Pi2oW7JRD9q3moVsSC4XqqiOEerl52Khava60C Bf0QhkZV2HekJPjsqtxrv2xpX/Agh8WXpaPmU+co5BP08rbz6EsgULwLj 7s6qDECNk8gVHe/nEJfGGHEO5bWt2Qm5NdGgW+WStd94Wz4Tp97WL5GqF kGLSCkZQEkR79js7yUNGKZ4bKE/Y1r3aK9aUlejcZc8R0MlFdeLPlsptT W0X0datipp7PMxQrXps/wCCvPcAQZkDdF/QBuVcPrKyClUL8oaahgtdmz CGIolcREcteAAexmWXaV9FomzsUTKv/e793QPR75Av1mGv1sQwliRGS8q Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900112" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900112" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:31 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725450" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725450" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:29 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:29 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:03:01 +0300 Message-Id: <20230421120307.24793-8-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 07/13] drm/i915/psr: Restore PSR interrupt handler for HSW X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Add the PSR interrupt handling code back for HSW. Looks like the removal was never completed anyway since the irq setup code was lest untouched. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_irq.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 2b94b8ca8ec9..e1c57ba4f80a 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1781,6 +1781,20 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv, if (de_iir & DE_ERR_INT_IVB) ivb_err_int_handler(dev_priv); + if (de_iir & DE_EDP_PSR_INT_HSW) { + struct intel_encoder *encoder; + + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + u32 psr_iir; + + psr_iir = intel_uncore_rmw(&dev_priv->uncore, + EDP_PSR_IIR, 0, 0); + intel_psr_irq_handler(intel_dp, psr_iir); + break; + } + } + if (de_iir & DE_AUX_CHANNEL_A_IVB) dp_aux_irq_handler(dev_priv); From patchwork Fri Apr 21 12:03:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219907 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 545AFC77B75 for ; Fri, 21 Apr 2023 12:03:39 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BFA7710EE0E; Fri, 21 Apr 2023 12:03:38 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4258310EE12 for ; Fri, 21 Apr 2023 12:03:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078615; x=1713614615; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=zvjgWKuHmb3hjGm/JMwak6h1wEod1toDoU29bqGUl6A=; b=AlEI5tp2dMOARUISiXbxL+uP81ci0dCftvFbZEGg6LtRpRIAlR4ThvOi /x1mwkoc/jqz7FAjZkEUbeJo/Zna16diVQVsIFJGYYtNlZC1PV6ODSW0W XZA00Zs9Yq+trad2l/aHyERjSt0f+EPkYYLf7aICV31YdSmQw+JaA9DxT sTMvVhDQdhuANl3H4+d7MqMouKdbzXMl+4KA7T+yOgqLNlCy8YQZ65tH+ KI+huJuZd4N7BMJtslpveTUKTGKOBWnbTWtFloVubw65uMxTBrtHUYcW4 nmTxy+AkmZTLz+iDatwnkHmReFFUcqsR2UNLvUd1Z+/A9HCR9Hc+Rka6X A==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900123" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900123" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:35 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725456" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725456" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:32 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:32 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:03:02 +0300 Message-Id: <20230421120307.24793-9-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 08/13] drm/i915/psr: Implement WaPsrDPAMaskVBlankInSRD:hsw X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Implement WaPsrDPAMaskVBlankInSRD:hsw, which makes the hardware generate the extra vblank between link training and first frame being transmitted. This is the same thing that's controlled by TRANS_CHICKEN[21] on skl+ (but due to the funky double buffering it's effectively always at the rest value after DC5 exit). So for consistent behaviour we want every platform to generate said vblank. BDW is already setting this up correctly. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_clock_gating.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index a27600bc5976..9682323510cd 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -562,6 +562,9 @@ static void hsw_init_clock_gating(struct drm_i915_private *i915) /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); + /* WaPsrDPAMaskVBlankInSRD:hsw */ + intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); + /* This is required by WaCatErrorRejectionIssue:hsw */ intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); From patchwork Fri Apr 21 12:03:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219908 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6C7F2C77B75 for ; Fri, 21 Apr 2023 12:03:43 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E4B1910EE0C; Fri, 21 Apr 2023 12:03:42 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4693410EE0E for ; Fri, 21 Apr 2023 12:03:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078618; x=1713614618; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=TMoHOl3M1kp5lZzgvVhEgWzDwdgCpCuRx2DPLWW9fBw=; b=OgoKhqLB8KQU5pMAxAadefRa66qs5+xZ4CLNMnnheDPZMw4jfQv7druC X0E1b87yDKXag1t6wWqxaZua9ABcPTK1H+hcDgWMkECNa08z+ZxU5ZmyD kEf6K3OgExYNihcjAy1y30KueOa8XnoXPT/elkxp+pTvGvNgJ93scI7LM 39jvzEGV/foSOU6IWP51mRPkCvFFRypKAMNsDJfqRUwGJR2airfFhived tJPkhlVDKrR9+8ZgBLy73eIJX6KSDeAKmKRSsfUupMlGSsnBWT3bYRVvA Ngq5jBVoILzXu7xahQ0dnXeKRjXydFYnTlqaSQOdjrTbjvqwz4IieDJWI Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900135" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900135" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:37 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725463" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725463" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:35 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:35 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:03:03 +0300 Message-Id: <20230421120307.24793-10-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 09/13] drm/i915/psr: Implement WaPsrDPRSUnmaskVBlankInSRD:hsw X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Bspec asks us to unmask "vblank to registers" in the DPRS unit. Note that I was unable to observe any change in hardware behviour due to this bit on HSW. But let's do this anyway in case it matters in some cases, and the correspoding bit on BDW is abolutely critical as without it the hardware won't generate any vblanks whatsoever after PSR exit. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_clock_gating.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 9682323510cd..d9600cd1ab06 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -559,12 +559,20 @@ static void bdw_init_clock_gating(struct drm_i915_private *i915) static void hsw_init_clock_gating(struct drm_i915_private *i915) { + enum pipe pipe; + /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(PIPE_A), 0, HSW_FBCQ_DIS); /* WaPsrDPAMaskVBlankInSRD:hsw */ intel_uncore_rmw(&i915->uncore, CHICKEN_PAR1_1, 0, HSW_MASK_VBL_TO_PIPE_IN_SRD); + for_each_pipe(i915, pipe) { + /* WaPsrDPRSUnmaskVBlankInSRD:hsw */ + intel_uncore_rmw(&i915->uncore, CHICKEN_PIPESL_1(pipe), + 0, HSW_UNMASK_VBL_TO_REGS_IN_SRD); + } + /* This is required by WaCatErrorRejectionIssue:hsw */ intel_uncore_rmw(&i915->uncore, GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, 0, GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); From patchwork Fri Apr 21 12:03:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219909 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0A8DAC7618E for ; Fri, 21 Apr 2023 12:03:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 63DF910EE12; Fri, 21 Apr 2023 12:03:44 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 6598810EE0C for ; Fri, 21 Apr 2023 12:03:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078621; x=1713614621; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=xtKg76LqwgwtAmlGv0Ypkp8ORUQ6s9AK8W2RzI6YGHE=; b=cQqmKusURvdK8x/TCiYOBq4dlEtIUXBZQfcPUHy31Hk7jSrL1FKuwtdV 1HjJxakPbPfZAD6Ouje6uGC0ff36lSPTpJ4EdW+nlAlY2pIDPgNnAQWRC tEes789EZc/dVsjW9qgvndsAg61sTg+c9Lx8eLrLDJH/BbWbyMBqqY91a CV5K84W9XYvsu0H79lYYBnhX9VnKG8CkRiabTjTHDEAPTkgWTjiQroWJm nT8vUO3lBa5zjKhJCB7zWF9auQefaic613SaiClnxzWsfd6mBUFHV+hK1 kOCHa9jB16c40yfHpGhUiCxtIDLN7ayxBCyQXWeQvLwc2qmgKvyPkRJqu g==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900143" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900143" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725465" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725465" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:38 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:38 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:03:04 +0300 Message-Id: <20230421120307.24793-11-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/13] drm/i915/psr: Do no mask display register writes on hsw/bdw X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä hsw/bdw lack the pipe register vs. display register distinction in their PSR masking capabilities. So to keep our CURSURFLIVE tricks working we need to just unmask all display register writes on these platforms. The downside being that any display regitster (eg. even SWF regs) will cause a PSR exit. Note that WaMaskMMIOWriteForPSR asks us to mask this on bdw, but that won't work since we need those CURSURFLIVE tricks. Observations on actual hardware show that this causes one extra PSR exit ~every 10 seconds, which is pretty much irrelevant. I suspect this is due to the pcode poking at IPS_CTL. Disabling IPS does not stop it however, so either I'm wrong or pcode pokes at the register regardless of whether it's actually trying to enable/disable IPS. Also when the machine is busy (eg. just running 'find /') these extra PSR exits cease, which again points at pcode or some other PM entity as being the culprit. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index f5089565e800..d871a7d3357a 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1392,7 +1392,11 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, EDP_PSR_DEBUG_MASK_LPSP | EDP_PSR_DEBUG_MASK_MAX_SLEEP; - if (DISPLAY_VER(dev_priv) < 11) + /* + * No separate pipe reg write mask on hsw/bdw, so have to unmask all + * registers in order to keep the CURSURFLIVE tricks working :( + */ + if (IS_DISPLAY_VER(dev_priv, 9, 10)) mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; intel_de_write(dev_priv, psr_debug_reg(dev_priv, cpu_transcoder), mask); From patchwork Fri Apr 21 12:03:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219910 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E3007C77B75 for ; Fri, 21 Apr 2023 12:03:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 72CA810EE16; Fri, 21 Apr 2023 12:03:48 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7AFBA10EE16 for ; Fri, 21 Apr 2023 12:03:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078624; x=1713614624; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=Cn9ZNEibVw7/CDJecYGfuDhZk8kGqs9yIsbMHlCeh7c=; b=N0GewvDn+I3cE8wrgscUWNKTUpzIuHbHmu/d+JV//9SLjhWIIQaCCQOi UgP/JR5JogP5QSrlNFf/Mjwwc1j3Fmida6RtDAUOHSq0TBmpystbJhixs oKOOoh/uTAy16pSs2IkNhyvCo/mZKAH1MzwomLfkKuJN7LVWaBX4I9jEv s1iFo10r2YW5E/KpAp9IuQC6ZZyY084PNYdULly5xq64rhxaCym0teSot nslCsdDOoLs/K19HUYOMBXjtGLqhZ4N5PjIzLDoeq/1Fz0kijlhRl2BeO 14/10MELxo9oEebHUxME9a+M/KWIU3ajGVF47P/5qvNWqg5W+2Kbnu4Wa Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900153" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900153" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:44 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725469" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725469" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:42 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:41 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:03:05 +0300 Message-Id: <20230421120307.24793-12-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/13] drm/i915/psr: Don't skip both TP1 and TP2/3 on hsw/bdw X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä WA 0479 says: "Do not skip both TP1 and TP2/TP3". Let's just stick the minimum 100us TP2/3 time in there to avoid that. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_psr.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index d871a7d3357a..072a431ec257 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -627,6 +627,15 @@ static u32 intel_psr1_get_tp_time(struct intel_dp *intel_dp) else val |= EDP_PSR_TP2_TP3_TIME_2500us; + /* + * WA 0479: hsw,bdw + * "Do not skip both TP1 and TP2/TP3" + */ + if (DISPLAY_VER(dev_priv) < 9 && + connector->panel.vbt.psr.tp1_wakeup_time_us == 0 && + connector->panel.vbt.psr.tp2_tp3_wakeup_time_us == 0) + val |= EDP_PSR_TP2_TP3_TIME_100us; + check_tp3_sel: if (intel_dp_source_supports_tps3(dev_priv) && drm_dp_tps3_supported(intel_dp->dpcd)) From patchwork Fri Apr 21 12:03:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219911 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BADDC77B75 for ; Fri, 21 Apr 2023 12:03:52 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CDA7610EE17; Fri, 21 Apr 2023 12:03:51 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3957210EE16 for ; Fri, 21 Apr 2023 12:03:47 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078627; x=1713614627; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=bM9baCrNNl4d6Ck0vR4GBUNkq1Uz2jby67LPDaHKLHY=; b=e6HZ1/FhFxo4STFkyjW3f5tHrrBB+7VPFqUjAHkjZqFS+YhavjOMEKQQ SGU/KfiuNQ5KbG+8Kj2RheCrdqUnwuI0a62uToEVhOmKASBNM6kw2abwV hrNOtSoJLwMJiNIVgeFhwF0n8D+PGVCmevN5hIuFrTke5uf6ugc/ZGv29 kKcuenRsafxyAd+0d5aS4Bs4YRcHow6lAQstdAL5HQlwK1Izi3LTthgnE Ex2kD42M/JfL5X/Sojk8VGasNsYBagLOXfACUu+5fOtcg6XDe7D7qOm+O +p1PdDp6s2Q6CAJto2zb9lUl1zGZpgas/ecbe/Xauqy8SJgac8LEgtPcw w==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900160" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900160" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:46 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725475" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725475" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:45 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:44 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:03:06 +0300 Message-Id: <20230421120307.24793-13-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 12/13] drm/i915/psr: Allow PSR with sprite enabled on hsw/bdw X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä Can't see why we'd want the sprite blocking PSR entry. Mask it out. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_display.c | 4 ++++ drivers/gpu/drm/i915/display/intel_psr.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index bf391a6cd8d6..0ff50f995bf4 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -3133,6 +3133,10 @@ static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state) if (DISPLAY_VER(dev_priv) >= 12) val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC; + /* allow PSR with sprite enabled */ + if (IS_BROADWELL(dev_priv)) + val |= PIPE_MISC_PSR_MASK_SPRITE_ENABLE; + intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val); } diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 072a431ec257..0dd321f48c81 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -1408,6 +1408,10 @@ static void intel_psr_enable_source(struct intel_dp *intel_dp, if (IS_DISPLAY_VER(dev_priv, 9, 10)) mask |= EDP_PSR_DEBUG_MASK_DISP_REG_WRITE; + /* allow PSR with sprite enabled */ + if (IS_HASWELL(dev_priv)) + mask |= EDP_PSR_DEBUG_MASK_SPRITE_ENABLE; + intel_de_write(dev_priv, psr_debug_reg(dev_priv, cpu_transcoder), mask); psr_irq_control(intel_dp); From patchwork Fri Apr 21 12:03:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?VmlsbGUgU3lyasOkbMOk?= X-Patchwork-Id: 13219912 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6BDFDC77B75 for ; Fri, 21 Apr 2023 12:03:55 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7D2D10EE19; Fri, 21 Apr 2023 12:03:54 +0000 (UTC) Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2937A10EE17 for ; Fri, 21 Apr 2023 12:03:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1682078630; x=1713614630; h=from:to:subject:date:message-id:in-reply-to:references: mime-version:content-transfer-encoding; bh=FaiYJdvcVUY14aoY2erSgI9ucHLqhtA+fWeAbvIOy04=; b=L4OMxj/dzzjOudAYAVK3q52+JLFOgc9ZnHGkI4IiTq/tDPYwXnhAq8od cCm3d/NuGX2HUJhaJ+Gw2j68LJovCwI+Nesx2FD9rumVyo73CDBiu9hC0 ciWvam6BzXGjJ5hWGMkvYNk3hJ0jHUgKVmKcI6ItFSxYBk2PLZObDr2CI nRVvmU2Ns6dRVXtRdNV0qK6yR0VDRNSX/L71l3yRi7vEz2L3H/ZxswewS VxsqrcDeXPqVkCrn9oxlXLTm+QKZzrrda4jV3kSdkcTmRbZMLo2j5LBul gWvbQhV9O7jpxEHUJZkMxkIIzsLfhqXz9MLju8uYBeEI4dqwqZ4tWbioR g==; X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="373900168" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="373900168" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Apr 2023 05:03:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10686"; a="722725476" X-IronPort-AV: E=Sophos;i="5.99,214,1677571200"; d="scan'208";a="722725476" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.70]) by orsmga008.jf.intel.com with SMTP; 21 Apr 2023 05:03:48 -0700 Received: by stinkbox (sSMTP sendmail emulation); Fri, 21 Apr 2023 15:03:47 +0300 From: Ville Syrjala To: intel-gfx@lists.freedesktop.org Date: Fri, 21 Apr 2023 15:03:07 +0300 Message-Id: <20230421120307.24793-14-ville.syrjala@linux.intel.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230421120307.24793-1-ville.syrjala@linux.intel.com> References: <20230421120307.24793-1-ville.syrjala@linux.intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 13/13] drm/i915/psr: Re-enable PSR1 on hdw/bdw X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" From: Ville Syrjälä All known issues fixed now, so re-enable PSR1 on hsw/bdw. Signed-off-by: Ville Syrjälä --- drivers/gpu/drm/i915/i915_pci.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 272a8ba37b64..923e24044967 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -562,6 +562,8 @@ static const struct intel_device_info vlv_info = { BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \ .display.has_ddi = 1, \ .display.has_fpga_dbg = 1, \ + .display.has_psr = 1, \ + .display.has_psr_hw_tracking = 1, \ .display.has_dp_mst = 1, \ .has_rc6p = 0 /* RC6p removed-by HSW */, \ HSW_PIPE_OFFSETS, \ @@ -665,8 +667,6 @@ static const struct intel_device_info chv_info = { .has_gt_uc = 1, \ .__runtime.has_hdcp = 1, \ .display.has_ipc = 1, \ - .display.has_psr = 1, \ - .display.has_psr_hw_tracking = 1, \ .display.dbuf.size = 896 - 4, /* 4 blocks for bypass path allocation */ \ .display.dbuf.slice_mask = BIT(DBUF_S1)