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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:36 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 01/13] hw/ide/pci: Expose legacy interrupts as GPIOs Date: Sat, 22 Apr 2023 17:07:16 +0200 Message-Id: <20230422150728.176512-2-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Exposing the legacy IDE interrupts as GPIOs allows them to be connected in the parent device through qdev_connect_gpio_out(), i.e. without accessing private data of TYPE_PCI_IDE. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- hw/ide/pci.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/ide/pci.c b/hw/ide/pci.c index fc9224bbc9..942e216b9b 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -522,10 +522,18 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d) bm->pci_dev = d; } +static void pci_ide_init(Object *obj) +{ + PCIIDEState *d = PCI_IDE(obj); + + qdev_init_gpio_out(DEVICE(d), d->isa_irq, ARRAY_SIZE(d->isa_irq)); +} + static const TypeInfo pci_ide_type_info = { .name = TYPE_PCI_IDE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCIIDEState), + .instance_init = pci_ide_init, .abstract = true, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, From patchwork Sat Apr 22 15:07:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221034 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0D41CC7618E for ; Sat, 22 Apr 2023 15:10:24 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqEq1-0001rO-Uq; Sat, 22 Apr 2023 11:07:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqEpz-0001nf-Mi; Sat, 22 Apr 2023 11:07:43 -0400 Received: from mail-ej1-x62d.google.com ([2a00:1450:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqEpw-000596-KI; Sat, 22 Apr 2023 11:07:42 -0400 Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-94a34d3812cso480632566b.2; Sat, 22 Apr 2023 08:07:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682176058; x=1684768058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+EWP4yPmLtvO9JWiKUeH2VsYNoRmYM/ETrmN3+B7dEc=; b=Uiq7ApnD0hq+bd49pePFUZxZa1lvJoIMjzszv5MPjMUKqmYfIlKrLK+tLKZadYpTIl svTifgiyY8R7jfPSbwbyhxPtefdKaxn6OOCf+Bky11WMboOMB1TQoBXQcdnV01MsmNNT /k0wjaUa16Pag61vNoq/SNTreZJyB0vJ+QdazjVXUh3phPObH8j3Sl4m3Gbsh45Lsj7O zx8GM9O7aIykvkavevEzhQYlX1IMZnkQ5KoO/X/9eIJ9A51HggRBlUqZMxjiWQJUSnDp Ilk/WBnVDJiAzdEzU5DcDb7AvHnixpq31F0YlEhoD8TCG7wFDI2VwwPQp11Zx5xdbiYv FgNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682176058; x=1684768058; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+EWP4yPmLtvO9JWiKUeH2VsYNoRmYM/ETrmN3+B7dEc=; b=YJBE1wmofKXrbCRxYxqNNMypxddwFoSa8AUxP3T74V90JYH7WzrPAJsbLBFvqlHt7k CS+Ss4ly+RwpY9evHylwO3do1HbWAd0DbjjcVXUm4cWhHrSMLohjOFUM/2yoTY4lMdor UV7q+JbqOgOymPrBZDbTi7HIs+xnvwqzvya04rv4esLVMFKfRxhmNBeMzKMA8ZLBGfyl 3Jj/z40cCjmus14aQhtzTeyrvnoV3GO9mUzJ5Df/08YX+qAW/0/TL4mPiKiq7ZJT76N/ +OIEb8hBJLrW/1Wg+HnGlGL+v5kboUJW06m+zDX7/ATVgTo+k3lctBx5ppaGhNrnpM1R OFhQ== X-Gm-Message-State: AAQBX9eMIHKF8rEZdXCK3vg2SOW2J12uHTY5Q0cB2AaqxARKUPwp1PX+ tBuJqV2ObJ9hAP/4hNvpqKatTdF8xAg= X-Google-Smtp-Source: AKy350aFg6fqL8mrGqM2OXU2Zs3QnWkYQ00LQ/DDwILWvKzccHcg8V7kb7pim/6ZJXft4RRfzkQNWA== X-Received: by 2002:a17:906:1907:b0:958:cc8:bd55 with SMTP id a7-20020a170906190700b009580cc8bd55mr2169339eje.0.1682176057798; Sat, 22 Apr 2023 08:07:37 -0700 (PDT) Received: from Provence.localdomain (dynamic-077-191-017-015.77.191.pool.telefonica.de. [77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:37 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 02/13] hw/ide/via: Implement ISA IRQ routing Date: Sat, 22 Apr 2023 17:07:17 +0200 Message-Id: <20230422150728.176512-3-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62d; envelope-from=shentey@gmail.com; helo=mail-ej1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The VIA south bridge allows the legacy IDE interrupts to be routed to four different ISA interrupts. This can be configured through the 0x4a register in the PCI configuration space of the ISA function. The default routing matches the legacy ISA IRQs, that is 14 and 15. Implement this missing piece of the VIA south bridge. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- hw/ide/via.c | 6 ++++-- hw/isa/vt82c686.c | 17 +++++++++++++++++ 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/ide/via.c b/hw/ide/via.c index 177baea9a7..0caae52276 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -31,6 +31,7 @@ #include "sysemu/dma.h" #include "hw/isa/vt82c686.h" #include "hw/ide/pci.h" +#include "hw/irq.h" #include "trace.h" static uint64_t bmdma_read(void *opaque, hwaddr addr, @@ -104,7 +105,8 @@ static void bmdma_setup_bar(PCIIDEState *d) static void via_ide_set_irq(void *opaque, int n, int level) { - PCIDevice *d = PCI_DEVICE(opaque); + PCIIDEState *s = opaque; + PCIDevice *d = PCI_DEVICE(s); if (level) { d->config[0x70 + n * 8] |= 0x80; @@ -112,7 +114,7 @@ static void via_ide_set_irq(void *opaque, int n, int level) d->config[0x70 + n * 8] &= ~0x80; } - via_isa_set_irq(pci_get_function_0(d), 14 + n, level); + qemu_set_irq(s->isa_irq[n], level); } static void via_ide_reset(DeviceState *dev) diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index ca89119ce0..c7e29bb46a 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -568,9 +568,19 @@ static const VMStateDescription vmstate_via = { } }; +static void via_isa_set_ide_irq(void *opaque, int n, int level) +{ + static const uint8_t irqs[] = { 14, 15, 10, 11 }; + ViaISAState *s = opaque; + uint8_t irq = irqs[(s->dev.config[0x4a] >> (n * 2)) & 0x3]; + + qemu_set_irq(s->isa_irqs_in[irq], level); +} + static void via_isa_init(Object *obj) { ViaISAState *s = VIA_ISA(obj); + DeviceState *dev = DEVICE(s); object_initialize_child(obj, "rtc", &s->rtc, TYPE_MC146818_RTC); object_initialize_child(obj, "ide", &s->ide, TYPE_VIA_IDE); @@ -578,6 +588,8 @@ static void via_isa_init(Object *obj) object_initialize_child(obj, "uhci2", &s->uhci[1], TYPE_VT82C686B_USB_UHCI); object_initialize_child(obj, "ac97", &s->ac97, TYPE_VIA_AC97); object_initialize_child(obj, "mc97", &s->mc97, TYPE_VIA_MC97); + + qdev_init_gpio_in_named(dev, via_isa_set_ide_irq, "ide", ARRAY_SIZE(s->ide.isa_irq)); } static const TypeInfo via_isa_info = { @@ -692,6 +704,10 @@ static void via_isa_realize(PCIDevice *d, Error **errp) if (!qdev_realize(DEVICE(&s->ide), BUS(pci_bus), errp)) { return; } + for (i = 0; i < 2; i++) { + qdev_connect_gpio_out(DEVICE(&s->ide), i, + qdev_get_gpio_in_named(DEVICE(s), "ide", i)); + } /* Functions 2-3: USB Ports */ for (i = 0; i < ARRAY_SIZE(s->uhci); i++) { @@ -814,6 +830,7 @@ static void vt8231_isa_reset(DeviceState *dev) PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); + pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */ pci_conf[0x67] = 0x08; /* Fast IR Config */ pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */ From patchwork Sat Apr 22 15:07:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221022 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 74C54C77B76 for ; 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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:38 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 03/13] hw/isa/vt82c686: Remove via_isa_set_irq() Date: Sat, 22 Apr 2023 17:07:18 +0200 Message-Id: <20230422150728.176512-4-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::629; envelope-from=shentey@gmail.com; helo=mail-ej1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that via_isa_set_irq() is unused it can be removed. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- include/hw/isa/vt82c686.h | 2 -- hw/isa/vt82c686.c | 6 ------ 2 files changed, 8 deletions(-) diff --git a/include/hw/isa/vt82c686.h b/include/hw/isa/vt82c686.h index da1722daf2..b6e95b2851 100644 --- a/include/hw/isa/vt82c686.h +++ b/include/hw/isa/vt82c686.h @@ -34,6 +34,4 @@ struct ViaAC97State { uint32_t ac97_cmd; }; -void via_isa_set_irq(PCIDevice *d, int n, int level); - #endif diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index c7e29bb46a..a69888a396 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -604,12 +604,6 @@ static const TypeInfo via_isa_info = { }, }; -void via_isa_set_irq(PCIDevice *d, int n, int level) -{ - ViaISAState *s = VIA_ISA(d); - qemu_set_irq(s->isa_irqs_in[n], level); -} - static void via_isa_request_i8259_irq(void *opaque, int irq, int level) { ViaISAState *s = opaque; From patchwork Sat Apr 22 15:07:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 58D96C6FD18 for ; Sat, 22 Apr 2023 15:10:05 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqEq2-0001sx-NL; Sat, 22 Apr 2023 11:07:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqEq0-0001o5-57; Sat, 22 Apr 2023 11:07:44 -0400 Received: from mail-ej1-x62e.google.com ([2a00:1450:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqEpy-00059P-Gn; Sat, 22 Apr 2023 11:07:43 -0400 Received: by mail-ej1-x62e.google.com with SMTP id a640c23a62f3a-94f32588c13so373844266b.2; Sat, 22 Apr 2023 08:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682176060; x=1684768060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=muBkECbZkz3PPDQCsG7ydl9JvU+1aeqdPslh1wRssVc=; b=Aq0XsN9TtSS0usTAlTJ7nP0eM4bVGNN/vkUQ3ZCCeLWPEnmpPNdpI/F898OQ9hX9+z 7LNd0R6ePJKSf2+8m0qy0N3+qr1iha1OAjUbvet2j0Q8ofkJq/lrRZkTsxcqemktCEWL ZfiSGqvszQzmG7iie4lJ7Ejo6gG9+JQsEqE4fQwbEs2RjeQQt+7npEs45dHVYI2I3TbU 6zXnI1H33pnCk0kc9DLLieDI3OXwduDcNQRlsy4kZiayIPix2P3YLSiP1mkxsDYUMtBa 7fYrc7yAGdTN0mYl/MJEaXPz56qkLuUh8Il/8MCT0EY06muC8yrCnCNC6VW0VVVlVu+D DOcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682176060; x=1684768060; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=muBkECbZkz3PPDQCsG7ydl9JvU+1aeqdPslh1wRssVc=; b=OeXCtKjC87RAlmXOhu9F9cOlwsZxZQpOgidcS0X40uKR6LCA8V6ZyssWpQrFld4a8r a2v3pcxGeAQVuct15A90f4uPvt00E+qNd8jXN2vnGUr2KNasqV1WszTkOcvXD6QPfCLo cmYvQ5OT2b+uiarCjlWmnCAFuFi5Uy3ZSH9AwN/Vu83BjnHgFFxQU7lwQxzNIGZHnU/1 5MgwwSXc0or2Iw7BMPtmO9pi4YzpzkbyXZTlMjup0zlVPYZb7FiUc+qvGlQgYiwvCtgY 7UdHNf+tdu5dH0L2mq66laQcEmqIwZac3OM9/r76K8nxH8j3t4BAXAiEgqHmiOWMKDJV aVYw== X-Gm-Message-State: AAQBX9ejia4M80d554lL9e11Mcczn2bMGi8uBu1MA4NaSeAZp09iXOYU WC7QSkzOIF5L3xr4szIB7VC8xrvl9zE= X-Google-Smtp-Source: AKy350blfDzx1ILyqcWMTq7PQfkUAa8BUu7Mu3klKw2iqDBnIADattD6xvPmbwFPnxuRsXY/TDk5JA== X-Received: by 2002:a17:906:7d6:b0:957:2d2a:e8a2 with SMTP id m22-20020a17090607d600b009572d2ae8a2mr4386577ejc.27.1682176060066; Sat, 22 Apr 2023 08:07:40 -0700 (PDT) Received: from Provence.localdomain (dynamic-077-191-017-015.77.191.pool.telefonica.de. [77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:39 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 04/13] hw/ide: Extract IDEBus assignment into bmdma_init() Date: Sat, 22 Apr 2023 17:07:19 +0200 Message-Id: <20230422150728.176512-5-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=shentey@gmail.com; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Every invocation of bmdma_init() is followed by `d->bmdma[i].bus = &d->bus[i]`. Resolve this redundancy by extracting it into bmdma_init(). Signed-off-by: Bernhard Beschow Reviewed-by: BALATON Zoltan Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland --- hw/ide/cmd646.c | 1 - hw/ide/pci.c | 1 + hw/ide/piix.c | 1 - hw/ide/sii3112.c | 1 - hw/ide/via.c | 1 - 5 files changed, 1 insertion(+), 4 deletions(-) diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index a68357c1c5..a094a6e12a 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -297,7 +297,6 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i)); bmdma_init(&d->bus[i], &d->bmdma[i], d); - d->bmdma[i].bus = &d->bus[i]; ide_bus_register_restart_cb(&d->bus[i]); } } diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 942e216b9b..67e0998ff0 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -519,6 +519,7 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d) bus->dma = &bm->dma; bm->irq = bus->irq; bus->irq = qemu_allocate_irq(bmdma_irq, bm, 0); + bm->bus = bus; bm->pci_dev = d; } diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 41d60921e3..a32f7ccece 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -144,7 +144,6 @@ static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp) ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); bmdma_init(&d->bus[i], &d->bmdma[i], d); - d->bmdma[i].bus = &d->bus[i]; ide_bus_register_restart_cb(&d->bus[i]); return true; diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index f9becdff8e..5dd3d03c29 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -287,7 +287,6 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp) ide_bus_init_output_irq(&s->bus[i], qdev_get_gpio_in(ds, i)); bmdma_init(&s->bus[i], &s->bmdma[i], s); - s->bmdma[i].bus = &s->bus[i]; ide_bus_register_restart_cb(&s->bus[i]); } } diff --git a/hw/ide/via.c b/hw/ide/via.c index 0caae52276..91253fa4ef 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -196,7 +196,6 @@ static void via_ide_realize(PCIDevice *dev, Error **errp) ide_bus_init_output_irq(&d->bus[i], qdev_get_gpio_in(ds, i)); bmdma_init(&d->bus[i], &d->bmdma[i], d); - d->bmdma[i].bus = &d->bus[i]; ide_bus_register_restart_cb(&d->bus[i]); } } From patchwork Sat Apr 22 15:07:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221035 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C5256C7618E for ; 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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:40 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 05/13] hw/ide: Extract pci_ide_class_init() Date: Sat, 22 Apr 2023 17:07:20 +0200 Message-Id: <20230422150728.176512-6-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Resolves redundant code in every PCI IDE device model. --- include/hw/ide/pci.h | 1 - hw/ide/cmd646.c | 15 --------------- hw/ide/pci.c | 25 ++++++++++++++++++++++++- hw/ide/piix.c | 19 ------------------- hw/ide/sii3112.c | 3 ++- hw/ide/via.c | 15 --------------- 6 files changed, 26 insertions(+), 52 deletions(-) diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index 74c127e32f..7bc4e53d02 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -61,7 +61,6 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val); extern MemoryRegionOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev); -extern const VMStateDescription vmstate_ide_pci; extern const MemoryRegionOps pci_ide_cmd_le_ops; extern const MemoryRegionOps pci_ide_data_le_ops; #endif diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index a094a6e12a..9aabf80e52 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -301,17 +301,6 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) } } -static void pci_cmd646_ide_exitfn(PCIDevice *dev) -{ - PCIIDEState *d = PCI_IDE(dev); - unsigned i; - - for (i = 0; i < 2; ++i) { - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); - } -} - static Property cmd646_ide_properties[] = { DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), DEFINE_PROP_END_OF_LIST(), @@ -323,17 +312,13 @@ static void cmd646_ide_class_init(ObjectClass *klass, void *data) PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); dc->reset = cmd646_reset; - dc->vmsd = &vmstate_ide_pci; k->realize = pci_cmd646_ide_realize; - k->exit = pci_cmd646_ide_exitfn; k->vendor_id = PCI_VENDOR_ID_CMD; k->device_id = PCI_DEVICE_ID_CMD_646; k->revision = 0x07; - k->class_id = PCI_CLASS_STORAGE_IDE; k->config_read = cmd646_pci_config_read; k->config_write = cmd646_pci_config_write; device_class_set_props(dc, cmd646_ide_properties); - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo cmd646_ide_info = { diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 67e0998ff0..8bea92e394 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -467,7 +467,7 @@ static int ide_pci_post_load(void *opaque, int version_id) return 0; } -const VMStateDescription vmstate_ide_pci = { +static const VMStateDescription vmstate_ide_pci = { .name = "ide", .version_id = 3, .minimum_version_id = 0, @@ -530,11 +530,34 @@ static void pci_ide_init(Object *obj) qdev_init_gpio_out(DEVICE(d), d->isa_irq, ARRAY_SIZE(d->isa_irq)); } +static void pci_ide_exitfn(PCIDevice *dev) +{ + PCIIDEState *d = PCI_IDE(dev); + unsigned i; + + for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) { + memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); + memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); + } +} + +static void pci_ide_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + dc->vmsd = &vmstate_ide_pci; + k->exit = pci_ide_exitfn; + k->class_id = PCI_CLASS_STORAGE_IDE; + set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); +} + static const TypeInfo pci_ide_type_info = { .name = TYPE_PCI_IDE, .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(PCIIDEState), .instance_init = pci_ide_init, + .class_init = pci_ide_class_init, .abstract = true, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, diff --git a/hw/ide/piix.c b/hw/ide/piix.c index a32f7ccece..4e6ca99123 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -159,8 +159,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) bmdma_setup_bar(d); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); - vmstate_register(VMSTATE_IF(dev), 0, &vmstate_ide_pci, d); - for (unsigned i = 0; i < 2; i++) { if (!pci_piix_init_bus(d, i, errp)) { return; @@ -168,17 +166,6 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) } } -static void pci_piix_ide_exitfn(PCIDevice *dev) -{ - PCIIDEState *d = PCI_IDE(dev); - unsigned i; - - for (i = 0; i < 2; ++i) { - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); - } -} - /* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */ static void piix3_ide_class_init(ObjectClass *klass, void *data) { @@ -187,11 +174,8 @@ static void piix3_ide_class_init(ObjectClass *klass, void *data) dc->reset = piix_ide_reset; k->realize = pci_piix_ide_realize; - k->exit = pci_piix_ide_exitfn; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371SB_1; - k->class_id = PCI_CLASS_STORAGE_IDE; - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->hotpluggable = false; } @@ -209,11 +193,8 @@ static void piix4_ide_class_init(ObjectClass *klass, void *data) dc->reset = piix_ide_reset; k->realize = pci_piix_ide_realize; - k->exit = pci_piix_ide_exitfn; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82371AB; - k->class_id = PCI_CLASS_STORAGE_IDE; - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); dc->hotpluggable = false; } diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 5dd3d03c29..0af897a9ef 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -301,9 +301,10 @@ static void sii3112_pci_class_init(ObjectClass *klass, void *data) pd->class_id = PCI_CLASS_STORAGE_RAID; pd->revision = 1; pd->realize = sii3112_pci_realize; + pd->exit = NULL; dc->reset = sii3112_reset; + dc->vmsd = NULL; dc->desc = "SiI3112A SATA controller"; - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo sii3112_pci_info = { diff --git a/hw/ide/via.c b/hw/ide/via.c index 91253fa4ef..287143a005 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -200,34 +200,19 @@ static void via_ide_realize(PCIDevice *dev, Error **errp) } } -static void via_ide_exitfn(PCIDevice *dev) -{ - PCIIDEState *d = PCI_IDE(dev); - unsigned i; - - for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) { - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); - } -} - static void via_ide_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); dc->reset = via_ide_reset; - dc->vmsd = &vmstate_ide_pci; /* Reason: only works as function of VIA southbridge */ dc->user_creatable = false; k->realize = via_ide_realize; - k->exit = via_ide_exitfn; k->vendor_id = PCI_VENDOR_ID_VIA; k->device_id = PCI_DEVICE_ID_VIA_IDE; k->revision = 0x06; - k->class_id = PCI_CLASS_STORAGE_IDE; - set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); } static const TypeInfo via_ide_info = { From patchwork Sat Apr 22 15:07:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221027 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A39DEC77B76 for ; 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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:42 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 06/13] hw/ide: Extract bmdma_init_ops() Date: Sat, 22 Apr 2023 17:07:21 +0200 Message-Id: <20230422150728.176512-7-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=shentey@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There are three private copies of bmdma_setup_bar() with small adaptions. Consolidate them into one public implementation. While at it rename the function to bmdma_init_ops() to reflect that the memory regions being initialized represent BMDMA operations. The actual mapping as a PCI BAR is still performed separately in each device. Note that the bmdma_bar attribute will be renamed in a separate commit. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland --- include/hw/ide/pci.h | 1 + hw/ide/cmd646.c | 20 +------------------- hw/ide/pci.c | 16 ++++++++++++++++ hw/ide/piix.c | 19 +------------------ hw/ide/via.c | 19 +------------------ 5 files changed, 20 insertions(+), 55 deletions(-) diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index 7bc4e53d02..597c77c7ad 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -57,6 +57,7 @@ struct PCIIDEState { }; void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d); +void bmdma_init_ops(PCIIDEState *d, const MemoryRegionOps *bmdma_ops); void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val); extern MemoryRegionOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev); diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index 9aabf80e52..6fd09fe74e 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -161,24 +161,6 @@ static const MemoryRegionOps cmd646_bmdma_ops = { .write = bmdma_write, }; -static void bmdma_setup_bar(PCIIDEState *d) -{ - BMDMAState *bm; - int i; - - memory_region_init(&d->bmdma_bar, OBJECT(d), "cmd646-bmdma", 16); - for(i = 0;i < 2; i++) { - bm = &d->bmdma[i]; - memory_region_init_io(&bm->extra_io, OBJECT(d), &cmd646_bmdma_ops, bm, - "cmd646-bmdma-bus", 4); - memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); - memory_region_init_io(&bm->addr_ioport, OBJECT(d), - &bmdma_addr_ioport_ops, bm, - "cmd646-bmdma-ioport", 4); - memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); - } -} - static void cmd646_update_irq(PCIDevice *pd) { int pci_level; @@ -285,7 +267,7 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) &d->bus[1], "cmd646-cmd1", 4); pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); - bmdma_setup_bar(d); + bmdma_init_ops(d, &cmd646_bmdma_ops); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); /* TODO: RST# value should be 0 */ diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 8bea92e394..65ed6f7f72 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -523,6 +523,22 @@ void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d) bm->pci_dev = d; } +void bmdma_init_ops(PCIIDEState *d, const MemoryRegionOps *bmdma_ops) +{ + size_t i; + + memory_region_init(&d->bmdma_bar, OBJECT(d), "bmdma-container", 16); + for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) { + BMDMAState *bm = &d->bmdma[i]; + + memory_region_init_io(&bm->extra_io, OBJECT(d), bmdma_ops, bm, "bmdma-ops", 4); + memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); + memory_region_init_io(&bm->addr_ioport, OBJECT(d), &bmdma_addr_ioport_ops, bm, + "bmdma-ioport-ops", 4); + memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); + } +} + static void pci_ide_init(Object *obj) { PCIIDEState *d = PCI_IDE(obj); diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 4e6ca99123..5611473d37 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -86,23 +86,6 @@ static const MemoryRegionOps piix_bmdma_ops = { .write = bmdma_write, }; -static void bmdma_setup_bar(PCIIDEState *d) -{ - int i; - - memory_region_init(&d->bmdma_bar, OBJECT(d), "piix-bmdma-container", 16); - for(i = 0;i < 2; i++) { - BMDMAState *bm = &d->bmdma[i]; - - memory_region_init_io(&bm->extra_io, OBJECT(d), &piix_bmdma_ops, bm, - "piix-bmdma", 4); - memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); - memory_region_init_io(&bm->addr_ioport, OBJECT(d), - &bmdma_addr_ioport_ops, bm, "bmdma", 4); - memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); - } -} - static void piix_ide_reset(DeviceState *dev) { PCIIDEState *d = PCI_IDE(dev); @@ -156,7 +139,7 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode - bmdma_setup_bar(d); + bmdma_init_ops(d, &piix_bmdma_ops); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); for (unsigned i = 0; i < 2; i++) { diff --git a/hw/ide/via.c b/hw/ide/via.c index 287143a005..40704e2857 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -86,23 +86,6 @@ static const MemoryRegionOps via_bmdma_ops = { .write = bmdma_write, }; -static void bmdma_setup_bar(PCIIDEState *d) -{ - int i; - - memory_region_init(&d->bmdma_bar, OBJECT(d), "via-bmdma-container", 16); - for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) { - BMDMAState *bm = &d->bmdma[i]; - - memory_region_init_io(&bm->extra_io, OBJECT(d), &via_bmdma_ops, bm, - "via-bmdma", 4); - memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); - memory_region_init_io(&bm->addr_ioport, OBJECT(d), - &bmdma_addr_ioport_ops, bm, "bmdma", 4); - memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); - } -} - static void via_ide_set_irq(void *opaque, int n, int level) { PCIIDEState *s = opaque; @@ -187,7 +170,7 @@ static void via_ide_realize(PCIDevice *dev, Error **errp) &d->bus[1], "via-ide1-cmd", 4); pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); - bmdma_setup_bar(d); + bmdma_init_ops(d, &via_bmdma_ops); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); qdev_init_gpio_in(ds, via_ide_set_irq, ARRAY_SIZE(d->bus)); From patchwork Sat Apr 22 15:07:22 2023 Content-Type: text/plain; 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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:43 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 07/13] hw/ide: Extract pci_ide_{cmd, data}_le_ops initialization into base class constructor Date: Sat, 22 Apr 2023 17:07:22 +0200 Message-Id: <20230422150728.176512-8-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=shentey@gmail.com; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org There is redundant code in cmd646 and via which can be extracted into the base class. In case of piix and sii3112 this is currently unneccessary but shouldn't interfere since the memory regions aren't mapped by those devices. In few commits later this will be changed, i.e. those device models will also make use of these memory regions. Signed-off-by: Bernhard Beschow Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland --- hw/ide/cmd646.c | 11 ----------- hw/ide/pci.c | 10 ++++++++++ hw/ide/via.c | 11 ----------- 3 files changed, 10 insertions(+), 22 deletions(-) diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index 6fd09fe74e..85716aaf17 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -251,20 +251,9 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) dev->wmask[MRDMODE] = 0x0; dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1; - memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, - &d->bus[0], "cmd646-data0", 8); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); - - memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, - &d->bus[0], "cmd646-cmd0", 4); pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); - - memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, - &d->bus[1], "cmd646-data1", 8); pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); - - memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, - &d->bus[1], "cmd646-cmd1", 4); pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); bmdma_init_ops(d, &cmd646_bmdma_ops); diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 65ed6f7f72..a9194313bd 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -543,6 +543,16 @@ static void pci_ide_init(Object *obj) { PCIIDEState *d = PCI_IDE(obj); + memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, + &d->bus[0], "pci-ide0-data-ops", 8); + memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, + &d->bus[0], "pci-ide0-cmd-ops", 4); + + memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, + &d->bus[1], "pci-ide1-data-ops", 8); + memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, + &d->bus[1], "pci-ide1-cmd-ops", 4); + qdev_init_gpio_out(DEVICE(d), d->isa_irq, ARRAY_SIZE(d->isa_irq)); } diff --git a/hw/ide/via.c b/hw/ide/via.c index 40704e2857..704a8024cb 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -154,20 +154,9 @@ static void via_ide_realize(PCIDevice *dev, Error **errp) dev->wmask[PCI_INTERRUPT_LINE] = 0; dev->wmask[PCI_CLASS_PROG] = 5; - memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, - &d->bus[0], "via-ide0-data", 8); pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); - - memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, - &d->bus[0], "via-ide0-cmd", 4); pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); - - memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, - &d->bus[1], "via-ide1-data", 8); pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); - - memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, - &d->bus[1], "via-ide1-cmd", 4); pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); bmdma_init_ops(d, &via_bmdma_ops); From patchwork Sat Apr 22 15:07:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09E8DC77B7C for ; Sat, 22 Apr 2023 15:08:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqEq6-0001wq-ON; Sat, 22 Apr 2023 11:07:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqEq5-0001wD-5J; Sat, 22 Apr 2023 11:07:49 -0400 Received: from mail-ed1-x52c.google.com ([2a00:1450:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqEq3-0005C3-Ap; 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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:44 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 08/13] hw/ide: Rename PCIIDEState::*_bar attributes Date: Sat, 22 Apr 2023 17:07:23 +0200 Message-Id: <20230422150728.176512-9-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The attributes represent memory regions containing operations which are mapped by the device models into PCI BARs. Reflect this by changing the suffic into "_ops". Note that in a few commits piix will also use the {cmd,data}_ops but won't map them into BARs. This further suggests that the "_bar" suffix doesn't match very well. Signed-off-by: Bernhard Beschow --- include/hw/ide/pci.h | 6 +++--- hw/ide/cmd646.c | 10 +++++----- hw/ide/pci.c | 18 +++++++++--------- hw/ide/piix.c | 2 +- hw/ide/via.c | 10 +++++----- 5 files changed, 23 insertions(+), 23 deletions(-) diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index 597c77c7ad..5025df5b82 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -51,9 +51,9 @@ struct PCIIDEState { BMDMAState bmdma[2]; qemu_irq isa_irq[2]; uint32_t secondary; /* used only for cmd646 */ - MemoryRegion bmdma_bar; - MemoryRegion cmd_bar[2]; - MemoryRegion data_bar[2]; + MemoryRegion bmdma_ops; + MemoryRegion cmd_ops[2]; + MemoryRegion data_ops[2]; }; void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d); diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index 85716aaf17..b9d005a357 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -251,13 +251,13 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) dev->wmask[MRDMODE] = 0x0; dev->w1cmask[MRDMODE] = MRDMODE_INTR_CH0 | MRDMODE_INTR_CH1; - pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); - pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); - pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); - pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_ops[0]); + pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_ops[0]); + pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_ops[1]); + pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_ops[1]); bmdma_init_ops(d, &cmd646_bmdma_ops); - pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); + pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_ops); /* TODO: RST# value should be 0 */ pci_conf[PCI_INTERRUPT_PIN] = 0x01; // interrupt on pin 1 diff --git a/hw/ide/pci.c b/hw/ide/pci.c index a9194313bd..b2fcc00a64 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -527,15 +527,15 @@ void bmdma_init_ops(PCIIDEState *d, const MemoryRegionOps *bmdma_ops) { size_t i; - memory_region_init(&d->bmdma_bar, OBJECT(d), "bmdma-container", 16); + memory_region_init(&d->bmdma_ops, OBJECT(d), "bmdma-container", 16); for (i = 0; i < ARRAY_SIZE(d->bmdma); i++) { BMDMAState *bm = &d->bmdma[i]; memory_region_init_io(&bm->extra_io, OBJECT(d), bmdma_ops, bm, "bmdma-ops", 4); - memory_region_add_subregion(&d->bmdma_bar, i * 8, &bm->extra_io); + memory_region_add_subregion(&d->bmdma_ops, i * 8, &bm->extra_io); memory_region_init_io(&bm->addr_ioport, OBJECT(d), &bmdma_addr_ioport_ops, bm, "bmdma-ioport-ops", 4); - memory_region_add_subregion(&d->bmdma_bar, i * 8 + 4, &bm->addr_ioport); + memory_region_add_subregion(&d->bmdma_ops, i * 8 + 4, &bm->addr_ioport); } } @@ -543,14 +543,14 @@ static void pci_ide_init(Object *obj) { PCIIDEState *d = PCI_IDE(obj); - memory_region_init_io(&d->data_bar[0], OBJECT(d), &pci_ide_data_le_ops, + memory_region_init_io(&d->data_ops[0], OBJECT(d), &pci_ide_data_le_ops, &d->bus[0], "pci-ide0-data-ops", 8); - memory_region_init_io(&d->cmd_bar[0], OBJECT(d), &pci_ide_cmd_le_ops, + memory_region_init_io(&d->cmd_ops[0], OBJECT(d), &pci_ide_cmd_le_ops, &d->bus[0], "pci-ide0-cmd-ops", 4); - memory_region_init_io(&d->data_bar[1], OBJECT(d), &pci_ide_data_le_ops, + memory_region_init_io(&d->data_ops[1], OBJECT(d), &pci_ide_data_le_ops, &d->bus[1], "pci-ide1-data-ops", 8); - memory_region_init_io(&d->cmd_bar[1], OBJECT(d), &pci_ide_cmd_le_ops, + memory_region_init_io(&d->cmd_ops[1], OBJECT(d), &pci_ide_cmd_le_ops, &d->bus[1], "pci-ide1-cmd-ops", 4); qdev_init_gpio_out(DEVICE(d), d->isa_irq, ARRAY_SIZE(d->isa_irq)); @@ -562,8 +562,8 @@ static void pci_ide_exitfn(PCIDevice *dev) unsigned i; for (i = 0; i < ARRAY_SIZE(d->bmdma); ++i) { - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].extra_io); - memory_region_del_subregion(&d->bmdma_bar, &d->bmdma[i].addr_ioport); + memory_region_del_subregion(&d->bmdma_ops, &d->bmdma[i].extra_io); + memory_region_del_subregion(&d->bmdma_ops, &d->bmdma[i].addr_ioport); } } diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 5611473d37..6942b484f9 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -140,7 +140,7 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode bmdma_init_ops(d, &piix_bmdma_ops); - pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); + pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_ops); for (unsigned i = 0; i < 2; i++) { if (!pci_piix_init_bus(d, i, errp)) { diff --git a/hw/ide/via.c b/hw/ide/via.c index 704a8024cb..35dd97e49b 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -154,13 +154,13 @@ static void via_ide_realize(PCIDevice *dev, Error **errp) dev->wmask[PCI_INTERRUPT_LINE] = 0; dev->wmask[PCI_CLASS_PROG] = 5; - pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[0]); - pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[0]); - pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_bar[1]); - pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_bar[1]); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &d->data_ops[0]); + pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_ops[0]); + pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &d->data_ops[1]); + pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &d->cmd_ops[1]); bmdma_init_ops(d, &via_bmdma_ops); - pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_bar); + pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_ops); qdev_init_gpio_in(ds, via_ide_set_irq, ARRAY_SIZE(d->bus)); for (i = 0; i < ARRAY_SIZE(d->bus); i++) { From patchwork Sat Apr 22 15:07:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1E98C7618E for ; Sat, 22 Apr 2023 15:09:17 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqEq9-0001yW-2r; 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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:45 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 09/13] hw/ide/piix: Disuse isa_get_irq() Date: Sat, 22 Apr 2023 17:07:24 +0200 Message-Id: <20230422150728.176512-10-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=shentey@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org isa_get_irq() asks for an ISADevice which piix-ide doesn't provide. Passing a NULL pointer works but causes the isabus global to be used then. By fishing out TYPE_ISA_BUS from the QOM tree it is possible to achieve the same as using isa_get_irq(). This is an alternative solution to commit 9405d87be25d 'hw/ide: Fix crash when plugging a piix3-ide device into the x-remote machine' which allows for cleaning up the ISA API while keeping PIIX IDE functions user-createable. Signed-off-by: Bernhard Beschow --- hw/ide/piix.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 6942b484f9..a3a15dc7db 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -104,7 +104,8 @@ static void piix_ide_reset(DeviceState *dev) pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */ } -static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp) +static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, ISABus *isa_bus, + Error **errp) { static const struct { int iobase; @@ -124,7 +125,8 @@ static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, Error **errp) object_get_typename(OBJECT(d)), i); return false; } - ide_bus_init_output_irq(&d->bus[i], isa_get_irq(NULL, port_info[i].isairq)); + ide_bus_init_output_irq(&d->bus[i], + isa_bus_get_irq(isa_bus, port_info[i].isairq)); bmdma_init(&d->bus[i], &d->bmdma[i], d); ide_bus_register_restart_cb(&d->bus[i]); @@ -136,14 +138,29 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) { PCIIDEState *d = PCI_IDE(dev); uint8_t *pci_conf = dev->config; + ISABus *isa_bus; + bool ambiguous; pci_conf[PCI_CLASS_PROG] = 0x80; // legacy ATA mode bmdma_init_ops(d, &piix_bmdma_ops); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &d->bmdma_ops); + isa_bus = ISA_BUS(object_resolve_path_type("", TYPE_ISA_BUS, &ambiguous)); + if (ambiguous) { + error_setg(errp, + "More than one ISA bus found while %s supports only one", + object_get_typename(OBJECT(d))); + return; + } + if (!isa_bus) { + error_setg(errp, "No ISA bus found while %s requires one", + object_get_typename(OBJECT(d))); + return; + } + for (unsigned i = 0; i < 2; i++) { - if (!pci_piix_init_bus(d, i, errp)) { + if (!pci_piix_init_bus(d, i, isa_bus, errp)) { return; } } From patchwork Sat Apr 22 15:07:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 557FDC7618E for ; Sat, 22 Apr 2023 15:09:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqEq9-0001yk-HI; Sat, 22 Apr 2023 11:07:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqEq7-0001xp-Nx; Sat, 22 Apr 2023 11:07:51 -0400 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqEq6-0005CV-10; Sat, 22 Apr 2023 11:07:51 -0400 Received: by mail-ed1-x529.google.com with SMTP id 4fb4d7f45d1cf-508418b6d59so4837243a12.3; Sat, 22 Apr 2023 08:07:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682176066; x=1684768066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=c3NlfVN1e4CUbSX8ASIf+P0h+04YA8+XY04IMvAW5tA=; b=p5qzta5i4ArlWgs75ZJsEl8zVx9/Pm4bNlFEL8GO+yQHJDgxO5mNgkQJ0+OottP+oY 2xPcCo7gG828alTd1I1SY5lHWVLqUCE6mRZQmGXLZR14WYh6/XcbmK4QMAoadHcU1axN ddbDs/Mj3M4ueKm8PR0sWn00+lEDWdVtDmBlNFmQd3DdPKtcS73zNSuvIO2GZltVvnAI 6OwzlH/AfhhbXow+Z6mkHtZa28muS7yPqkIflRIx4teVWlbm0puVu3ly2ftbPa8PNLoC M3NR5gF03BNuenvnrXJOyTGUJvl4vKx855Xtg3W+Opi4R0CQPSayAesju8W9TFeLenE0 mKKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682176066; x=1684768066; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=c3NlfVN1e4CUbSX8ASIf+P0h+04YA8+XY04IMvAW5tA=; b=FHKvVLYCihEpO/X81aVVci6899JfkE3OYDmv2uA2vIvi11PqxQhsn9CRI3MURdiHBd W5Q8nls600nW7j042sMPihEabT/BoXmt652oEPI6wkyvNy1CyDyOqQ2StBZ6zxc5udl0 8N35h9tm41PNebDfv+drQBMNajeGmw+tea5QVnXr/bhdDQMJj/cdSrRqgk9r/MTBbs7A piNzTfSnVm6PkPR1CEGXlhG6VeWCOgoqLdGwbxqNQeY6GAx8Do0/+//PTk4S5/OBjuMM PTaf5JGhEk+Lg/L9PcrZWWn/pcVjzEmz1+vYMQVAoXewceGoHmC5LKg3ps3wr3AKI+U4 4hgA== X-Gm-Message-State: AAQBX9eCKTBSlKtqmQuxFCK2XEHz+r8/rYXu3cliKRRidDgq/nir+l/9 82Q5njV06tdPsMyE9JjnKrq+kKiBpdY= X-Google-Smtp-Source: AKy350bi4nwRTWgUkixaf/swGdaGuhUyS00Ztalg7g1DE/Pnu97Gkhh4zo86F2lCzeF0EjEws2hSsA== X-Received: by 2002:a17:906:3698:b0:958:5c21:3fa7 with SMTP id a24-20020a170906369800b009585c213fa7mr959315ejc.25.1682176066704; Sat, 22 Apr 2023 08:07:46 -0700 (PDT) Received: from Provence.localdomain (dynamic-077-191-017-015.77.191.pool.telefonica.de. [77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:46 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 10/13] hw/ide/piix: Reuse PCIIDEState::{cmd,data}_ops Date: Sat, 22 Apr 2023 17:07:25 +0200 Message-Id: <20230422150728.176512-11-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=shentey@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Now that PCIIDEState::{cmd,data}_ops are initialized in the base class constructor there is an opportunity for PIIX to reuse these attributes. This resolves usage of ide_init_ioport() which would fall back internally to using the isabus global due to NULL being passed as ISADevice by PIIX. Signed-off-by: Bernhard Beschow --- hw/ide/piix.c | 30 +++++++++++++----------------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/hw/ide/piix.c b/hw/ide/piix.c index a3a15dc7db..406a67fa0f 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -104,34 +104,32 @@ static void piix_ide_reset(DeviceState *dev) pci_set_byte(pci_conf + 0x20, 0x01); /* BMIBA: 20-23h */ } -static bool pci_piix_init_bus(PCIIDEState *d, unsigned i, ISABus *isa_bus, - Error **errp) +static void pci_piix_init_bus(PCIIDEState *d, unsigned i, ISABus *isa_bus) { static const struct { int iobase; int iobase2; int isairq; } port_info[] = { - {0x1f0, 0x3f6, 14}, - {0x170, 0x376, 15}, + {0x1f0, 0x3f4, 14}, + {0x170, 0x374, 15}, }; - int ret; + MemoryRegion *address_space_io = pci_address_space_io(PCI_DEVICE(d)); ide_bus_init(&d->bus[i], sizeof(d->bus[i]), DEVICE(d), i, 2); - ret = ide_init_ioport(&d->bus[i], NULL, port_info[i].iobase, - port_info[i].iobase2); - if (ret) { - error_setg_errno(errp, -ret, "Failed to realize %s port %u", - object_get_typename(OBJECT(d)), i); - return false; - } + memory_region_add_subregion(address_space_io, port_info[i].iobase, + &d->data_ops[i]); + /* + * PIIX forwards the last byte of cmd_ops to ISA. Model this using a low + * prio so competing memory regions take precedence. + */ + memory_region_add_subregion_overlap(address_space_io, port_info[i].iobase2, + &d->cmd_ops[i], -1); ide_bus_init_output_irq(&d->bus[i], isa_bus_get_irq(isa_bus, port_info[i].isairq)); bmdma_init(&d->bus[i], &d->bmdma[i], d); ide_bus_register_restart_cb(&d->bus[i]); - - return true; } static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) @@ -160,9 +158,7 @@ static void pci_piix_ide_realize(PCIDevice *dev, Error **errp) } for (unsigned i = 0; i < 2; i++) { - if (!pci_piix_init_bus(d, i, isa_bus, errp)) { - return; - } + pci_piix_init_bus(d, i, isa_bus); } } From patchwork Sat Apr 22 15:07:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221023 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5CE26C7618E for ; Sat, 22 Apr 2023 15:08:37 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqEqB-00022u-GF; Sat, 22 Apr 2023 11:07:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqEq9-0001yX-7m; Sat, 22 Apr 2023 11:07:53 -0400 Received: from mail-ed1-x536.google.com ([2a00:1450:4864:20::536]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pqEq6-00059f-BF; Sat, 22 Apr 2023 11:07:52 -0400 Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-506bdf29712so20427980a12.0; Sat, 22 Apr 2023 08:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682176068; x=1684768068; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JJpI+E7seMl1Wg5225zCGbACaVQwDu0wCPc1qczA8pM=; b=MFS9cXIRVuhGUq1DdjJtEKgDKYuBxt8dA2lrO5QPclLetgISCa+HBlGhSQqDhmdLqB AVhY8L7/ta7CZZ+acHTNgPzdBvUIeTWL4qRJ3AX62kKwVQ54NAiRmEXjMoREbaizapO9 g1KkMbIEB058WU4tz7kSMFlWVOKochz9QJ73tsT44j4Lwq1zn541Pyz5+R1OQX/iWugu 0J0ThHcqj2r676lDUzdBy80Dd2nOM+sm+SidW6gNckEzkPJjAC9gXFQRPsZIIo8zRc/5 QzCWUw0O5YoPCxVKXLaUNhry1heNRCTkuGvofjVWAyVk4iXlzwCpAAeNoBhZni+MRrFA Wv/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682176068; x=1684768068; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JJpI+E7seMl1Wg5225zCGbACaVQwDu0wCPc1qczA8pM=; b=EPVm8TO+JqRMks5Czvvv/XCKCl2rFByItHIYwvhwNURBqFNkK/t3lfy6Uw7Q7uMoJZ YGNGgrZq8KW3AyyrWriaVcn1Bt7RJxccmLIW8xcCqDoT97GtTb325/QZtUmHitV0a7b/ dvc842vZOO4hGcSs74DrluSnoitpd1d9GAHAmwE0I/uAow5y9Sq9ViNoziGu9Hi4wYbc EMEaK8uz14ABbZdoD3Ze/K33XjR4DRyVriPa5GjLYu/lcvymIOjtS5zEIRGx42jE8dmE /k95ow/SZjzybAiWE2nhkbH3HLfX2pcrH9zNLoyzTgR0gkfz6Ta/eNczPA+BbmgAahq6 BX0A== X-Gm-Message-State: AAQBX9enNlkfvIAkzsTNk3GDojgPckszXZDR55MMLPkrlksT8+Lrlm6k eJTqa7dnOE1S8HXhmTOHKt4taPJrfTE= X-Google-Smtp-Source: AKy350ailoOg60oz8XOqT33HN9t/n19tmlgpVdgtKvgk/1MEjbejWYeYGCqQgLnRh7JNq4LL3hw0HA== X-Received: by 2002:a17:906:7141:b0:94f:2a13:4df4 with SMTP id z1-20020a170906714100b0094f2a134df4mr5197835ejj.22.1682176067626; Sat, 22 Apr 2023 08:07:47 -0700 (PDT) Received: from Provence.localdomain (dynamic-077-191-017-015.77.191.pool.telefonica.de. [77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:47 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 11/13] hw/ide/sii3112: Reuse PCIIDEState::{cmd,data}_ops Date: Sat, 22 Apr 2023 17:07:26 +0200 Message-Id: <20230422150728.176512-12-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Allows to unexport pci_ide_{cmd,data}_le_ops and models TYPE_SII3112_PCI as a standard-compliant PCI IDE device. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- include/hw/ide/pci.h | 2 -- hw/ide/pci.c | 4 ++-- hw/ide/sii3112.c | 50 ++++++++++++++++---------------------------- 3 files changed, 20 insertions(+), 36 deletions(-) diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index 5025df5b82..dbb4b13161 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -62,6 +62,4 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val); extern MemoryRegionOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev); -extern const MemoryRegionOps pci_ide_cmd_le_ops; -extern const MemoryRegionOps pci_ide_data_le_ops; #endif diff --git a/hw/ide/pci.c b/hw/ide/pci.c index b2fcc00a64..97ccc75aa6 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -60,7 +60,7 @@ static void pci_ide_ctrl_write(void *opaque, hwaddr addr, ide_ctrl_write(bus, addr + 2, data); } -const MemoryRegionOps pci_ide_cmd_le_ops = { +static const MemoryRegionOps pci_ide_cmd_le_ops = { .read = pci_ide_status_read, .write = pci_ide_ctrl_write, .endianness = DEVICE_LITTLE_ENDIAN, @@ -98,7 +98,7 @@ static void pci_ide_data_write(void *opaque, hwaddr addr, } } -const MemoryRegionOps pci_ide_data_le_ops = { +static const MemoryRegionOps pci_ide_data_le_ops = { .read = pci_ide_data_read, .write = pci_ide_data_write, .endianness = DEVICE_LITTLE_ENDIAN, diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 0af897a9ef..9cf920369f 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -88,21 +88,9 @@ static uint64_t sii3112_reg_read(void *opaque, hwaddr addr, val |= (d->regs[1].confstat & (1UL << 11) ? (1 << 4) : 0); val |= (uint32_t)d->i.bmdma[1].status << 16; break; - case 0x80 ... 0x87: - val = pci_ide_data_le_ops.read(&d->i.bus[0], addr - 0x80, size); - break; - case 0x8a: - val = pci_ide_cmd_le_ops.read(&d->i.bus[0], 2, size); - break; case 0xa0: val = d->regs[0].confstat; break; - case 0xc0 ... 0xc7: - val = pci_ide_data_le_ops.read(&d->i.bus[1], addr - 0xc0, size); - break; - case 0xca: - val = pci_ide_cmd_le_ops.read(&d->i.bus[1], 2, size); - break; case 0xe0: val = d->regs[1].confstat; break; @@ -171,18 +159,6 @@ static void sii3112_reg_write(void *opaque, hwaddr addr, case 0x0c ... 0x0f: bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size); break; - case 0x80 ... 0x87: - pci_ide_data_le_ops.write(&d->i.bus[0], addr - 0x80, val, size); - break; - case 0x8a: - pci_ide_cmd_le_ops.write(&d->i.bus[0], 2, val, size); - break; - case 0xc0 ... 0xc7: - pci_ide_data_le_ops.write(&d->i.bus[1], addr - 0xc0, val, size); - break; - case 0xca: - pci_ide_cmd_le_ops.write(&d->i.bus[1], 2, val, size); - break; case 0x100: d->regs[0].scontrol = val & 0xfff; if (val & 1) { @@ -259,6 +235,11 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp) pci_config_set_interrupt_pin(dev->config, 1); pci_set_byte(dev->config + PCI_CACHE_LINE_SIZE, 8); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->data_ops[0]); + pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->cmd_ops[0]); + pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->data_ops[1]); + pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &s->cmd_ops[1]); + /* BAR5 is in PCI memory space */ memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d, "sii3112.bar5", 0x200); @@ -266,17 +247,22 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp) /* BAR0-BAR4 are PCI I/O space aliases into BAR5 */ mr = g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &d->mmio, 0x80, 8); - pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_IO, mr); + memory_region_init_alias(mr, OBJECT(d), "sii3112.bar0", &s->data_ops[0], 0, + memory_region_size(&s->data_ops[0])); + memory_region_add_subregion_overlap(&d->mmio, 0x80, mr, 1); mr = g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &d->mmio, 0x88, 4); - pci_register_bar(dev, 1, PCI_BASE_ADDRESS_SPACE_IO, mr); + memory_region_init_alias(mr, OBJECT(d), "sii3112.bar1", &s->cmd_ops[0], 0, + memory_region_size(&s->cmd_ops[0])); + memory_region_add_subregion_overlap(&d->mmio, 0x88, mr, 1); mr = g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &d->mmio, 0xc0, 8); - pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, mr); + memory_region_init_alias(mr, OBJECT(d), "sii3112.bar2", &s->data_ops[1], 0, + memory_region_size(&s->data_ops[1])); + memory_region_add_subregion_overlap(&d->mmio, 0xc0, mr, 1); mr = g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &d->mmio, 0xc8, 4); - pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, mr); + memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &s->cmd_ops[1], 0, + memory_region_size(&s->cmd_ops[1])); + memory_region_add_subregion_overlap(&d->mmio, 0xc8, mr, 1); + mr = g_new(MemoryRegion, 1); memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16); pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr); From patchwork Sat Apr 22 15:07:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bernhard Beschow X-Patchwork-Id: 13221030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 85865C7618E for ; Sat, 22 Apr 2023 15:09:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqEqC-00023T-4D; Sat, 22 Apr 2023 11:07:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqEq9-0001ya-Ca; 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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:48 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 12/13] hw/ide/sii3112: Reuse PCIIDEState::bmdma_ops Date: Sat, 22 Apr 2023 17:07:27 +0200 Message-Id: <20230422150728.176512-13-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=shentey@gmail.com; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Allows to unexport bmdma_addr_ioport_ops and models TYPE_SII3112_PCI as a standard-compliant PCI IDE device. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- include/hw/ide/pci.h | 1 - hw/ide/pci.c | 2 +- hw/ide/sii3112.c | 94 ++++++++++++++++++++++++++------------------ hw/ide/trace-events | 6 ++- 4 files changed, 60 insertions(+), 43 deletions(-) diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index dbb4b13161..81e0370202 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -59,7 +59,6 @@ struct PCIIDEState { void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d); void bmdma_init_ops(PCIIDEState *d, const MemoryRegionOps *bmdma_ops); void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val); -extern MemoryRegionOps bmdma_addr_ioport_ops; void pci_ide_create_devs(PCIDevice *dev); #endif diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 97ccc75aa6..3539b162b7 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -342,7 +342,7 @@ static void bmdma_addr_write(void *opaque, hwaddr addr, bm->addr |= ((data & mask) << shift) & ~3; } -MemoryRegionOps bmdma_addr_ioport_ops = { +static MemoryRegionOps bmdma_addr_ioport_ops = { .read = bmdma_addr_read, .write = bmdma_addr_write, .endianness = DEVICE_LITTLE_ENDIAN, diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 9cf920369f..373c0dd1ee 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -34,47 +34,73 @@ struct SiI3112PCIState { SiI3112Regs regs[2]; }; -/* The sii3112_reg_read and sii3112_reg_write functions implement the - * Internal Register Space - BAR5 (section 6.7 of the data sheet). - */ - -static uint64_t sii3112_reg_read(void *opaque, hwaddr addr, - unsigned int size) +static uint64_t sii3112_bmdma_read(void *opaque, hwaddr addr, unsigned int size) { - SiI3112PCIState *d = opaque; + BMDMAState *bm = opaque; + SiI3112PCIState *d = SII3112_PCI(bm->pci_dev); + int i = (bm == &bm->pci_dev->bmdma[0]) ? 0 : 1; uint64_t val; switch (addr) { case 0x00: - val = d->i.bmdma[0].cmd; + val = bm->cmd; break; case 0x01: - val = d->regs[0].swdata; + val = d->regs[i].swdata; break; case 0x02: - val = d->i.bmdma[0].status; + val = bm->status; break; case 0x03: val = 0; break; - case 0x04 ... 0x07: - val = bmdma_addr_ioport_ops.read(&d->i.bmdma[0], addr - 4, size); - break; - case 0x08: - val = d->i.bmdma[1].cmd; + default: + val = 0; break; - case 0x09: - val = d->regs[1].swdata; + } + trace_sii3112_bmdma_read(size, addr, val); + return val; +} + +static void sii3112_bmdma_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + BMDMAState *bm = opaque; + SiI3112PCIState *d = SII3112_PCI(bm->pci_dev); + int i = (bm == &bm->pci_dev->bmdma[0]) ? 0 : 1; + + trace_sii3112_bmdma_write(size, addr, val); + switch (addr) { + case 0x00: + bmdma_cmd_writeb(bm, val); break; - case 0x0a: - val = d->i.bmdma[1].status; + case 0x01: + d->regs[i].swdata = val & 0x3f; break; - case 0x0b: - val = 0; + case 0x02: + bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 6); break; - case 0x0c ... 0x0f: - val = bmdma_addr_ioport_ops.read(&d->i.bmdma[1], addr - 12, size); + default: break; + } +} + +static const MemoryRegionOps sii3112_bmdma_ops = { + .read = sii3112_bmdma_read, + .write = sii3112_bmdma_write, +}; + +/* The sii3112_reg_read and sii3112_reg_write functions implement the + * Internal Register Space - BAR5 (section 6.7 of the data sheet). + */ + +static uint64_t sii3112_reg_read(void *opaque, hwaddr addr, + unsigned int size) +{ + SiI3112PCIState *d = opaque; + uint64_t val; + + switch (addr) { case 0x10: val = d->i.bmdma[0].cmd; val |= (d->regs[0].confstat & (1UL << 11) ? (1 << 4) : 0); /*SATAINT0*/ @@ -127,38 +153,26 @@ static void sii3112_reg_write(void *opaque, hwaddr addr, trace_sii3112_write(size, addr, val); switch (addr) { - case 0x00: case 0x10: bmdma_cmd_writeb(&d->i.bmdma[0], val); break; - case 0x01: case 0x11: d->regs[0].swdata = val & 0x3f; break; - case 0x02: case 0x12: d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) | (d->i.bmdma[0].status & ~val & 6); break; - case 0x04 ... 0x07: - bmdma_addr_ioport_ops.write(&d->i.bmdma[0], addr - 4, val, size); - break; - case 0x08: case 0x18: bmdma_cmd_writeb(&d->i.bmdma[1], val); break; - case 0x09: case 0x19: d->regs[1].swdata = val & 0x3f; break; - case 0x0a: case 0x1a: d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) | (d->i.bmdma[1].status & ~val & 6); break; - case 0x0c ... 0x0f: - bmdma_addr_ioport_ops.write(&d->i.bmdma[1], addr - 12, val, size); - break; case 0x100: d->regs[0].scontrol = val & 0xfff; if (val & 1) { @@ -240,6 +254,9 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp) pci_register_bar(dev, 2, PCI_BASE_ADDRESS_SPACE_IO, &s->data_ops[1]); pci_register_bar(dev, 3, PCI_BASE_ADDRESS_SPACE_IO, &s->cmd_ops[1]); + bmdma_init_ops(s, &sii3112_bmdma_ops); + pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, &s->bmdma_ops); + /* BAR5 is in PCI memory space */ memory_region_init_io(&d->mmio, OBJECT(d), &sii3112_reg_ops, d, "sii3112.bar5", 0x200); @@ -262,10 +279,10 @@ static void sii3112_pci_realize(PCIDevice *dev, Error **errp) memory_region_init_alias(mr, OBJECT(d), "sii3112.bar3", &s->cmd_ops[1], 0, memory_region_size(&s->cmd_ops[1])); memory_region_add_subregion_overlap(&d->mmio, 0xc8, mr, 1); - mr = g_new(MemoryRegion, 1); - memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &d->mmio, 0, 16); - pci_register_bar(dev, 4, PCI_BASE_ADDRESS_SPACE_IO, mr); + memory_region_init_alias(mr, OBJECT(d), "sii3112.bar4", &s->bmdma_ops, 0, + memory_region_size(&s->bmdma_ops)); + memory_region_add_subregion_overlap(&d->mmio, 0x0, mr, 1); qdev_init_gpio_in(ds, sii3112_set_irq, 2); for (i = 0; i < 2; i++) { @@ -287,7 +304,6 @@ static void sii3112_pci_class_init(ObjectClass *klass, void *data) pd->class_id = PCI_CLASS_STORAGE_RAID; pd->revision = 1; pd->realize = sii3112_pci_realize; - pd->exit = NULL; dc->reset = sii3112_reset; dc->vmsd = NULL; dc->desc = "SiI3112A SATA controller"; diff --git a/hw/ide/trace-events b/hw/ide/trace-events index 57042cafdd..a479525e38 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -38,8 +38,10 @@ bmdma_read(uint64_t addr, uint8_t val) "bmdma: readb 0x%"PRIx64" : 0x%02x" bmdma_write(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64" : 0x%02"PRIx64 # sii3112.c -sii3112_read(int size, uint64_t addr, uint64_t val) "bmdma: read (size %d) 0x%"PRIx64" : 0x%02"PRIx64 -sii3112_write(int size, uint64_t addr, uint64_t val) "bmdma: write (size %d) 0x%"PRIx64" : 0x%02"PRIx64 +sii3112_bmdma_read(int size, uint64_t addr, uint64_t val) "read (size %d) 0x%"PRIx64" : 0x%02"PRIx64 +sii3112_bmdma_write(int size, uint64_t addr, uint64_t val) "write (size %d) 0x%"PRIx64" : 0x%02"PRIx64 +sii3112_read(int size, uint64_t addr, uint64_t val) "read (size %d) 0x%"PRIx64" : 0x%02"PRIx64 +sii3112_write(int size, uint64_t addr, uint64_t val) "write (size %d) 0x%"PRIx64" : 0x%02"PRIx64 sii3112_set_irq(int channel, int level) "channel %d level %d" # via.c From patchwork Sat Apr 22 15:07:28 2023 Content-Type: text/plain; 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[77.191.17.15]) by smtp.gmail.com with ESMTPSA id e7-20020a170906844700b0094f7b713e40sm3300108ejy.126.2023.04.22.08.07.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 22 Apr 2023 08:07:49 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-block@nongnu.org, Jiaxun Yang , BALATON Zoltan , John Snow , Huacai Chen , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-ppc@nongnu.org, Bernhard Beschow Subject: [PATCH 13/13] hw/ide: Extract bmdma_clear_status() Date: Sat, 22 Apr 2023 17:07:28 +0200 Message-Id: <20230422150728.176512-14-shentey@gmail.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230422150728.176512-1-shentey@gmail.com> References: <20230422150728.176512-1-shentey@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52c; envelope-from=shentey@gmail.com; helo=mail-ed1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Extract bmdma_clear_status() mirroring bmdma_cmd_writeb(). Signed-off-by: Bernhard Beschow --- include/hw/ide/pci.h | 1 + hw/ide/cmd646.c | 2 +- hw/ide/pci.c | 7 +++++++ hw/ide/piix.c | 2 +- hw/ide/sii3112.c | 12 +++++------- hw/ide/via.c | 2 +- hw/ide/trace-events | 1 + 7 files changed, 17 insertions(+), 10 deletions(-) diff --git a/include/hw/ide/pci.h b/include/hw/ide/pci.h index 81e0370202..6a286ad307 100644 --- a/include/hw/ide/pci.h +++ b/include/hw/ide/pci.h @@ -59,6 +59,7 @@ struct PCIIDEState { void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d); void bmdma_init_ops(PCIIDEState *d, const MemoryRegionOps *bmdma_ops); void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val); +void bmdma_clear_status(BMDMAState *bm, uint32_t val); void pci_ide_create_devs(PCIDevice *dev); #endif diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index b9d005a357..973c3ff0dc 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -144,7 +144,7 @@ static void bmdma_write(void *opaque, hwaddr addr, cmd646_update_irq(pci_dev); break; case 2: - bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); + bmdma_clear_status(bm, val); break; case 3: if (bm == &bm->pci_dev->bmdma[0]) { diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 3539b162b7..4aa06be7c6 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -318,6 +318,13 @@ void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val) bm->cmd = val & 0x09; } +void bmdma_clear_status(BMDMAState *bm, uint32_t val) +{ + trace_bmdma_update_status(val); + + bm->status = (val & 0x60) | (bm->status & BM_STATUS_DMAING) | (bm->status & ~val & 0x06); +} + static uint64_t bmdma_addr_read(void *opaque, hwaddr addr, unsigned width) { diff --git a/hw/ide/piix.c b/hw/ide/piix.c index 406a67fa0f..9eab615e35 100644 --- a/hw/ide/piix.c +++ b/hw/ide/piix.c @@ -76,7 +76,7 @@ static void bmdma_write(void *opaque, hwaddr addr, bmdma_cmd_writeb(bm, val); break; case 2: - bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); + bmdma_clear_status(bm, val); break; } } diff --git a/hw/ide/sii3112.c b/hw/ide/sii3112.c index 373c0dd1ee..1180ff55e7 100644 --- a/hw/ide/sii3112.c +++ b/hw/ide/sii3112.c @@ -66,7 +66,7 @@ static void sii3112_bmdma_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size) { BMDMAState *bm = opaque; - SiI3112PCIState *d = SII3112_PCI(bm->pci_dev); + SiI3112PCIState *s = SII3112_PCI(bm->pci_dev); int i = (bm == &bm->pci_dev->bmdma[0]) ? 0 : 1; trace_sii3112_bmdma_write(size, addr, val); @@ -75,10 +75,10 @@ static void sii3112_bmdma_write(void *opaque, hwaddr addr, bmdma_cmd_writeb(bm, val); break; case 0x01: - d->regs[i].swdata = val & 0x3f; + s->regs[i].swdata = val & 0x3f; break; case 0x02: - bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 6); + bmdma_clear_status(bm, val); break; default: break; @@ -160,8 +160,7 @@ static void sii3112_reg_write(void *opaque, hwaddr addr, d->regs[0].swdata = val & 0x3f; break; case 0x12: - d->i.bmdma[0].status = (val & 0x60) | (d->i.bmdma[0].status & 1) | - (d->i.bmdma[0].status & ~val & 6); + bmdma_clear_status(&d->i.bmdma[0], val); break; case 0x18: bmdma_cmd_writeb(&d->i.bmdma[1], val); @@ -170,8 +169,7 @@ static void sii3112_reg_write(void *opaque, hwaddr addr, d->regs[1].swdata = val & 0x3f; break; case 0x1a: - d->i.bmdma[1].status = (val & 0x60) | (d->i.bmdma[1].status & 1) | - (d->i.bmdma[1].status & ~val & 6); + bmdma_clear_status(&d->i.bmdma[1], val); break; case 0x100: d->regs[0].scontrol = val & 0xfff; diff --git a/hw/ide/via.c b/hw/ide/via.c index 35dd97e49b..afb97f302a 100644 --- a/hw/ide/via.c +++ b/hw/ide/via.c @@ -75,7 +75,7 @@ static void bmdma_write(void *opaque, hwaddr addr, bmdma_cmd_writeb(bm, val); break; case 2: - bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06); + bmdma_clear_status(bm, val); break; default:; } diff --git a/hw/ide/trace-events b/hw/ide/trace-events index a479525e38..d219c64b61 100644 --- a/hw/ide/trace-events +++ b/hw/ide/trace-events @@ -30,6 +30,7 @@ bmdma_write_cmd646(uint64_t addr, uint64_t val) "bmdma: writeb 0x%"PRIx64" : 0x% # pci.c bmdma_reset(void) "" bmdma_cmd_writeb(uint32_t val) "val: 0x%08x" +bmdma_update_status(uint32_t val) "val: 0x%08x" bmdma_addr_read(uint64_t data) "data: 0x%016"PRIx64 bmdma_addr_write(uint64_t data) "data: 0x%016"PRIx64