From patchwork Mon Apr 24 09:07:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13221858 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 569A1C7618E for ; Mon, 24 Apr 2023 09:07:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231274AbjDXJHg (ORCPT ); Mon, 24 Apr 2023 05:07:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46812 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231394AbjDXJHe (ORCPT ); Mon, 24 Apr 2023 05:07:34 -0400 Received: from mail-pg1-x530.google.com (mail-pg1-x530.google.com [IPv6:2607:f8b0:4864:20::530]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1B33E79 for ; Mon, 24 Apr 2023 02:07:32 -0700 (PDT) Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-51f597c975fso4457383a12.0 for ; Mon, 24 Apr 2023 02:07:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682327252; x=1684919252; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=5z/8lGR1AkQIcHq/8iqR9nQgXil5d7VQ8a2hbIgNp0E=; b=fDfm2ZTFk1o8gSk8alCzqUgJwDAVAv2wdNYqSiaJ+7votKR76jVnlbsXLQtgLx9EHn kzR7hYACAbNCXwemqwPWuUr6uCpHmTur+PiamI+wxb0ymmRzsESVmD7kRSpEK82zpiWD nIUcThnq+xeMOFt0QKX/KVdNbhVPMxXDl8FEJFmWMNuXR2ldmEBW+sWUkYGXBHoKBllj XfB1JH/aFTa0bAOQDC+z+IIvK7gjCUWCr+YZUO7ywf5sXoQC3zcFxBW5KpbavpvubAEc bBxqloGOoHupMMYC7ARkIgQIS4j7/aS20RLxh9eYXkEZXkPuZcJZF1zlOZFyWgAiI7qn yttg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682327252; x=1684919252; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5z/8lGR1AkQIcHq/8iqR9nQgXil5d7VQ8a2hbIgNp0E=; b=c+9z3xD5XRtqGYV+63OOZ0Nz9ZLLKnkeRVlMcglXDBkwnas/o0xTFTIQAw5dZhJyjO fGJqz/AB/j1GSIeRKlIAw5cmVOcawak9oC0FugZKKd14uTUtMLnAsxvfXfYjFRCc+dEs K5VyY7Zp4s7RKeqSLoEnuOVI7QoqDt6p4SBF9Rkoz2Jgt6EM/MQ4rlDvaugYlol+OULc /IHK4zyrEIi89KogVuOa+XiW8NKV8yhi8ZB9GApK2Uhl1lNkcmq9UZi2Ph7zkvJyt2My pwLaasmzRu3IM8WQTKgdRA6u4z4nAXm6ywEo0I6vv2hhikPgzsdp0dC9ESmLC5udOXrL iJCA== X-Gm-Message-State: AAQBX9eJRbJdjZN6Xo/ZdXjgqqD6NcqnrroZvCFloHQYKP/s3CsXi4LW Bg2K+3iyz/6SCb/eVkjvvVuhZw== X-Google-Smtp-Source: AKy350az9guWfDiaJa9jsO+Oh2dtSwmH48lLWeKBR5zQJpQdM0tMgNFkLexzfrSCyCLpKEk42BfStw== X-Received: by 2002:a17:903:245:b0:1a5:f9b:27bd with SMTP id j5-20020a170903024500b001a50f9b27bdmr15188504plh.34.1682327252143; Mon, 24 Apr 2023 02:07:32 -0700 (PDT) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jf2-20020a170903268200b001a207906418sm6234820plb.23.2023.04.24.02.07.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 02:07:31 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, Yong-Xuan Wang , "Michael S. Tsirkin" , Cornelia Huck , Paolo Bonzini , Palmer Dabbelt , Alistair Francis , Bin Meng , Thomas Huth , Chenyi Qiang , Alex Williamson , kvm@vger.kernel.org Subject: [PATCH 1/6] update-linux-headers: sync-up header with Linux for KVM AIA support Date: Mon, 24 Apr 2023 09:07:03 +0000 Message-Id: <20230424090716.15674-2-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230424090716.15674-1-yongxuan.wang@sifive.com> References: <20230424090716.15674-1-yongxuan.wang@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Sync-up Linux header to get latest KVM RISC-V headers having AIA support. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- linux-headers/linux/kvm.h | 2 ++ target/riscv/kvm_riscv.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index ebdafa576d..316732a617 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1426,6 +1426,8 @@ enum kvm_device_type { #define KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_XIVE KVM_DEV_TYPE_ARM_PV_TIME, #define KVM_DEV_TYPE_ARM_PV_TIME KVM_DEV_TYPE_ARM_PV_TIME + KVM_DEV_TYPE_RISCV_AIA, +#define KVM_DEV_TYPE_RISCV_AIA KVM_DEV_TYPE_RISCV_AIA KVM_DEV_TYPE_MAX, }; diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index ed281bdce0..606968a4b7 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -22,4 +22,37 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); +#define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 +#define KVM_DEV_RISCV_AIA_CONFIG_MODE 0 +#define KVM_DEV_RISCV_AIA_CONFIG_IDS 1 +#define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2 +#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3 +#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4 +#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5 +#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6 +#define KVM_DEV_RISCV_AIA_MODE_EMUL 0 +#define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1 +#define KVM_DEV_RISCV_AIA_MODE_AUTO 2 +#define KVM_DEV_RISCV_AIA_IDS_MIN 63 +#define KVM_DEV_RISCV_AIA_IDS_MAX 2048 +#define KVM_DEV_RISCV_AIA_SRCS_MAX 1024 +#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8 +#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24 +#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56 +#define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16 +#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8 + +#define KVM_DEV_RISCV_AIA_GRP_ADDR 1 +#define KVM_DEV_RISCV_AIA_ADDR_APLIC 0 +#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu)) +#define KVM_DEV_RISCV_AIA_ADDR_MAX \ + (1 + KVM_DEV_RISCV_APLIC_MAX_HARTS) + +#define KVM_DEV_RISCV_AIA_GRP_CTRL 2 +#define KVM_DEV_RISCV_AIA_CTRL_INIT 0 + +#define KVM_DEV_RISCV_AIA_GRP_APLIC 3 + +#define KVM_DEV_RISCV_AIA_GRP_IMSIC 4 + #endif From patchwork Mon Apr 24 09:07:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13221859 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C68DC7618E for ; Mon, 24 Apr 2023 09:07:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231472AbjDXJHt (ORCPT ); Mon, 24 Apr 2023 05:07:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46990 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231402AbjDXJHr (ORCPT ); Mon, 24 Apr 2023 05:07:47 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2B11410F0 for ; Mon, 24 Apr 2023 02:07:41 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1a6762fd23cso36796805ad.3 for ; Mon, 24 Apr 2023 02:07:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682327260; x=1684919260; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=Fua0B/nbmKUJP9K04TOuYhl26KH1ZTyjvPcnsj/T2bE=; b=k7EoDrjMFvWCasc6+7i/ZJAEukqdW68vCJFzSTMnXxSdO3useorqP56qd63TTfYkf5 geY0pVq2k+aw+XUGk978QNA4fTpJDrMpvbHClMxamDSCWt5+Jy/FHO9rUaCG2JnyUtyw LocLBJezivMbnF7V6KrOSoO2qAMEUQ1v+jeRlXIqgqCF+j0IGAhlONKkpt+/LwLHtMpr bJs3pngJo8lOiIVuZ9xTeP6lH2xawBfW2mbDNEf+GnjxmFTaPCnutT9zoK8WNIUA9dGa cR41Slzq78Ohn+jMeYgr4ZVgplRoZhz/2ryiK5U4Ireutdtfr5w9B2vDp2nIBWCtE2Uo 827A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682327260; x=1684919260; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=Fua0B/nbmKUJP9K04TOuYhl26KH1ZTyjvPcnsj/T2bE=; b=RF3nqz5ELqRPzlBfhGYOj9g4ZHyb2dPWZRIKu0Z28QKexYa2lQU03lV1SESVVyhF/w e4+4PeUELWy6W3t8c7S3r32jFPLP57GXCBad+qwK2sngLeq5oOsrT0fK1f4/IIYD3tRv Tt1C86iHblrvCvLCF+3KQUGrxOqPaSns7T2DEmmqbhMF2ikblEkYkAUxEbMwoEpUTAo1 ierWVqAUtmIPOfOBkQnC0NwCWmfxuEipUIuq9iOwpqmJPIHR8ER7IEQklvazXz/yLO8b QMgvMAeheKd0t6M/H4+ICgKc05S5XLeHC9Eo13L+KVBPGgPRdtWLIXKufV3hGTaWgIum pPfQ== X-Gm-Message-State: AAQBX9eIiNZ5c1MD+Zm9V+Xe0DWC+vq/8rV/sGKyineDOG3VcdFyEg1l AHUK36d3iM6/60pp/8nj7LYFrQ== X-Google-Smtp-Source: AKy350Y0kVgXK6MzgqOE+iENhZhpis8rzzeUu2s5kgPtN4XeCpSsdsoSS99vmnY0iNRjzTZaFcPT9Q== X-Received: by 2002:a17:902:ec86:b0:1a9:5674:282e with SMTP id x6-20020a170902ec8600b001a95674282emr10310838plg.14.1682327260677; Mon, 24 Apr 2023 02:07:40 -0700 (PDT) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jf2-20020a170903268200b001a207906418sm6234820plb.23.2023.04.24.02.07.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 02:07:40 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Paolo Bonzini , kvm@vger.kernel.org Subject: [PATCH 3/6] target/riscv: check the in-kernel irqchip support Date: Mon, 24 Apr 2023 09:07:05 +0000 Message-Id: <20230424090716.15674-4-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230424090716.15674-1-yongxuan.wang@sifive.com> References: <20230424090716.15674-1-yongxuan.wang@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org We check the in-kernel irqchip support when using KVM acceleration. Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 30f21453d6..6aad25bbc3 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -433,7 +433,18 @@ int kvm_arch_init(MachineState *ms, KVMState *s) int kvm_arch_irqchip_create(KVMState *s) { - return 0; + if (kvm_kernel_irqchip_split()) { + error_report("-machine kernel_irqchip=split is not supported " + "on RISC-V."); + exit(1); + } + + /* + * If we can create the VAIA using the newer device control API, we + * let the device do this when it initializes itself, otherwise we + * fall back to the old API + */ + return kvm_check_extension(s, KVM_CAP_DEVICE_CTRL); } int kvm_arch_process_async_events(CPUState *cs) From patchwork Mon Apr 24 09:07:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yong-Xuan Wang X-Patchwork-Id: 13221860 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4A753C7618E for ; Mon, 24 Apr 2023 09:07:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231558AbjDXJH4 (ORCPT ); Mon, 24 Apr 2023 05:07:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231402AbjDXJHv (ORCPT ); Mon, 24 Apr 2023 05:07:51 -0400 Received: from mail-pg1-x52b.google.com (mail-pg1-x52b.google.com [IPv6:2607:f8b0:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C59E9210C for ; Mon, 24 Apr 2023 02:07:46 -0700 (PDT) Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-518d325b8a2so4379188a12.0 for ; Mon, 24 Apr 2023 02:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; t=1682327266; x=1684919266; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=zCTpZ9cYwennHW314QharwHociieKqS09SCoYz2Uc9c=; b=PKuQmahPDHia3TjZrCVAWuNT1ruY1srIGXlysgjFADbLQTbqOTzxr7gXRZY7dC+VM0 c+vi4s0nf1voHMy8JH6d6vYQz3ynjxZKUdrBXBRpZg5wL89afiS9Sxi2d2Pd/xcg2W33 xafyt+HnZqHQ7gSLRoEPbnov1OSH9/ZawWGg1H25hjyUK/m8WSqbuu3qSehZz3vL+55N VodhHUFTUwbcYbNedvODjy7m+40Als1d1nEWeELdLwvXtituhVp7gqIiFuXRVvdrpHK/ kSAFFFiKUtEI8aVKTOz7otkrwMjRQIF3LXU7kmLVK+5rpUkqKwkEINKLFT5GUgl9ALAT d6bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682327266; x=1684919266; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=zCTpZ9cYwennHW314QharwHociieKqS09SCoYz2Uc9c=; b=V5ORW0P0bBh/iGuYLZyiMVLNWkG1zezyORJ88Of4AjMlpgvGxjh/GVF/0hI0DG92AU BK2q2eeoSY48FlWmyi7Ro+qeB4yFrTGWokLWu5H5G8DyM6YUslwfjBDIkijRHp/56UMu dZ/SxEAfaQcSjJw2U5H8iyrq65E9gxVQB+Hf9kKV/rjRoSey98t1pE3d/dZmwFQCKbYs fw1iG1YvbYEfZHGUzxdXpDQEhuZAtApi2iNWIvCPFSalxWGQp8aP02qmguADtNNm2Rh7 oRKAxyUSD68i91vLAmO4gEFsg892nO2xoxUELRfOJPEl0QSIph8k6tkz5BxdoORAkv8A 3RoQ== X-Gm-Message-State: AAQBX9fTZKO3sH42wMqbx0EaZAKaNuPu7p0H1eBtfkPHDFCluLjED9nR zW9CmtdUahd34+7B18YOde8x4Q== X-Google-Smtp-Source: AKy350blO8lqsu+SA6uqnm+u1bPUNrWuOOKNE2c9gsgbqxocJntSV9P99fbdIJLwihPGn6GRnWPCag== X-Received: by 2002:a17:902:dad1:b0:1a6:d15f:3ce1 with SMTP id q17-20020a170902dad100b001a6d15f3ce1mr16907842plx.34.1682327265978; Mon, 24 Apr 2023 02:07:45 -0700 (PDT) Received: from hsinchu25.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id jf2-20020a170903268200b001a207906418sm6234820plb.23.2023.04.24.02.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 24 Apr 2023 02:07:45 -0700 (PDT) From: Yong-Xuan Wang To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: rkanwal@rivosinc.com, anup@brainfault.org, dbarboza@ventanamicro.com, atishp@atishpatra.org, vincent.chen@sifive.com, greentime.hu@sifive.com, frank.chang@sifive.com, Yong-Xuan Wang , Palmer Dabbelt , Alistair Francis , Bin Meng , Paolo Bonzini , kvm@vger.kernel.org Subject: [PATCH 4/6] target/riscv: Create an KVM AIA irqchip Date: Mon, 24 Apr 2023 09:07:06 +0000 Message-Id: <20230424090716.15674-5-yongxuan.wang@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230424090716.15674-1-yongxuan.wang@sifive.com> References: <20230424090716.15674-1-yongxuan.wang@sifive.com> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org implement a function to create an KVM AIA chip Signed-off-by: Yong-Xuan Wang Reviewed-by: Jim Shu --- target/riscv/kvm.c | 83 ++++++++++++++++++++++++++++++++++++++++ target/riscv/kvm_riscv.h | 3 ++ 2 files changed, 86 insertions(+) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 6aad25bbc3..1c21f5a180 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -34,6 +34,7 @@ #include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/irq.h" +#include "hw/intc/riscv_imsic.h" #include "qemu/log.h" #include "hw/loader.h" #include "kvm_riscv.h" @@ -547,3 +548,85 @@ bool kvm_arch_cpu_check_are_resettable(void) void kvm_arch_accel_class_init(ObjectClass *oc) { } + +void kvm_riscv_aia_create(DeviceState *aplic_s, bool msimode, int socket, + uint64_t aia_irq_num, uint64_t hart_count, + uint64_t aplic_base, uint64_t imsic_base) +{ + int ret; + int aia_fd = -1; + uint64_t aia_mode; + uint64_t aia_nr_ids; + uint64_t aia_hart_bits = find_last_bit(&hart_count, BITS_PER_LONG) + 1; + + if (!msimode) { + error_report("Currently KVM AIA only supports aplic_imsic mode"); + exit(1); + } + + aia_fd = kvm_create_device(kvm_state, KVM_DEV_TYPE_RISCV_AIA, false); + + if (aia_fd < 0) { + error_report("Unable to create in-kernel irqchip"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_MODE, + &aia_mode, false, NULL); + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_IDS, + &aia_nr_ids, false, NULL); + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_SRCS, + &aia_irq_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: fail to set number input irq lines"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_HART_BITS, + &aia_hart_bits, true, NULL); + if (ret < 0) { + error_report("KVM AIA: fail to set number of harts"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_APLIC, + &aplic_base, true, NULL); + if (ret < 0) { + error_report("KVM AIA: fail to set the base address of APLIC"); + exit(1); + } + + for (int i = 0; i < hart_count; i++) { + uint64_t imsic_addr = imsic_base + i * IMSIC_HART_SIZE(0); + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_IMSIC(i), + &imsic_addr, true, NULL); + if (ret < 0) { + error_report("KVM AIA: fail to set the base address of IMSICs"); + exit(1); + } + } + + if (kvm_has_gsi_routing()) { + for (uint64_t idx = 0; idx < aia_irq_num + 1; ++idx) { + kvm_irqchip_add_irq_route(kvm_state, idx, socket, idx); + } + kvm_gsi_routing_allowed = true; + kvm_irqchip_commit_routes(kvm_state); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CTRL, + KVM_DEV_RISCV_AIA_CTRL_INIT, + NULL, true, NULL); + if (ret < 0) { + error_report("KVM AIA: initialized fail"); + exit(1); + } +} diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index 606968a4b7..6067adff51 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -21,6 +21,9 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu); void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); +void kvm_riscv_aia_create(DeviceState *aplic_s, bool msimode, int socket, + uint64_t aia_irq_num, uint64_t hart_count, + uint64_t aplic_base, uint64_t imsic_base); #define KVM_DEV_RISCV_AIA_GRP_CONFIG 0 #define KVM_DEV_RISCV_AIA_CONFIG_MODE 0