From patchwork Mon Apr 24 14:47:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harsh Prateek Bora X-Patchwork-Id: 13222262 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EB31FC77B61 for ; Mon, 24 Apr 2023 14:49:04 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqxTl-0006dw-9i; Mon, 24 Apr 2023 10:47:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqxTj-0006dM-Dl; Mon, 24 Apr 2023 10:47:43 -0400 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pqxTh-0008Sk-Mp; Mon, 24 Apr 2023 10:47:43 -0400 Received: from pps.filterd (m0353728.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 33OEiuZX009960; Mon, 24 Apr 2023 14:47:39 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding; s=pp1; bh=1rtnKa9ocZEMLYzritdpolZnQ+UtK6/jtCxvwaZ6/hk=; b=LRolTzaL9/oiin2Nb+79qEXNr3FaW3hgv8zo4+iFK3b4VnLtEg7966Vie4+aYFSb9Y6p OHAVvJIm8m4wPqcP6cyQY2hRN6zcKNUENqiXrnjPcUFGEcRMBGieINyzn/UBW6UGfvlK G5xWKKRJBfSeTM5vm/SUEYiRyoMFPqKF6RhGQcAJop6Y6hPFk8iBJuGS52WJxmqIHKg8 Tcd4rdeL2mXZm5mRHSzYiVxjOrcOTdQC7g3nxFmYTPEBP5pVtv2cHdC8P40ifNqSWbXy qDw7CDNsNF/NX9oYA/aR56cV36qUPJpO6AGd3Xw1HDFpLBFRJzWwoBPLW1mNKxatXUVJ ZQ== Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3q46m63tve-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Apr 2023 14:47:39 +0000 Received: from m0353728.ppops.net (m0353728.ppops.net [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 33OEbFxm015725; Mon, 24 Apr 2023 14:47:38 GMT Received: from ppma04fra.de.ibm.com (6a.4a.5195.ip4.static.sl-reverse.com [149.81.74.106]) by mx0a-001b2d01.pphosted.com (PPS) with ESMTPS id 3q46m63tsr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Apr 2023 14:47:38 +0000 Received: from pps.filterd (ppma04fra.de.ibm.com [127.0.0.1]) by ppma04fra.de.ibm.com (8.17.1.19/8.17.1.19) with ESMTP id 33OEcCTm004691; Mon, 24 Apr 2023 14:47:34 GMT Received: from smtprelay07.fra02v.mail.ibm.com ([9.218.2.229]) by ppma04fra.de.ibm.com (PPS) with ESMTPS id 3q47770yt6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 24 Apr 2023 14:47:34 +0000 Received: from smtpav02.fra02v.mail.ibm.com (smtpav02.fra02v.mail.ibm.com [10.20.54.101]) by smtprelay07.fra02v.mail.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 33OElVBs29557192 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 24 Apr 2023 14:47:31 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BFE9920043; Mon, 24 Apr 2023 14:47:31 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BC63F20040; Mon, 24 Apr 2023 14:47:29 +0000 (GMT) Received: from li-1901474c-32f3-11b2-a85c-fc5ff2c001f3.ibm.com.com (unknown [9.43.92.123]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 24 Apr 2023 14:47:29 +0000 (GMT) From: Harsh Prateek Bora To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, farosas@suse.de, npiggin@gmail.com, danielhb413@gmail.com Subject: [PATCH v2 1/4] ppc: spapr: cleanup cr get/store in [h_enter|spapr_exit]_nested with helpers. Date: Mon, 24 Apr 2023 20:17:09 +0530 Message-Id: <20230424144712.1985425-2-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230424144712.1985425-1-harshpb@linux.ibm.com> References: <20230424144712.1985425-1-harshpb@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: k-qhqtoEpBjpdza7QVcQSRYYyPPcriwv X-Proofpoint-GUID: qu1FRDgS7dhOkFYL98Z03yP3EdInXo3K X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-24_09,2023-04-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=951 priorityscore=1501 mlxscore=0 spamscore=0 adultscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 impostorscore=0 phishscore=0 bulkscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304240131 Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org The bits in cr reg are grouped into eight 4-bit fields represented by env->crf[8] and the related calculations should be abstracted to keep the calling routines simpler to read. This is a step towards cleaning up the [h_enter|spapr_exit]_nested calls for better readability. Signed-off-by: Harsh Prateek Bora Reviewed-by: Fabiano Rosas --- hw/ppc/spapr_hcall.c | 18 ++---------------- target/ppc/cpu.c | 17 +++++++++++++++++ target/ppc/cpu.h | 2 ++ 3 files changed, 21 insertions(+), 16 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index ec4def62f8..124cee5e53 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1566,8 +1566,6 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, struct kvmppc_hv_guest_state hv_state; struct kvmppc_pt_regs *regs; hwaddr len; - uint64_t cr; - int i; if (spapr->nested_ptcr == 0) { return H_NOT_AVAILABLE; @@ -1616,12 +1614,7 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, env->lr = regs->link; env->ctr = regs->ctr; cpu_write_xer(env, regs->xer); - - cr = regs->ccr; - for (i = 7; i >= 0; i--) { - env->crf[i] = cr & 15; - cr >>= 4; - } + ppc_store_cr(env, regs->ccr); env->msr = regs->msr; env->nip = regs->nip; @@ -1698,8 +1691,6 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) struct kvmppc_hv_guest_state *hvstate; struct kvmppc_pt_regs *regs; hwaddr len; - uint64_t cr; - int i; assert(spapr_cpu->in_nested); @@ -1757,12 +1748,7 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) regs->link = env->lr; regs->ctr = env->ctr; regs->xer = cpu_read_xer(env); - - cr = 0; - for (i = 0; i < 8; i++) { - cr |= (env->crf[i] & 15) << (4 * (7 - i)); - } - regs->ccr = cr; + regs->ccr = ppc_get_cr(env); if (excp == POWERPC_EXCP_MCHECK || excp == POWERPC_EXCP_RESET || diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 1a97b41c6b..3b444e58b5 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -67,6 +67,23 @@ uint32_t ppc_get_vscr(CPUPPCState *env) return env->vscr | (sat << VSCR_SAT); } +void ppc_store_cr(CPUPPCState *env, uint64_t cr) +{ + for (int i = 7; i >= 0; i--) { + env->crf[i] = cr & 15; + cr >>= 4; + } +} + +uint64_t ppc_get_cr(CPUPPCState *env) +{ + uint64_t cr = 0; + for (int i = 0; i < 8; i++) { + cr |= (env->crf[i] & 15) << (4 * (7 - i)); + } + return cr; +} + /* GDBstub can read and write MSR... */ void ppc_store_msr(CPUPPCState *env, target_ulong value) { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 557d736dab..b4c21459f1 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2773,6 +2773,8 @@ void dump_mmu(CPUPPCState *env); void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len); void ppc_store_vscr(CPUPPCState *env, uint32_t vscr); uint32_t ppc_get_vscr(CPUPPCState *env); +void ppc_store_cr(CPUPPCState *env, uint64_t cr); +uint64_t ppc_get_cr(CPUPPCState *env); /*****************************************************************************/ /* Power management enable checks */ From patchwork Mon Apr 24 14:47:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harsh Prateek Bora X-Patchwork-Id: 13222263 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21B77C7618E for ; Mon, 24 Apr 2023 14:49:07 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pqxTl-0006e2-CH; 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Mon, 24 Apr 2023 14:47:34 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 446AE20040; Mon, 24 Apr 2023 14:47:34 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 43FE02004B; Mon, 24 Apr 2023 14:47:32 +0000 (GMT) Received: from li-1901474c-32f3-11b2-a85c-fc5ff2c001f3.ibm.com.com (unknown [9.43.92.123]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 24 Apr 2023 14:47:31 +0000 (GMT) From: Harsh Prateek Bora To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, farosas@suse.de, npiggin@gmail.com, danielhb413@gmail.com Subject: [PATCH v2 2/4] ppc: spapr: cleanup h_enter_nested() with helper routines. Date: Mon, 24 Apr 2023 20:17:10 +0530 Message-Id: <20230424144712.1985425-3-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230424144712.1985425-1-harshpb@linux.ibm.com> References: <20230424144712.1985425-1-harshpb@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: q-ukusMDnA9xM0e0d6gZvvSJ5Zx1cCQ5 X-Proofpoint-GUID: dB7Cv4pFn3Dv0hm5INCedk7tjJ85KDbs X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-24_09,2023-04-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 priorityscore=1501 adultscore=0 suspectscore=0 lowpriorityscore=0 phishscore=0 bulkscore=0 mlxscore=0 spamscore=0 mlxlogscore=881 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304240131 Received-SPF: pass client-ip=148.163.156.1; envelope-from=harshpb@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org h_enter_nested() currently does a lot of register specific operations which should be abstracted logically to simplify the code for better readability. This patch breaks down relevant blocks into respective helper routines to make use of them for better readability/maintenance. Signed-off-by: Harsh Prateek Bora --- hw/ppc/spapr_hcall.c | 117 ++++++++++++++++++++++++++++--------------- 1 file changed, 78 insertions(+), 39 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 124cee5e53..f24d4b368e 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1544,6 +1544,81 @@ static target_ulong h_copy_tofrom_guest(PowerPCCPU *cpu, return H_FUNCTION; } +static void restore_hdec_from_hvstate(CPUPPCState *dst, + struct kvmppc_hv_guest_state *hv_state, + target_ulong now) +{ + target_ulong hdec; + + assert(hv_state); + hdec = hv_state->hdec_expiry - now; + cpu_ppc_hdecr_init(dst); + cpu_ppc_store_hdecr(dst, hdec); +} + +static void restore_lpcr_from_hvstate(PowerPCCPU *cpu, + struct kvmppc_hv_guest_state *hv_state) +{ + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + CPUPPCState *dst = &cpu->env; + target_ulong lpcr, lpcr_mask; + + assert(hv_state); + lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; + lpcr = (dst->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state->lpcr & lpcr_mask); + lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; + lpcr &= ~LPCR_LPES0; + dst->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask; +} + +static void restore_env_from_ptregs(CPUPPCState *env, + struct kvmppc_pt_regs *regs) +{ + assert(env); + assert(regs); + assert(sizeof(env->gpr) == sizeof(regs->gpr)); + memcpy(env->gpr, regs->gpr, sizeof(env->gpr)); + env->nip = regs->nip; + env->msr = regs->msr; + env->lr = regs->link; + env->ctr = regs->ctr; + cpu_write_xer(env, regs->xer); + ppc_store_cr(env, regs->ccr); +} + +static void restore_env_from_hvstate(CPUPPCState *env, + struct kvmppc_hv_guest_state *hv_state) +{ + assert(env); + assert(hv_state); + env->spr[SPR_HFSCR] = hv_state->hfscr; + /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/ + env->cfar = hv_state->cfar; + env->spr[SPR_PCR] = hv_state->pcr; + env->spr[SPR_DPDES] = hv_state->dpdes; + env->spr[SPR_SRR0] = hv_state->srr0; + env->spr[SPR_SRR1] = hv_state->srr1; + env->spr[SPR_SPRG0] = hv_state->sprg[0]; + env->spr[SPR_SPRG1] = hv_state->sprg[1]; + env->spr[SPR_SPRG2] = hv_state->sprg[2]; + env->spr[SPR_SPRG3] = hv_state->sprg[3]; + env->spr[SPR_BOOKS_PID] = hv_state->pidr; + env->spr[SPR_PPR] = hv_state->ppr; +} + +static inline void restore_l2_env(PowerPCCPU *cpu, + struct kvmppc_hv_guest_state *hv_state, + struct kvmppc_pt_regs *regs, + target_ulong now) +{ + CPUPPCState *env = &cpu->env; + + restore_env_from_ptregs(env, regs); + restore_env_from_hvstate(env, hv_state); + restore_lpcr_from_hvstate(cpu, hv_state); + restore_hdec_from_hvstate(env, hv_state, now); +} + /* * When this handler returns, the environment is switched to the L2 guest * and TCG begins running that. spapr_exit_nested() performs the switch from @@ -1554,14 +1629,12 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, target_ulong opcode, target_ulong *args) { - PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); target_ulong hv_ptr = args[0]; target_ulong regs_ptr = args[1]; - target_ulong hdec, now = cpu_ppc_load_tbl(env); - target_ulong lpcr, lpcr_mask; + target_ulong now = cpu_ppc_load_tbl(env); struct kvmppc_hv_guest_state *hvstate; struct kvmppc_hv_guest_state hv_state; struct kvmppc_pt_regs *regs; @@ -1607,49 +1680,15 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, return H_P2; } - len = sizeof(env->gpr); - assert(len == sizeof(regs->gpr)); - memcpy(env->gpr, regs->gpr, len); - - env->lr = regs->link; - env->ctr = regs->ctr; - cpu_write_xer(env, regs->xer); - ppc_store_cr(env, regs->ccr); - - env->msr = regs->msr; - env->nip = regs->nip; + /* restore L2 env from hv_state and ptregs */ + restore_l2_env(cpu, &hv_state, regs, now); address_space_unmap(CPU(cpu)->as, regs, len, len, false); - env->cfar = hv_state.cfar; - assert(env->spr[SPR_LPIDR] == 0); env->spr[SPR_LPIDR] = hv_state.lpid; - lpcr_mask = LPCR_DPFD | LPCR_ILE | LPCR_AIL | LPCR_LD | LPCR_MER; - lpcr = (env->spr[SPR_LPCR] & ~lpcr_mask) | (hv_state.lpcr & lpcr_mask); - lpcr |= LPCR_HR | LPCR_UPRT | LPCR_GTSE | LPCR_HVICE | LPCR_HDICE; - lpcr &= ~LPCR_LPES0; - env->spr[SPR_LPCR] = lpcr & pcc->lpcr_mask; - - env->spr[SPR_PCR] = hv_state.pcr; - /* hv_state.amor is not used */ - env->spr[SPR_DPDES] = hv_state.dpdes; - env->spr[SPR_HFSCR] = hv_state.hfscr; - hdec = hv_state.hdec_expiry - now; spapr_cpu->nested_tb_offset = hv_state.tb_offset; - /* TCG does not implement DAWR*, CIABR, PURR, SPURR, IC, VTB, HEIR SPRs*/ - env->spr[SPR_SRR0] = hv_state.srr0; - env->spr[SPR_SRR1] = hv_state.srr1; - env->spr[SPR_SPRG0] = hv_state.sprg[0]; - env->spr[SPR_SPRG1] = hv_state.sprg[1]; - env->spr[SPR_SPRG2] = hv_state.sprg[2]; - env->spr[SPR_SPRG3] = hv_state.sprg[3]; - env->spr[SPR_BOOKS_PID] = hv_state.pidr; - env->spr[SPR_PPR] = hv_state.ppr; - - cpu_ppc_hdecr_init(env); - cpu_ppc_store_hdecr(env, hdec); /* * The hv_state.vcpu_token is not needed. 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Date: Mon, 24 Apr 2023 20:17:11 +0530 Message-Id: <20230424144712.1985425-4-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230424144712.1985425-1-harshpb@linux.ibm.com> References: <20230424144712.1985425-1-harshpb@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: SA600k7atVZMc-8tfs28emFqyfPXQZez X-Proofpoint-ORIG-GUID: 7iKl-2qpDjDpcTimCcHQ8zOqWlTCfo1n X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-24_09,2023-04-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 clxscore=1015 malwarescore=0 adultscore=0 mlxlogscore=981 mlxscore=0 lowpriorityscore=0 bulkscore=0 phishscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304240131 Received-SPF: pass client-ip=148.163.158.5; envelope-from=harshpb@linux.ibm.com; helo=mx0b-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Currently, in spapr_exit_nested(), it does a lot of register state restoring from ptregs/hvstate after mapping each of those before restoring the L1 host state. This patch breaks down those set of ops to respective helper routines for better code readability/maintenance. Signed-off-by: Harsh Prateek Bora --- hw/ppc/spapr_hcall.c | 120 ++++++++++++++++++++++++++----------------- 1 file changed, 72 insertions(+), 48 deletions(-) diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index f24d4b368e..e69634bc22 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1719,45 +1719,14 @@ static target_ulong h_enter_nested(PowerPCCPU *cpu, return env->gpr[3]; } -void spapr_exit_nested(PowerPCCPU *cpu, int excp) +static void restore_hvstate_from_env(struct kvmppc_hv_guest_state *hvstate, + CPUPPCState *env, int excp) { - CPUState *cs = CPU(cpu); - CPUPPCState *env = &cpu->env; - SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); - target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */ - target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4]; - target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5]; - struct kvmppc_hv_guest_state *hvstate; - struct kvmppc_pt_regs *regs; - hwaddr len; - - assert(spapr_cpu->in_nested); - - cpu_ppc_hdecr_exit(env); - - len = sizeof(*hvstate); - hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true, - MEMTXATTRS_UNSPECIFIED); - if (len != sizeof(*hvstate)) { - address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true); - r3_return = H_PARAMETER; - goto out_restore_l1; - } - hvstate->cfar = env->cfar; hvstate->lpcr = env->spr[SPR_LPCR]; hvstate->pcr = env->spr[SPR_PCR]; hvstate->dpdes = env->spr[SPR_DPDES]; hvstate->hfscr = env->spr[SPR_HFSCR]; - - if (excp == POWERPC_EXCP_HDSI) { - hvstate->hdar = env->spr[SPR_HDAR]; - hvstate->hdsisr = env->spr[SPR_HDSISR]; - hvstate->asdr = env->spr[SPR_ASDR]; - } else if (excp == POWERPC_EXCP_HISI) { - hvstate->asdr = env->spr[SPR_ASDR]; - } - /* HEIR should be implemented for HV mode and saved here. */ hvstate->srr0 = env->spr[SPR_SRR0]; hvstate->srr1 = env->spr[SPR_SRR1]; @@ -1768,27 +1737,43 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) hvstate->pidr = env->spr[SPR_BOOKS_PID]; hvstate->ppr = env->spr[SPR_PPR]; - /* Is it okay to specify write length larger than actual data written? */ - address_space_unmap(CPU(cpu)->as, hvstate, len, len, true); + if (excp == POWERPC_EXCP_HDSI) { + hvstate->hdar = env->spr[SPR_HDAR]; + hvstate->hdsisr = env->spr[SPR_HDSISR]; + hvstate->asdr = env->spr[SPR_ASDR]; + } else if (excp == POWERPC_EXCP_HISI) { + hvstate->asdr = env->spr[SPR_ASDR]; + } +} - len = sizeof(*regs); - regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true, +static int map_and_restore_l2_hvstate(PowerPCCPU *cpu, int excp, target_ulong *r3) +{ + CPUPPCState *env = &cpu->env; + SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); + target_ulong hv_ptr = spapr_cpu->nested_host_state->gpr[4]; + struct kvmppc_hv_guest_state *hvstate; + hwaddr len = sizeof(*hvstate); + + hvstate = address_space_map(CPU(cpu)->as, hv_ptr, &len, true, MEMTXATTRS_UNSPECIFIED); - if (!regs || len != sizeof(*regs)) { - address_space_unmap(CPU(cpu)->as, regs, len, 0, true); - r3_return = H_P2; - goto out_restore_l1; + if (len != sizeof(*hvstate)) { + address_space_unmap(CPU(cpu)->as, hvstate, len, 0, true); + *r3 = H_PARAMETER; + return -1; } + restore_hvstate_from_env(hvstate, env, excp); + /* Is it okay to specify write length larger than actual data written? */ + address_space_unmap(CPU(cpu)->as, hvstate, len, len, true); + return 0; +} +static void restore_ptregs_from_env(struct kvmppc_pt_regs *regs, + CPUPPCState *env, int excp) +{ + hwaddr len; len = sizeof(env->gpr); assert(len == sizeof(regs->gpr)); memcpy(regs->gpr, env->gpr, len); - - regs->link = env->lr; - regs->ctr = env->ctr; - regs->xer = cpu_read_xer(env); - regs->ccr = ppc_get_cr(env); - if (excp == POWERPC_EXCP_MCHECK || excp == POWERPC_EXCP_RESET || excp == POWERPC_EXCP_SYSCALL) { @@ -1798,11 +1783,50 @@ void spapr_exit_nested(PowerPCCPU *cpu, int excp) regs->nip = env->spr[SPR_HSRR0]; regs->msr = env->spr[SPR_HSRR1] & env->msr_mask; } + regs->link = env->lr; + regs->ctr = env->ctr; + regs->xer = cpu_read_xer(env); + regs->ccr = ppc_get_cr(env); +} +static int map_and_restore_l2_ptregs(PowerPCCPU *cpu, int excp, target_ulong *r3) +{ + CPUPPCState *env = &cpu->env; + SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); + target_ulong regs_ptr = spapr_cpu->nested_host_state->gpr[5]; + hwaddr len; + struct kvmppc_pt_regs *regs = NULL; + + len = sizeof(*regs); + regs = address_space_map(CPU(cpu)->as, regs_ptr, &len, true, + MEMTXATTRS_UNSPECIFIED); + if (!regs || len != sizeof(*regs)) { + address_space_unmap(CPU(cpu)->as, regs, len, 0, true); + *r3 = H_P2; + return -1; + } + restore_ptregs_from_env(regs, env, excp); /* Is it okay to specify write length larger than actual data written? */ address_space_unmap(CPU(cpu)->as, regs, len, len, true); + return 0; +} + +void spapr_exit_nested(PowerPCCPU *cpu, int excp) +{ + CPUState *cs = CPU(cpu); + CPUPPCState *env = &cpu->env; + SpaprCpuState *spapr_cpu = spapr_cpu_state(cpu); + target_ulong r3_return = env->excp_vectors[excp]; /* hcall return value */ + + assert(spapr_cpu->in_nested); + + cpu_ppc_hdecr_exit(env); + + if (!map_and_restore_l2_hvstate(cpu, excp, &r3_return)) { + map_and_restore_l2_ptregs (cpu, excp, &r3_return); + } -out_restore_l1: + /* out_restore_l1 */ memcpy(env->gpr, spapr_cpu->nested_host_state->gpr, sizeof(env->gpr)); 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Mon, 24 Apr 2023 14:47:39 GMT Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 469BD2004B; Mon, 24 Apr 2023 14:47:39 +0000 (GMT) Received: from smtpav02.fra02v.mail.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4840620040; Mon, 24 Apr 2023 14:47:37 +0000 (GMT) Received: from li-1901474c-32f3-11b2-a85c-fc5ff2c001f3.ibm.com.com (unknown [9.43.92.123]) by smtpav02.fra02v.mail.ibm.com (Postfix) with ESMTP; Mon, 24 Apr 2023 14:47:37 +0000 (GMT) From: Harsh Prateek Bora To: qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, farosas@suse.de, npiggin@gmail.com, danielhb413@gmail.com Subject: [PATCH v2 4/4] MAINTAINERS: Adding myself in the list for ppc/spapr Date: Mon, 24 Apr 2023 20:17:12 +0530 Message-Id: <20230424144712.1985425-5-harshpb@linux.ibm.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20230424144712.1985425-1-harshpb@linux.ibm.com> References: <20230424144712.1985425-1-harshpb@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: i_ff8EkenOPdqEaaFxCMyvm1jdT0gjI6 X-Proofpoint-GUID: 4D-w6i83ejqIOJgpt3JtnfsLZy3_sKZP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-04-24_09,2023-04-21_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 spamscore=0 impostorscore=0 bulkscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 malwarescore=0 mlxlogscore=978 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2303200000 definitions=main-2304240131 Received-SPF: pass client-ip=148.163.156.1; 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Signed-off-by: Harsh Prateek Bora Reviewed-by: Daniel Henrique Barboza --- MAINTAINERS | 1 + 1 file changed, 1 insertion(+) diff --git a/MAINTAINERS b/MAINTAINERS index 2c2068ea5c..b5d290cf92 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1420,6 +1420,7 @@ M: Daniel Henrique Barboza R: Cédric Le Goater R: David Gibson R: Greg Kurz +R: Harsh Prateek Bora L: qemu-ppc@nongnu.org S: Odd Fixes F: hw/*/spapr*