From patchwork Tue Apr 25 08:29:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223034 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DFF2BC77B76 for ; Tue, 25 Apr 2023 08:30:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233664AbjDYIaB (ORCPT ); Tue, 25 Apr 2023 04:30:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233672AbjDYI35 (ORCPT ); Tue, 25 Apr 2023 04:29:57 -0400 Received: from mail-ej1-x62c.google.com (mail-ej1-x62c.google.com [IPv6:2a00:1450:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7624D40E0; Tue, 25 Apr 2023 01:29:56 -0700 (PDT) Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-94f7a0818aeso813914266b.2; Tue, 25 Apr 2023 01:29:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411395; x=1685003395; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LaUHbduLvT7VglteyNVg17dxlefVbbFzI2gkZnIc6Vo=; b=RNg4TxdpaoPZ75DhJpNTUsxQOiUNBEwwOvkaIQWV8Rxmv/cHH1Dc82zums7p9O3nRc vAZxcKkZn+OEy45IZctFwMls7KpJ5HjXE3g6otBXRmxU2d+0Lo3vz8aNIYKc26tjQXVy sBaB3/y8BGC2+G1lEhFDNqiHd2nk0ybFiccl6vbt8F0YP9Z0Pj42VzNzg6OOQyVxRdz9 /WsI1HJw8kHWsjgsIT3dJeQcGSqzCgNAttBIFba4LAk79cYqE3iS2my2tSCtAqg320ik pAz6D0wVmNdovtJqEpLGlpEUu7ug9cIb1mtFcy1MzC/jSsss1hYlRZkGNfpYC+mGICgV B60g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411395; x=1685003395; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LaUHbduLvT7VglteyNVg17dxlefVbbFzI2gkZnIc6Vo=; b=PwnTzRQwPQhnVKlmEiyiFEfp4wxQRsJE9+v43ewhrUdCEHgFH12bE9j56Hk9CCFnzl cughSyHVLmztdutFjsrq7lHCwCixITalEOU1Iyu/BbYrGDMlGY3bl9MB6kXqyhY/aSSD 5G4XZTqi992W9WZ14jJRFEvm8Aht6dKRR9up5lAAf0GKf5bz76TBrxP4qPbuIr/XtORs MvP4ESal5eRJIkXSA1jbcX9xjhZopcF4Yme9jY0kgcYo3pbTrE97d9FLvt4CILuWTptZ Qd1rQVW1kT7ublvXMsWpW+trt7s39GvgD9ZOwqBYdsz6VU/24QDmFXWt2nYBJTki1EBt DE6g== X-Gm-Message-State: AAQBX9emQ6swCXkUlNcxPnRfR50AuYHEGolnTDEEYFHbXQXTyPlgDFaJ odNaA/2PUN0u9bwzNkjFOs0= X-Google-Smtp-Source: AKy350Yap/bGcpQf2xq4sCbut3Oh2Si3tTlDY/j7jrRF8KfM8Fk4Vn3KlifqbJVaeCl1FeMEUphp1w== X-Received: by 2002:a17:906:300b:b0:951:756d:6542 with SMTP id 11-20020a170906300b00b00951756d6542mr13114494ejz.32.1682411394759; Tue, 25 Apr 2023 01:29:54 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.29.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:29:54 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , stable@vger.kernel.org, Bartel Eerdekens , Richard van Schagen , Richard van Schagen , Frank Wunderlich , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 01/24] net: dsa: mt7530: fix corrupt frames using trgmii on 40 MHz XTAL MT7621 Date: Tue, 25 Apr 2023 11:29:10 +0300 Message-Id: <20230425082933.84654-2-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL The multi-chip module MT7530 switch with a 40 MHz oscillator on the MT7621AT, MT7621DAT, and MT7621ST SoCs forwards corrupt frames using trgmii. This is caused by the assumption that MT7621 SoCs have got 150 MHz PLL, hence using the ncpo1 value, 0x0780. My testing shows this value works on Unielec U7621-06, Bartel's testing shows it won't work on Hi-Link HLK-MT7621A and Netgear WAC104. All devices tested have got 40 MHz oscillators. Using the value for 125 MHz PLL, 0x0640, works on all boards at hand. The definitions for 125 MHz PLL exist on the Banana Pi BPI-R2 BSP source code whilst 150 MHz PLL don't. Forwarding frames using trgmii on the MCM MT7530 switch with a 25 MHz oscillator on the said MT7621 SoCs works fine because the ncpo1 value defined for it is for 125 MHz PLL. Change the 150 MHz PLL comment to 125 MHz PLL, and use the 125 MHz PLL ncpo1 values for both oscillator frequencies. Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/81d24bbce7d99524d0771a8bdb2d6663e4eb4faa/u-boot-mt/drivers/net/rt2880_eth.c#L2195 Fixes: 7ef6f6f8d237 ("net: dsa: mt7530: Add MT7621 TRGMII mode support") Cc: stable@vger.kernel.org Tested-by: Bartel Eerdekens Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index c680873819b0..7d9f9563dbda 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -426,9 +426,9 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) else ssc_delta = 0x87; if (priv->id == ID_MT7621) { - /* PLL frequency: 150MHz: 1.2GBit */ + /* PLL frequency: 125MHz: 1.0GBit */ if (xtal == HWTRAP_XTAL_40MHZ) - ncpo1 = 0x0780; + ncpo1 = 0x0640; if (xtal == HWTRAP_XTAL_25MHZ) ncpo1 = 0x0a00; } else { /* PLL frequency: 250MHz: 2.0Gbit */ From patchwork Tue Apr 25 08:29:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223035 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34E04C77B61 for ; Tue, 25 Apr 2023 08:30:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233656AbjDYIaE (ORCPT ); Tue, 25 Apr 2023 04:30:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233678AbjDYIaA (ORCPT ); Tue, 25 Apr 2023 04:30:00 -0400 Received: from mail-ed1-x52e.google.com (mail-ed1-x52e.google.com [IPv6:2a00:1450:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD7E67EC0; Tue, 25 Apr 2023 01:29:58 -0700 (PDT) Received: by mail-ed1-x52e.google.com with SMTP id 4fb4d7f45d1cf-504dfc87927so9228919a12.0; Tue, 25 Apr 2023 01:29:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411397; x=1685003397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aAGSKJ4Dha/ZIAfZI+1H0/FLVbZeQzSqGgtEHuX/IJM=; b=cnlFX8IxXuPwTO1yT4lwjyNQCZ058C6TnRaTTsJY6HLV3NeEX49ScZCKnXjzQwLE57 /sPROHBOn+lw3cHYmXNX8qW0IerL4cuWmDi4qqWHlHnnPcXAs8iygdsfT/8UGXSpxyC4 qL7KxlQ47l9rO4gNSRgdfbUa2rZv5v9UP8pCk+GtNoCmD6+H/6P7ZfInjBmD957Kmriy PPw4JTyoqCQ29eRqXIWhj+JxVrFPDXYyEh+B01uly5avMxiCrlaZ0cI/RTZdq4ENTYLS MVGFS8JkkQ9NBUxVEeSTmUUx3JUONPmAsUNBcNWlm/Wq40yKhfuNeEMw6fnJc2ryeFhn dfaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411397; x=1685003397; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aAGSKJ4Dha/ZIAfZI+1H0/FLVbZeQzSqGgtEHuX/IJM=; b=lRNzQ/p4MyVy/OTGIqeyISpj2W13vHfs4PsWuG83JzU7D2mIGhIy0MJVntJf/Mr82g lv6tjnkXOdk4tbXi/N+USVVlrmvMxC03UOowQm84wH624WvyyFs534i3KEBSadMqzb2e 6JMO2SErd+zePzh2Gkdxvq5bJqlTu7aeufJpfwGK6jSrCAWgVRO8CceAim9GPKO1Lly7 JBUJungjCasoPaWFFwJL7vXLYLZeXvBj+zErhi0hEoM4hKRL/DYwGBxoMVxvOhWpbFAi xkKbH1uVLM9SzlkRsoUP2dxKgYPANlQ9PePtPghnrsmNfdqv3fGGAlkP8wUjYsymhjnl 98iw== X-Gm-Message-State: AAQBX9c/FzsoMhD3UXUYF8aTurXvVpr3E98IjnTXrDc/pgi9f784umor IdGmcRYArd4sVcSX9BpTE4E= X-Google-Smtp-Source: AKy350ZqTfe8+1rkKQxwz2ZUF853VV4zr2Tiiz9s/Xjtv8sk7t9V91AYeRqoxxZOBC6CKpGEx/R1Qg== X-Received: by 2002:a50:ee8c:0:b0:506:79ba:2492 with SMTP id f12-20020a50ee8c000000b0050679ba2492mr13873740edr.12.1682411397128; Tue, 25 Apr 2023 01:29:57 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.29.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:29:56 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 02/24] net: dsa: mt7530: add missing @p5_interface to mt7530_priv description Date: Tue, 25 Apr 2023 11:29:11 +0300 Message-Id: <20230425082933.84654-3-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL Add the missing p5_interface field to the mt7530_priv description. Sort out the description in the process. Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 5084f48a8869..845f5dd16d83 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -746,7 +746,8 @@ struct mt753x_info { * @ports: Holding the state among ports * @reg_mutex: The lock for protecting among process accessing * registers - * @p6_interface Holding the current port 6 interface + * @p6_interface: Holding the current port 6 interface + * @p5_interface: Holding the current port 5 interface * @p5_intf_sel: Holding the current port 5 interface select * @irq: IRQ number of the switch * @irq_domain: IRQ domain of the switch irq_chip From patchwork Tue Apr 25 08:29:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223036 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19E05C77B61 for ; Tue, 25 Apr 2023 08:30:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233653AbjDYIa0 (ORCPT ); Tue, 25 Apr 2023 04:30:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233688AbjDYIaC (ORCPT ); Tue, 25 Apr 2023 04:30:02 -0400 Received: from mail-ed1-x52b.google.com (mail-ed1-x52b.google.com [IPv6:2a00:1450:4864:20::52b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41DB97AA8; Tue, 25 Apr 2023 01:30:01 -0700 (PDT) Received: by mail-ed1-x52b.google.com with SMTP id 4fb4d7f45d1cf-5055141a8fdso7909975a12.3; Tue, 25 Apr 2023 01:30:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411400; x=1685003400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7rU2rEuh2fF/AUhiTvEQmHXWDUbju8C9sKkmr3u6JBw=; b=P/ECSuh6Fs+oMNsVuAbO7v2WqO2J8/Bs7A6vuJ7oPUFYjuhaSJXrnd6tw8ERYNodHv M4MKjb7+pE/aDSS8oa1OVS683xnnTg0sJRGEiI8ZMy2PLihmdJj6yXp4x6fmuoW3vgOP qSnVT4BHlhybLzJkfpBu2C32NqXDM9acUB2nhbNlx8/SjRa0IyQ9LsVWRHUgtbGHWUVk +Yc/M4qGMqoWP1Wr8DKjVfWzEzKXc0Eh66evGXDZ7F42OlCUzTNfKzT/7RTjMwUetU/m JatOPGsJKen2PS2Lo9I1mDQo/AtWmFYcYUXmWyiaAc7oIEMprE3PCRuaJzcV2vh24ZMl 0iOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411400; x=1685003400; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7rU2rEuh2fF/AUhiTvEQmHXWDUbju8C9sKkmr3u6JBw=; b=L7JCA9qaZVs6akFCi20QbAayaAIqieb8XyBAchsEnYycTxj3Yqrdd4naojDe16Rerj uYAvI7sSFTxsZAoK/XsBd1KZHzBe+Z1oe9AuSSPoxjNyvJbtkZSwcBuWogluYOMUa1rV 6ekwgBvZDbgo0iExO2c8XcY/cyXQYGrLc2VlXJDpCK+ZwgyPtbZ6qHDYVb5yRD9k/HYQ DvdP5uZ5iv73+aA63Aa+eX5x93OeE8uH2grN9AZp9Q3IkGDdoFNWlKyadlIPKsQrIaAW 3LsgtRxgYF4pmJfQQb3dctjBY0aS4ScJkjRPn9rm+/SPSfeUwg1mYs6qkEuBhxU2VH3e 42Ww== X-Gm-Message-State: AAQBX9edfLzM6w5oSYkE/I5wbmEq7hDvaLEmNfQVaipL9at66MiKeE3E Zp73OBFiAAaK5rOkRu8YraQ= X-Google-Smtp-Source: AKy350bkcOtAPqPEVvCIw4dBxIjTwoE4qSLUO9+d/iejSLnws3XSgdmdmMCOCq8NCWekbY1afU7U0A== X-Received: by 2002:aa7:de11:0:b0:506:b209:edb with SMTP id h17-20020aa7de11000000b00506b2090edbmr12731369edv.38.1682411399523; Tue, 25 Apr 2023 01:29:59 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.29.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:29:59 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 03/24] net: dsa: mt7530: use p5_interface_select as data type for p5_intf_sel Date: Tue, 25 Apr 2023 11:29:12 +0300 Message-Id: <20230425082933.84654-4-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL Use the p5_interface_select enumeration as the data type for the p5_intf_sel field. This ensures p5_intf_sel can only take the values defined in the p5_interface_select enumeration. Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 845f5dd16d83..415d8ea07472 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -675,7 +675,7 @@ struct mt7530_port { /* Port 5 interface select definitions */ enum p5_interface_select { - P5_DISABLED = 0, + P5_DISABLED, P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, @@ -768,7 +768,7 @@ struct mt7530_priv { bool mcm; phy_interface_t p6_interface; phy_interface_t p5_interface; - unsigned int p5_intf_sel; + enum p5_interface_select p5_intf_sel; u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; From patchwork Tue Apr 25 08:29:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223037 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 509F6C6FD18 for ; Tue, 25 Apr 2023 08:30:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233702AbjDYIa3 (ORCPT ); Tue, 25 Apr 2023 04:30:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233187AbjDYIaY (ORCPT ); Tue, 25 Apr 2023 04:30:24 -0400 Received: from mail-ej1-x629.google.com (mail-ej1-x629.google.com [IPv6:2a00:1450:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 994CD7D8C; Tue, 25 Apr 2023 01:30:03 -0700 (PDT) Received: by mail-ej1-x629.google.com with SMTP id a640c23a62f3a-94f1d0d2e03so785051466b.0; Tue, 25 Apr 2023 01:30:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411402; x=1685003402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2Zg6q3hENEW8zSi0jjqicVV9HpCo5eIV09wuIIBYAVE=; b=W/rzZtxCxh9koLA/qZzkgeA1WYuoFP1v0sTEFuJwTqCugbrzrnQZCR7pQef129xLyI vdyk8dbEz1Pyg71oX+UZ+7EFL47ljOfDXS5/Ny4zZg+zDEpnw2/tFY/NJjk/hMEuJVld j85bpdmxIjnO+/2FyUXkA56X99cc2TOnod+sE1uRg/Fd7KmM5ycYnAVO9ce8UwpjljJ7 EUWWcOK2KcaX6CRDkOWACShAVQLlpqhShkHM0NAFCAdop2kZNYEk011ESJhG6XqEp521 Dclxm32BEz1x/oKyKjub4cLE19w1ogi/pYV0IUY0EBHpZ3GO9fqWyG+h4XXSr2OBHWPc +u/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411402; x=1685003402; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Zg6q3hENEW8zSi0jjqicVV9HpCo5eIV09wuIIBYAVE=; b=GrcaBFvNDSbpjwJKfJw8VYBmj1TYD57TuxaabFqWpMZkbQdk8YYF+XP6vT86tDGkw+ s3/0HaPKx40jb3w4alqXtN4qgYMh4LMtgZ5FIWROL5imdSoENcjazFzzD/jmGZl6lI2P S7SxfQoYTNHZO3S/jcLXMSuapsqMF6GyUndBp7ifqG5IbdLX2zsFmwtIxwf8R26FP03r hgbNfNEu2eUtZ9MjgFKyG7rEK0UV0V7196X08bYBnI7PRkqo55PyRI29YNA45SSWPoue 6oQZBpZ/z2xKiAbV9i6ugvoojj8aLaJ9tMHQzPqQA9u78Jzml1styk+HWUmUEvJmkJjh 2tLw== X-Gm-Message-State: AAQBX9cmVZURriT3Ma4fW3QB1oMTEAkA+XfMN8e3wtMYHmx84CWf08JZ VIxlWdfk0rt4X5kuiyUV1qI= X-Google-Smtp-Source: AKy350bDc8HkZvDSbkV6BstZcjc9ipj6PtWcgYgA6ZSujLvNaR2DmLML6+XTpszjOptMZ2KI4uZzfA== X-Received: by 2002:a17:906:808:b0:953:856f:bd83 with SMTP id e8-20020a170906080800b00953856fbd83mr12738577ejd.75.1682411401875; Tue, 25 Apr 2023 01:30:01 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.29.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:01 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 04/24] net: dsa: mt7530: properly support MT7531AE and MT7531BE Date: Tue, 25 Apr 2023 11:29:13 +0300 Message-Id: <20230425082933.84654-5-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL Introduce the p5_sgmii pointer to store the information for whether port 5 has got SGMII or not. Move the comment about MT7531AE and MT7531BE to mt7531_setup(), where the switch is identified. Get rid of mt7531_dual_sgmii_supported() now that priv->p5_sgmii stores the information. Address the code where mt7531_dual_sgmii_supported() is used. Get rid of mt7531_is_rgmii_port() which just prints the opposite of priv->p5_sgmii. Remove P5_INTF_SEL_GMAC5_SGMII. The p5_interface_select enum is supposed to represent the mode that port 5 is being used in, not the hardware information of port 5. Set p5_intf_sel to P5_INTF_SEL_GMAC5 instead, if port 5 is not dsa_is_unused_port(). Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530-mdio.c | 7 ++---- drivers/net/dsa/mt7530.c | 43 ++++++++++++----------------------- drivers/net/dsa/mt7530.h | 6 +++-- 3 files changed, 21 insertions(+), 35 deletions(-) diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mt7530-mdio.c index 088533663b83..fa3ee85a99c1 100644 --- a/drivers/net/dsa/mt7530-mdio.c +++ b/drivers/net/dsa/mt7530-mdio.c @@ -81,17 +81,14 @@ static const struct regmap_bus mt7530_regmap_bus = { }; static int -mt7531_create_sgmii(struct mt7530_priv *priv, bool dual_sgmii) +mt7531_create_sgmii(struct mt7530_priv *priv) { struct regmap_config *mt7531_pcs_config[2] = {}; struct phylink_pcs *pcs; struct regmap *regmap; int i, ret = 0; - /* MT7531AE has two SGMII units for port 5 and port 6 - * MT7531BE has only one SGMII unit for port 6 - */ - for (i = dual_sgmii ? 0 : 1; i < 2; i++) { + for (i = priv->p5_sgmii ? 0 : 1; i < 2; i++) { mt7531_pcs_config[i] = devm_kzalloc(priv->dev, sizeof(struct regmap_config), GFP_KERNEL); diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 7d9f9563dbda..29abf2745294 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -473,15 +473,6 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) return 0; } -static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) -{ - u32 val; - - val = mt7530_read(priv, MT7531_TOP_SIG_SR); - - return (val & PAD_DUAL_SGMII_EN) != 0; -} - static int mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { @@ -496,7 +487,7 @@ mt7531_pll_setup(struct mt7530_priv *priv) u32 xtal; u32 val; - if (mt7531_dual_sgmii_supported(priv)) + if (priv->p5_sgmii) return; val = mt7530_read(priv, MT7531_CREV); @@ -907,8 +898,6 @@ static const char *p5_intf_modes(unsigned int p5_interface) return "PHY P4"; case P5_INTF_SEL_GMAC5: return "GMAC5"; - case P5_INTF_SEL_GMAC5_SGMII: - return "GMAC5_SGMII"; default: return "unknown"; } @@ -2440,6 +2429,12 @@ mt7531_setup(struct dsa_switch *ds) return -ENODEV; } + /* MT7531AE has got two SGMII units. One for port 5, one for port 6. + * MT7531BE has got only one SGMII unit which is for port 6. + */ + val = mt7530_read(priv, MT7531_TOP_SIG_SR); + priv->p5_sgmii = !!(val & PAD_DUAL_SGMII_EN); + /* all MACs must be forced link-down before sw reset */ for (i = 0; i < MT7530_NUM_PORTS; i++) mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); @@ -2451,19 +2446,16 @@ mt7531_setup(struct dsa_switch *ds) mt7531_pll_setup(priv); - if (mt7531_dual_sgmii_supported(priv)) { - priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; - + if (priv->p5_sgmii) { /* Let ds->slave_mii_bus be able to access external phy. */ mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, MT7531_EXT_P_MDC_11); mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, MT7531_EXT_P_MDIO_12); - } else { - priv->p5_intf_sel = P5_INTF_SEL_GMAC5; } - dev_dbg(ds->dev, "P5 support %s interface\n", - p5_intf_modes(priv->p5_intf_sel)); + + if (!dsa_is_unused_port(ds, 5)) + priv->p5_intf_sel = P5_INTF_SEL_GMAC5; mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); @@ -2523,11 +2515,6 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, } } -static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) -{ - return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); -} - static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { @@ -2540,7 +2527,7 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, break; case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ - if (mt7531_is_rgmii_port(priv, port)) { + if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } @@ -2607,7 +2594,7 @@ static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, { u32 val; - if (!mt7531_is_rgmii_port(priv, port)) { + if (priv->p5_sgmii) { dev_err(priv->dev, "RGMII mode is not available for port %d\n", port); return -EINVAL; @@ -2860,7 +2847,7 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port) switch (port) { case 5: - if (mt7531_is_rgmii_port(priv, port)) + if (!priv->p5_sgmii) interface = PHY_INTERFACE_MODE_RGMII; else interface = PHY_INTERFACE_MODE_2500BASEX; @@ -3019,7 +3006,7 @@ mt753x_setup(struct dsa_switch *ds) mt7530_free_irq_common(priv); if (priv->create_sgmii) { - ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); + ret = priv->create_sgmii(priv); if (ret && priv->irq) mt7530_free_irq(priv); } diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 415d8ea07472..2602c95fd3a5 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -679,7 +679,6 @@ enum p5_interface_select { P5_INTF_SEL_PHY_P0, P5_INTF_SEL_PHY_P4, P5_INTF_SEL_GMAC5, - P5_INTF_SEL_GMAC5_SGMII, }; struct mt7530_priv; @@ -749,6 +748,8 @@ struct mt753x_info { * @p6_interface: Holding the current port 6 interface * @p5_interface: Holding the current port 5 interface * @p5_intf_sel: Holding the current port 5 interface select + * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch + * has got SGMII * @irq: IRQ number of the switch * @irq_domain: IRQ domain of the switch irq_chip * @irq_enable: IRQ enable bits, synced to SYS_INT_EN @@ -769,6 +770,7 @@ struct mt7530_priv { phy_interface_t p6_interface; phy_interface_t p5_interface; enum p5_interface_select p5_intf_sel; + bool p5_sgmii; u8 mirror_rx; u8 mirror_tx; struct mt7530_port ports[MT7530_NUM_PORTS]; @@ -778,7 +780,7 @@ struct mt7530_priv { int irq; struct irq_domain *irq_domain; u32 irq_enable; - int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii); + int (*create_sgmii)(struct mt7530_priv *priv); }; struct mt7530_hw_vlan_entry { From patchwork Tue Apr 25 08:29:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223038 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4A72C6FD18 for ; Tue, 25 Apr 2023 08:30:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233699AbjDYIax (ORCPT ); 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Tue, 25 Apr 2023 01:30:03 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 05/24] net: dsa: mt7530: improve comments regarding port 5 and 6 Date: Tue, 25 Apr 2023 11:29:14 +0300 Message-Id: <20230425082933.84654-6-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL There's no logic to numerically order the CPU ports. State the port number and its capability of being used as a CPU port instead. Remove the irrelevant PHY muxing information from mt7530_mac_port_get_caps(). Explain the supported MII modes instead. Remove the out of place PHY muxing information from mt753x_phylink_mac_config(). The function is for both the MT7530 and MT7531 switches but there's no PHY muxing on MT7531. These comments were gradually introduced with the commits below. ca366d6c889b ("net: dsa: mt7530: Convert to PHYLINK API") 38f790a80560 ("net: dsa: mt7530: Add support for port 5") 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware") c288575f7810 ("net: dsa: mt7530: Add the support of MT7531 switch") Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 29abf2745294..d0eae8e8c41d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2498,7 +2498,9 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5 which can be used as a CPU port supports rgmii with + * delays, mii, and gmii. + */ phy_interface_set_rgmii(config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); @@ -2506,7 +2508,9 @@ static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 6: /* 1st cpu port */ + case 6: /* Port 6 which can be used as a CPU port supports rgmii and + * trgmii. + */ __set_bit(PHY_INTERFACE_MODE_RGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_TRGMII, @@ -2526,14 +2530,17 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, config->supported_interfaces); break; - case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ + case 5: /* Port 5 which can be used as a CPU port supports rgmii with + * delays on MT7531BE, sgmii/802.3z on MT7531AE. + */ if (!priv->p5_sgmii) { phy_interface_set_rgmii(config->supported_interfaces); break; } fallthrough; - case 6: /* 1st cpu port supports sgmii/8023z only */ + case 6: /* Port 6 which can be used as a CPU port supports sgmii/802.3z. + */ __set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces); __set_bit(PHY_INTERFACE_MODE_1000BASEX, @@ -2725,7 +2732,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, state->interface != PHY_INTERFACE_MODE_INTERNAL) goto unsupported; break; - case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ + case 5: /* Port 5, can be used as a CPU port. */ if (priv->p5_interface == state->interface) break; @@ -2735,7 +2742,7 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (priv->p5_intf_sel != P5_DISABLED) priv->p5_interface = state->interface; break; - case 6: /* 1st cpu port */ + case 6: /* Port 6, can be used as a CPU port. */ if (priv->p6_interface == state->interface) break; From patchwork Tue Apr 25 08:29:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223039 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3C28C77B76 for ; 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Tue, 25 Apr 2023 01:30:06 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:06 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 06/24] net: dsa: mt7530: read XTAL value from correct register Date: Tue, 25 Apr 2023 11:29:15 +0300 Message-Id: <20230425082933.84654-7-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL On commit 7ef6f6f8d237 ("net: dsa: mt7530: Add MT7621 TRGMII mode support") bit mask macros were added under the MT7530_HWTRAP register to read the crystal frequency. However, the value given to the xtal variable on mt7530_pad_clk_setup() is read from the MT7530_MHWTRAP register instead. It doesn't seem to matter as my testing on MCM and standalone MT7530 shows the value is correctly read from both registers but change it anyway. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index d0eae8e8c41d..98ef5ba0b19b 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -406,7 +406,7 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) struct mt7530_priv *priv = ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; - xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; + xtal = mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; if (xtal == HWTRAP_XTAL_20MHZ) { dev_err(priv->dev, From patchwork Tue Apr 25 08:29:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223040 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9F06C77B71 for ; Tue, 25 Apr 2023 08:31:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233710AbjDYIbS (ORCPT ); Tue, 25 Apr 2023 04:31:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233714AbjDYIaw (ORCPT ); Tue, 25 Apr 2023 04:30:52 -0400 Received: from mail-ej1-x62d.google.com (mail-ej1-x62d.google.com [IPv6:2a00:1450:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06561D30D; Tue, 25 Apr 2023 01:30:11 -0700 (PDT) Received: by mail-ej1-x62d.google.com with SMTP id a640c23a62f3a-94f6c285d22so1007838566b.2; Tue, 25 Apr 2023 01:30:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411409; x=1685003409; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Me/5070ACKIQU4J+v2mhTC588oNjGg5pGKAJrtCPvhY=; b=cS6Oz6YVZPKIdLSoVVLMCRnoc3D9cg0nE5K2dSxoqeBYwOLJI8Myz0/aCi5MQ09y/8 Bb9RBY+A67uEvB0HET36vE6K/F5516P1DFSUfZAfa7vIB7700QZkjazhffGKQSuPQxM6 78r5Hy0OziBGPmgLs8Xg2mQjI9t/iNu/TIRTctJu4pWqAzHOxJvzzW/x8BuiBPejmr8b cI1PKZWSDNNzk7Pq4A5X5lkWiP4UGeXABIzLOh/lP4Cobxr9VO+ntWO7ghvoOBYV8WkL U5DaUD2qaf2wDZs53Sg3IEB7NXya1tX5hyKc5TUzzc/e0/MijhrXxOw3c47Z3VFRUo41 Eu9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411409; x=1685003409; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Me/5070ACKIQU4J+v2mhTC588oNjGg5pGKAJrtCPvhY=; b=Z3X9iQcSL7rLBpUGNjXLiKec/tkScRTl+MWWBe9KVnQ4FHF6rWhFVYlGlqhox0apt0 cxyU3QrkbgkZn8uNCcQ0bO8efuCCOjJbR4xh3aZwYnzvPyMsyjNas4U1lsYQPQ5hRpWk Oqljn4CdEZ5XTxmWVpeLMjSWdNmHxBlJmj/kmfyKDEFsPPXzl/noYg8j/9//v6FQu+Cj 7iFhEt3JN5CbHEVpe2fsOYhO7R/eOfFjrEWx1xABklRO4Hf1hwnUvYsTxUvExVcytpWY 70o7uHqifpecE77S5XhZp+1RxVoTecTFmwnKzkEv6smORkX3e/GFQwskYF+eh9AGnTF5 F7VA== X-Gm-Message-State: AAQBX9fwpLJAo5ronQu9RnUOxEXxzSeDNvhWiL7//mmFMSyuCTb47lI6 TfKf6FnUkjMmn/dCKnnUvq0= X-Google-Smtp-Source: AKy350ZxsjzJSESr4bMyY+44vc6B2jumt24xvk4np9MIyL9T8ndSUBp+t6EzrMaq/uws1qhkGbLA1Q== X-Received: by 2002:a17:906:ecac:b0:94f:6218:191d with SMTP id qh12-20020a170906ecac00b0094f6218191dmr12652278ejb.32.1682411408919; Tue, 25 Apr 2023 01:30:08 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:08 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 07/24] net: dsa: mt7530: improve code path for setting up port 5 Date: Tue, 25 Apr 2023 11:29:16 +0300 Message-Id: <20230425082933.84654-8-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() Currently mt7530_setup_port5() from mt7530_setup() always runs. If port 5 is used as a CPU, DSA, or user port, mt7530_setup_port5() from mt753x_phylink_mac_config() won't run. That is because priv->p5_interface set on mt7530_setup_port5() will match state->interface on mt753x_phylink_mac_config() which will stop running mt7530_setup_port5() again. mt7530_setup_port5() from mt753x_phylink_mac_config() won't run when port 5 is disabled or used for PHY muxing as port 5 won't be defined on the devicetree. Therefore, mt7530_setup_port5() will never run from mt753x_phylink_mac_config(). Address this by not running mt7530_setup_port5() from mt7530_setup() if port 5 is used as a CPU, DSA, or user port. For the cases of PHY muxing or the port being disabled, call mt7530_setup_port5() from mt7530_setup(). Do not set priv->p5_interface on mt7530_setup_port5(). There won't be a case where mt753x_phylink_mac_config() runs after mt7530_setup_port5() anymore. Do not set priv->p5_intf_sel to P5_DISABLED. It is already set to that when "priv" is allocated. Move setting the interface to a more specific location. It's supposed to be overwritten if PHY muxing is detected. Improve the comment which explain the process. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 98ef5ba0b19b..f3d238a46543 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -968,8 +968,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); - priv->p5_interface = interface; - unlock_exit: mutex_unlock(&priv->reg_mutex); } @@ -2277,16 +2275,15 @@ mt7530_setup(struct dsa_switch *ds) return ret; /* Setup port 5 */ - priv->p5_intf_sel = P5_DISABLED; - interface = PHY_INTERFACE_MODE_NA; - if (!dsa_is_unused_port(ds, 5)) { priv->p5_intf_sel = P5_INTF_SEL_GMAC5; - ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); - if (ret && ret != -ENODEV) - return ret; } else { - /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ + /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. + * Set priv->p5_intf_sel to the appropriate value if PHY muxing + * is detected. + */ + interface = PHY_INTERFACE_MODE_NA; + for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2317,6 +2314,8 @@ mt7530_setup(struct dsa_switch *ds) of_node_put(phy_node); break; } + + mt7530_setup_port5(ds, interface); } #ifdef CONFIG_GPIOLIB @@ -2327,8 +2326,6 @@ mt7530_setup(struct dsa_switch *ds) } #endif /* CONFIG_GPIOLIB */ - mt7530_setup_port5(ds, interface); - /* Flush the FDB table */ ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); if (ret < 0) From patchwork Tue Apr 25 08:29:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223041 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41F23C77B71 for ; Tue, 25 Apr 2023 08:31:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233629AbjDYIbU (ORCPT ); Tue, 25 Apr 2023 04:31:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233721AbjDYIax (ORCPT ); Tue, 25 Apr 2023 04:30:53 -0400 Received: from mail-ed1-x536.google.com (mail-ed1-x536.google.com [IPv6:2a00:1450:4864:20::536]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC5B012C8C; Tue, 25 Apr 2023 01:30:12 -0700 (PDT) Received: by mail-ed1-x536.google.com with SMTP id 4fb4d7f45d1cf-504eb1155d3so40857222a12.1; Tue, 25 Apr 2023 01:30:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411411; x=1685003411; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ZV9/o17xPvhI7zBC/LGreGcB1RV1tqZFpx81rZya07Y=; b=ofF8cvyb2QFgkMaFU0VQLXptVklQ8QYHBxZEsNaTCvxJxJ3ZrhXI/Kj50pdwhqZ4Nd m4n/+USQGMKuN19yf+k41GD10ZUE3PQ2WoFFOe0XRWKmbhI7c/8sGw1va7ICq9H+RGdD pK4ocmhO/8mJ52fZJKcc+y3JE1N97UrkRTg+W6J9siDVo1kusSSfs/7yIjZQ+zgq1rQr Aiz2rplD7AvhqFoGRHPS7nx74qZEE9VrsWqoNhTTDFsDeZkRZ2NJ7po/x3mkDfsXy4/U WqzsJvin3es+my7E9TziBOYDLUD/qvx8CAkofVU1wR7lCrw1TgL5gb+fckZmxLm3zXK9 d/Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411411; x=1685003411; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ZV9/o17xPvhI7zBC/LGreGcB1RV1tqZFpx81rZya07Y=; b=SSgA/LFHewixfnmBJvlbTXxhMwL3yoq0eFnmLDQR0EnKF6JDYxHfvqkZ5EYVflNaZT BQKhb4HlnjAI6eJ5Bzfma4+hpaNTakr6+mosF8y+PHaEQHM8SiTBNExH+cu1XiodJvul UwYEg5FH9WGkvw4dgzd6+c9MLuk4T9vgJdWNvlc4OJijSzRrRRgEHJCUVeidS0XCirJ/ vAyiLUwE3wvoYuaK9pgM8fX6sAsDHsf7ae9ShXL07I+kIm1Ule6+FQcIezLAT3Tsip7q UOJNAOvD4pS7aH0FFqZTCY0i6j5ss4SPhrqDK+Xibfcb6towisQbsI1NzVqyOiYCCJ8K TSfw== X-Gm-Message-State: AAQBX9d4LUpX22EhppqPhubhDOpuCxvuWbXlWvbAyvnXmWfHR/iu+bgb HLsT03u+Rw5SCbiwj27Y4cg= X-Google-Smtp-Source: AKy350bQmjuao9lRHA+a9WNEY9AKrZ9G8JjIfn1vNnMwMltc90lAEtjbhzBai4IroqCXikVVgfWq9Q== X-Received: by 2002:a17:906:edc5:b0:953:7f08:a9ee with SMTP id sb5-20020a170906edc500b009537f08a9eemr12950081ejb.1.1682411411128; Tue, 25 Apr 2023 01:30:11 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:10 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 08/24] net: dsa: mt7530: do not run mt7530_setup_port5() if port 5 is disabled Date: Tue, 25 Apr 2023 11:29:17 +0300 Message-Id: <20230425082933.84654-9-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL There's no need to run all the code on mt7530_setup_port5() if port 5 is disabled. The only case for calling mt7530_setup_port5() from mt7530_setup() is when PHY muxing is enabled. That is because port 5 is not defined as a port on the devicetree, therefore, it cannot be controlled by phylink. Because of this, run mt7530_setup_port5() if priv->p5_intf_sel is P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4. Remove the P5_DISABLED case from mt7530_setup_port5(). Stop initialising the interface variable as the remaining cases will always call mt7530_setup_port5() with it initialised. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index f3d238a46543..5ef348b6a4b2 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -932,9 +932,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ val &= ~MHWTRAP_P5_DIS; break; - case P5_DISABLED: - interface = PHY_INTERFACE_MODE_NA; - break; default: dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", priv->p5_intf_sel); @@ -2282,8 +2279,6 @@ mt7530_setup(struct dsa_switch *ds) * Set priv->p5_intf_sel to the appropriate value if PHY muxing * is detected. */ - interface = PHY_INTERFACE_MODE_NA; - for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, "mediatek,eth-mac")) @@ -2315,7 +2310,9 @@ mt7530_setup(struct dsa_switch *ds) break; } - mt7530_setup_port5(ds, interface); + if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || + priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) + mt7530_setup_port5(ds, interface); } #ifdef CONFIG_GPIOLIB From patchwork Tue Apr 25 08:29:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223042 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DC07C77B61 for ; Tue, 25 Apr 2023 08:31:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233755AbjDYIbn (ORCPT ); Tue, 25 Apr 2023 04:31:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233485AbjDYIay (ORCPT ); Tue, 25 Apr 2023 04:30:54 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 576C212CB5; Tue, 25 Apr 2023 01:30:15 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-50674656309so8343885a12.0; Tue, 25 Apr 2023 01:30:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411413; x=1685003413; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w9apq9TPQdd3PTXsAONZD+3EUXt2FjfI3dHgVxl0ILg=; b=khGbo/D3U4zjnhtXvx72p4G9/VIdgAJBg3sQ+BZEAj8FIaLLZOejHV4kfL0xfLgp3P +Q4C7ap98BO/vC15GeppFmhhuc7LdsLwMvXvEeYiBXpUhCEcVGGtOA5BJmvXasi2J/ie NrP4viOHV7VoMvoU90Hx9lJ4Ql50hiNZ8Saae/W2fPKefRA/FVfml5L2+edJ6O0fyFoL mBNeZJuQ6mVOMpgczpuy7NytPz3JhRur/WLIrU2hDnEoUlVr8Bf7W4x4yoBRPXig2zrk 4wptCICRUQrU8SC5BgKKNz/vOXsF5nHaymBwKmnrw4sHIYnC9rMvJzBpR5NgHG7Z6fns gz1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411413; x=1685003413; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w9apq9TPQdd3PTXsAONZD+3EUXt2FjfI3dHgVxl0ILg=; b=A9aynX79RGEWfbVJ4mtPKrfzTTEUGcwMPDF/brjHlAu5o6B4kg3aey/trNsNR9ROU4 FJZD2GHlcE+XLPevwrof4wLSbqjes/4fteG1ahgDKqnmh1eOWAYd/S8PGOoHZemOfmXX kFEXpyqfsWBjZwTXDK+YfUh/d1nc6c/Gu+q6KxqmGwe6S+T2NN587A4gXj0/bHHJgpn/ nRvIgadwSIcPxnKTGOaAUqUL8L52hqziVwJQZHL+LL40lAt2/S4wMkmV0AA6NULWS7fY L6rdeStwjJF18EX8ikZLw9haGly3sdleGJ0dLmYu7yZbwCmF4FCW0rrryYMlP4BneDM5 x/LA== X-Gm-Message-State: AAQBX9cC7n/RFsweROi+fgKaNoMuPnpeqFezRUlQnkgFQ3Ciw/dt517O 2jVOYOP3lt+GJlg9ijq4gxA= X-Google-Smtp-Source: AKy350ZGqoo7GQeeSp2dqHa0n4V/z6iMCriDHZWhEtsodzBDMBu5CtUVKtp3P5D8vndAWw6eu4s3oA== X-Received: by 2002:aa7:d511:0:b0:506:84e0:a78a with SMTP id y17-20020aa7d511000000b0050684e0a78amr14370575edq.3.1682411413624; Tue, 25 Apr 2023 01:30:13 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:13 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 09/24] net: dsa: mt7530: change p{5,6}_interface to p{5,6}_configured Date: Tue, 25 Apr 2023 11:29:18 +0300 Message-Id: <20230425082933.84654-10-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL The idea of p5_interface and p6_interface pointers is to prevent mt753x_mac_config() from running twice for MT7531, as it's already run with mt753x_cpu_port_enable() from mt7531_setup_common(), if the port is used as a CPU port. Change p5_interface and p6_interface to p5_configured and p6_configured. Make them boolean. Do not set them for any other reason. The priv->p5_intf_sel check is useless as in this code path, it will always be P5_INTF_SEL_GMAC5. There was also no need to set priv->p5_interface and priv->p6_interface to PHY_INTERFACE_MODE_NA on mt7530_setup() and mt7531_setup() as they would already be set to that when "priv" is allocated. The pointers were of the phy_interface_t enumeration type, and the first element of the enum is PHY_INTERFACE_MODE_NA. There was nothing in between that would change this beforehand. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 19 ++++--------------- drivers/net/dsa/mt7530.h | 10 ++++++---- 2 files changed, 10 insertions(+), 19 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 5ef348b6a4b2..aab9ebb54d7d 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2237,8 +2237,6 @@ mt7530_setup(struct dsa_switch *ds) val |= MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); - priv->p6_interface = PHY_INTERFACE_MODE_NA; - /* Enable and reset MIB counters */ mt7530_mib_reset(ds); @@ -2454,10 +2452,6 @@ mt7531_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); - /* Let phylink decide the interface later. */ - priv->p5_interface = PHY_INTERFACE_MODE_NA; - priv->p6_interface = PHY_INTERFACE_MODE_NA; - /* Enable PHY core PLL, since phy_device has not yet been created * provided for phy_[read,write]_mmd_indirect is called, we provide * our own mt7531_ind_mmd_phy_[read,write] to complete this @@ -2727,25 +2721,20 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, goto unsupported; break; case 5: /* Port 5, can be used as a CPU port. */ - if (priv->p5_interface == state->interface) + if (priv->p5_configured) break; if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; - - if (priv->p5_intf_sel != P5_DISABLED) - priv->p5_interface = state->interface; break; case 6: /* Port 6, can be used as a CPU port. */ - if (priv->p6_interface == state->interface) + if (priv->p6_configured) break; mt753x_pad_setup(ds, state); if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; - - priv->p6_interface = state->interface; break; default: unsupported: @@ -2853,12 +2842,12 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port) else interface = PHY_INTERFACE_MODE_2500BASEX; - priv->p5_interface = interface; + priv->p5_configured = true; break; case 6: interface = PHY_INTERFACE_MODE_2500BASEX; - priv->p6_interface = interface; + priv->p6_configured = true; break; default: return -EINVAL; diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 2602c95fd3a5..06037be5882c 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -745,8 +745,10 @@ struct mt753x_info { * @ports: Holding the state among ports * @reg_mutex: The lock for protecting among process accessing * registers - * @p6_interface: Holding the current port 6 interface - * @p5_interface: Holding the current port 5 interface + * @p6_configured: Flag for distinguishing if port 6 of the MT7531 switch + * is already configured + * @p5_configured: Flag for distinguishing if port 5 of the MT7531 switch + * is already configured * @p5_intf_sel: Holding the current port 5 interface select * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch * has got SGMII @@ -767,8 +769,8 @@ struct mt7530_priv { const struct mt753x_info *info; unsigned int id; bool mcm; - phy_interface_t p6_interface; - phy_interface_t p5_interface; + bool p6_configured; + bool p5_configured; enum p5_interface_select p5_intf_sel; bool p5_sgmii; u8 mirror_rx; From patchwork Tue Apr 25 08:29:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223043 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C6858C6FD18 for ; Tue, 25 Apr 2023 08:32:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233747AbjDYIb6 (ORCPT ); Tue, 25 Apr 2023 04:31:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51184 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233749AbjDYIbF (ORCPT ); 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Tue, 25 Apr 2023 01:30:15 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 10/24] net: dsa: mt7530: empty default case on mt7530_setup_port5() Date: Tue, 25 Apr 2023 11:29:19 +0300 Message-Id: <20230425082933.84654-11-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL There're two code paths for setting up port 5: mt7530_setup() -> mt7530_setup_port5() mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() On the first code path, priv->p5_intf_sel is either set to P5_INTF_SEL_PHY_P0 or P5_INTF_SEL_PHY_P4 when mt7530_setup_port5() is run. On the second code path, priv->p5_intf_sel is set to P5_INTF_SEL_GMAC5 when mt7530_setup_port5() is run. Empty the default case which will never run but is needed nonetheless to handle all the remaining enumeration values. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index aab9ebb54d7d..b3db68d6939a 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -933,9 +933,7 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) val &= ~MHWTRAP_P5_DIS; break; default: - dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", - priv->p5_intf_sel); - goto unlock_exit; + break; } /* Setup RGMII settings */ @@ -965,7 +963,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); -unlock_exit: mutex_unlock(&priv->reg_mutex); } From patchwork Tue Apr 25 08:29:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223044 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 371E2C77B61 for ; Tue, 25 Apr 2023 08:32:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233697AbjDYIcE (ORCPT ); Tue, 25 Apr 2023 04:32:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50740 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233692AbjDYIbP (ORCPT ); Tue, 25 Apr 2023 04:31:15 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11FD612CAE; Tue, 25 Apr 2023 01:30:29 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-94f3df30043so855633666b.2; Tue, 25 Apr 2023 01:30:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411418; x=1685003418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qYvT8p6k4QzjjyECcMuC9v3ADC+KmlXGNmZgRR/65Uw=; b=UFAWV+1nlYwHQzmvVoN+/ZGHkk8Ew6bnLA4u2VQgfyZAcCJBju7Y+Fnro9dB2ZJtL0 C/alKxlYDz+fVsz2Ihz4l80W0RV4ghlklTO7m0U8xCQt3BL19sExvBSbXszlA0fF6KUk 1eITtM+juvDNuYId73jffkWAARmjB9pviSHpLvr0G3+bvGzduU7EIE32owSg70FaHljV wWYUuWlVANCESpYjAgJirzkcRVCU0+Wvx1QVDp7nZ1Pi0nATIdzczuM2KNxXe/rTEbfl P/9HAYz0wiH6MA/4MS7xf+biFw8kB9lzoyu7P1N1r3+3b+uBVZAXKHytk6mRS/8QVtFP xxbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411418; x=1685003418; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qYvT8p6k4QzjjyECcMuC9v3ADC+KmlXGNmZgRR/65Uw=; b=Z3WzDeUKKgL64+nlEyPYWq5Pg0RTNAnerfddIvmTBTMNpwPiqZeF9GUWsXaTwe30uz kejZbT9B0gkO03e9DBRUVuJv+GF6DPrHVDVt/DFp504egCK8VYhck/F7dgnZQRJYjteM 4rlbqZIQos5ejzCyGFnWG+RGCuSI42G7x1yIVQoZnLcgzw//TEbF39wRfqhU8CbdaxNd tgOKJKV52GruMw+bxJZjnGsy/QsmwvmfGhZGqowgYQZ+HDUKtcHhodWrrD4R0SrqwYBn fw9tBHnZcWfJwWHS7IGxXoEOiLhEjQgXsfesIr6rblFEf4XaEf87U91NmNATT5lXCTah BObA== X-Gm-Message-State: AAQBX9edzSRFGNGGTRUfxycSDoLX8Q4m0I/wciifp2w2FH1ivkKDgvEX Sn9it3HmLm1go8o+M+bx2Mg= X-Google-Smtp-Source: AKy350bujQz7yBAk7lju8dfbrKLpTH57gUasXDGEw8almcL4eBYWv7XfFoi97n3oFAUp43HpRDReTw== X-Received: by 2002:a17:906:d8ac:b0:94f:37af:d21b with SMTP id qc12-20020a170906d8ac00b0094f37afd21bmr12578329ejb.74.1682411418239; Tue, 25 Apr 2023 01:30:18 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:17 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 11/24] net: dsa: mt7530: call port 6 setup from mt7530_mac_config() Date: Tue, 25 Apr 2023 11:29:20 +0300 Message-Id: <20230425082933.84654-12-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL mt7530_pad_clk_setup() is called if port 6 is enabled. It used to do more things than setting up port 6. That part was moved to more appropriate locations, mt7530_setup() and mt7530_pll_setup(). Now that all it does is set up port 6, rename it to mt7530_setup_port6(), and move it to a more appropriate location, under mt7530_mac_config(). Leave an empty mt7530_pad_clk_setup() to satisfy the pad_setup function pointer. This is the call path for setting up the ports before: mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() -> mt753x_pad_setup() -> mt7530_pad_clk_setup() This is after: mt753x_phylink_mac_config() -> mt753x_mac_config() -> mt7530_mac_config() -> mt7530_setup_port5() -> mt7530_setup_port6() Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 21 +++++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index b3db68d6939a..6815d2579f37 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -401,7 +401,7 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) /* Setup port 6 interface mode and TRGMII TX circuit */ static int -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) +mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; u32 ncpo1, ssc_delta, trgint, xtal; @@ -473,6 +473,12 @@ mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) return 0; } +static int +mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) +{ + return 0; +} + static int mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) { @@ -2570,12 +2576,15 @@ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; + int ret; - /* Only need to setup port5. */ - if (port != 5) - return 0; - - mt7530_setup_port5(priv->ds, interface); + if (port == 5) { + mt7530_setup_port5(priv->ds, interface); + } else if (port == 6) { + ret = mt7530_setup_port6(priv->ds, interface); + if (ret) + return ret; + } return 0; } From patchwork Tue Apr 25 08:29:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223045 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EA517C77B76 for ; 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Tue, 25 Apr 2023 01:30:20 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:20 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 12/24] net: dsa: mt7530: remove pad_setup function pointer Date: Tue, 25 Apr 2023 11:29:21 +0300 Message-Id: <20230425082933.84654-13-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL The pad_setup function pointer was introduced with 88bdef8be9f6 ("net: dsa: mt7530: Extend device data ready for adding a new hardware"). It was being used to set up the core clock and port 6 of the MT7530 switch, and pll of the MT7531 switch. All of these were moved to more appropriate locations, and it was never used for the switch on the MT7988 SoC. Therefore, this function pointer hasn't got a use anymore. Remove it. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 36 ++---------------------------------- drivers/net/dsa/mt7530.h | 3 --- 2 files changed, 2 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 6815d2579f37..2addd5e7fbe6 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -473,18 +473,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) return 0; } -static int -mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - -static int -mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - static void mt7531_pll_setup(struct mt7530_priv *priv) { @@ -2563,14 +2551,6 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, } } -static int -mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) -{ - struct mt7530_priv *priv = ds->priv; - - return priv->info->pad_setup(ds, state->interface); -} - static int mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) @@ -2737,8 +2717,6 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, if (priv->p6_configured) break; - mt753x_pad_setup(ds, state); - if (mt753x_mac_config(ds, port, mode, state) < 0) goto unsupported; break; @@ -3040,11 +3018,6 @@ static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, return 0; } -static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) -{ - return 0; -} - static int mt7988_setup(struct dsa_switch *ds) { struct mt7530_priv *priv = ds->priv; @@ -3106,7 +3079,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c22 = mt7530_phy_write_c22, .phy_read_c45 = mt7530_phy_read_c45, .phy_write_c45 = mt7530_phy_write_c45, - .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, .mac_port_config = mt7530_mac_config, }, @@ -3118,7 +3090,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c22 = mt7530_phy_write_c22, .phy_read_c45 = mt7530_phy_read_c45, .phy_write_c45 = mt7530_phy_write_c45, - .pad_setup = mt7530_pad_clk_setup, .mac_port_get_caps = mt7530_mac_port_get_caps, .mac_port_config = mt7530_mac_config, }, @@ -3130,7 +3101,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c22 = mt7531_ind_c22_phy_write, .phy_read_c45 = mt7531_ind_c45_phy_read, .phy_write_c45 = mt7531_ind_c45_phy_write, - .pad_setup = mt7531_pad_setup, .cpu_port_config = mt7531_cpu_port_config, .mac_port_get_caps = mt7531_mac_port_get_caps, .mac_port_config = mt7531_mac_config, @@ -3143,7 +3113,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c22 = mt7531_ind_c22_phy_write, .phy_read_c45 = mt7531_ind_c45_phy_read, .phy_write_c45 = mt7531_ind_c45_phy_write, - .pad_setup = mt7988_pad_setup, .cpu_port_config = mt7988_cpu_port_config, .mac_port_get_caps = mt7988_mac_port_get_caps, .mac_port_config = mt7988_mac_config, @@ -3173,9 +3142,8 @@ mt7530_probe_common(struct mt7530_priv *priv) /* Sanity check if these required device operations are filled * properly. */ - if (!priv->info->sw_setup || !priv->info->pad_setup || - !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || - !priv->info->mac_port_get_caps || + if (!priv->info->sw_setup || !priv->info->phy_read_c22 || + !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps || !priv->info->mac_port_config) return -EINVAL; diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 06037be5882c..f7a504e4c17b 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -696,8 +696,6 @@ struct mt753x_pcs { * @phy_write_c22: Holding the way writing PHY port using C22 * @phy_read_c45: Holding the way reading PHY port using C45 * @phy_write_c45: Holding the way writing PHY port using C45 - * @pad_setup: Holding the way setting up the bus pad for a certain - * MAC port * @phy_mode_supported: Check if the PHY type is being supported on a certain * port * @mac_port_validate: Holding the way to set addition validate type for a @@ -718,7 +716,6 @@ struct mt753x_info { int regnum); int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, int regnum, u16 val); - int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); int (*cpu_port_config)(struct dsa_switch *ds, int port); void (*mac_port_get_caps)(struct dsa_switch *ds, int port, struct phylink_config *config); From patchwork Tue Apr 25 08:29:22 2023 Content-Type: text/plain; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 13/24] net: dsa: mt7530: move XTAL check to mt7530_setup() Date: Tue, 25 Apr 2023 11:29:22 +0300 Message-Id: <20230425082933.84654-14-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL The crystal frequency concerns the switch core. The frequency should be checked when the switch is being set up so the driver can reject the unsupported hardware earlier and without requiring port 6 to be used. Move it to mt7530_setup(). Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 2addd5e7fbe6..04a48829465c 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -408,13 +408,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) xtal = mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; - if (xtal == HWTRAP_XTAL_20MHZ) { - dev_err(priv->dev, - "%s: MT7530 with a 20MHz XTAL is not supported!\n", - __func__); - return -EINVAL; - } - switch (interface) { case PHY_INTERFACE_MODE_RGMII: trgint = 0; @@ -2136,7 +2129,7 @@ mt7530_setup(struct dsa_switch *ds) struct mt7530_dummy_poll p; phy_interface_t interface; struct dsa_port *cpu_dp; - u32 id, val; + u32 id, val, xtal; int ret, i; /* The parent node of master netdev which holds the common system @@ -2206,6 +2199,15 @@ mt7530_setup(struct dsa_switch *ds) return -ENODEV; } + xtal = mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; + + if (xtal == HWTRAP_XTAL_20MHZ) { + dev_err(priv->dev, + "%s: MT7530 with a 20MHz XTAL is not supported!\n", + __func__); + return -EINVAL; + } + /* Reset the switch through internal reset */ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | From patchwork Tue Apr 25 08:29:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223047 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AAB7C6FD18 for ; Tue, 25 Apr 2023 08:32:35 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233393AbjDYIcc (ORCPT ); Tue, 25 Apr 2023 04:32:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51258 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233315AbjDYIba (ORCPT ); Tue, 25 Apr 2023 04:31:30 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6775113C27; Tue, 25 Apr 2023 01:30:38 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-956eacbe651so958824966b.3; Tue, 25 Apr 2023 01:30:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411427; x=1685003427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4MATvTsgGeOmEQ/GANoUT20RiIWs3kO1MdMdepZzbt0=; b=bjcPp1ixgcYS0CdsMEKFpoRu5Vl9iYehRJyOq+x3P+aPBuYpVbrBkxhDE60ijZq4Cn jsAE6U7+b2vCL4yZJg6hDCZrZkjgZXqD1Fk+FHc30mWrtj31wfLnjVvbNfceZ7xwlOE9 dcVL9knnSHgtpJFYrObMrkCAWBD0JhQJKWW2VmvOVEg7E7XuL0yCSc6RKFSPmvlVamG+ ztYFGQInl27UNENF0L6JukJ63mBAw1u1lZE+RxMDKVeZNrVOXIbsAOVAE8t0rpzFF/j+ CZhTBxMbN5iW0l+3973AX/+j6/Z0WSfZ2qxvPR5aXn/3v7Pfi94NFbkeQbnDROUntJoU DLAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411427; x=1685003427; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4MATvTsgGeOmEQ/GANoUT20RiIWs3kO1MdMdepZzbt0=; b=hy9d+v8XqmJp3rnKUd5yTtgUlV1uCOljEgf1qGAptksT6ytixN4h8lv7i2O41jzY6L fjGAi4BEjJzPG7qgCg7KbO6OSVFWVyncBSFNM1ZLqCASVLBmVYU9xyAFcrPekhfCoMlW CvYdTVjYjhmBTySWPlRDQXCMkGVcWxWweR+zu5avpdAF5dhti4+5IBRVnT19k6dhgLHP 4q5/5eVdx3xcbIL3byrAA5UiPOrSv4tStwPrrjI6VEPtqGMb3KqaiscTy3/yOn+q+ma9 RDkdTuKVQrvheX3Umf/CfqaZMa2u2lPfAcyP08ijo3hjbPe6/Dt/ZKc3JZyBh7CmvEle 8usw== X-Gm-Message-State: AAQBX9cH2VupmrFAlvTrFo8ILpQ6jHEL6HAnwQfCnMD9gmI3iNdcNVJi SVonTjIRxoPysw4B/VSyE1s= X-Google-Smtp-Source: AKy350Ym3aXZPGeAbGZAmIl+ZSX9R9HZR20W6VN0rTWWg05z4lCRUaNGqdiq7x1Mun7p5ti0Rr6aog== X-Received: by 2002:a17:906:9bfa:b0:94e:c4b:4d95 with SMTP id de58-20020a1709069bfa00b0094e0c4b4d95mr12322934ejc.69.1682411427432; Tue, 25 Apr 2023 01:30:27 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:26 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 14/24] net: dsa: mt7530: move enabling port 6 to mt7530_setup_port6() Date: Tue, 25 Apr 2023 11:29:23 +0300 Message-Id: <20230425082933.84654-15-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL Enable port 6 only when port 6 is being used. Update the comment on mt7530_setup() with a better explanation. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 04a48829465c..980d59170ba2 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -404,7 +404,11 @@ static int mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; - u32 ncpo1, ssc_delta, trgint, xtal; + u32 ncpo1, ssc_delta, trgint, xtal, val; + + val = mt7530_read(priv, MT7530_MHWTRAP); + val &= ~MHWTRAP_P6_DIS; + mt7530_write(priv, MT7530_MHWTRAP, val); xtal = mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; @@ -2224,9 +2228,9 @@ mt7530_setup(struct dsa_switch *ds) mt7530_rmw(priv, MT7530_TRGMII_RD(i), RD_TAP_MASK, RD_TAP(16)); - /* Enable port 6 */ + /* Enable PHY access and operate in manual mode */ val = mt7530_read(priv, MT7530_MHWTRAP); - val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; + val &= ~MHWTRAP_PHY_ACCESS; val |= MHWTRAP_MANUAL; mt7530_write(priv, MT7530_MHWTRAP, val); From patchwork Tue Apr 25 08:29:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223048 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADDA8C6FD18 for ; Tue, 25 Apr 2023 08:32:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233815AbjDYIcx (ORCPT ); Tue, 25 Apr 2023 04:32:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51150 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233729AbjDYIbp (ORCPT ); Tue, 25 Apr 2023 04:31:45 -0400 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D913913F89; Tue, 25 Apr 2023 01:30:43 -0700 (PDT) Received: by mail-ej1-x62f.google.com with SMTP id a640c23a62f3a-94f3df30043so855667266b.2; Tue, 25 Apr 2023 01:30:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411430; x=1685003430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=co2jsjwTwJzbd0CfvHd0rFDJW53+yrpC0IXVfcexPcs=; b=XKb6hqva9cpaCTomkMHevUFoOT7/EU2Bze1fOeF/HN9vi9NOc1a+AGZkDack/8l0MD CdM/Ra+IIeBSyktSfQbpm8gj15u1/9FXIW0O+Js7Q/Zl/xgIyxVlCtvzxz8Sy2x49uxo LZKNfuW3TxpjjSjRph7wkZHXTgWZZCfeH3jdjen2DgyAWNwf0mYfOkNd6TV4NKXQqkit yeL2gxBcpSfcHwx9HlamE1NhYdEkYIpH1YEyXBfnhgiJch7oesiUG4A+HnisISEyjG3p 6sbfi3IxOUWc/OL21CNwTZVx2ETn3oV+llgn4CMEDJtM2pLu+L+nG4oFDQDgIJTm+wuV I9hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411430; x=1685003430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=co2jsjwTwJzbd0CfvHd0rFDJW53+yrpC0IXVfcexPcs=; b=Z7CDEAD+LWOUTns78NwwzOSboZ7WEolQE4m9eeMrFgCoopQQyLOB4LlR6O4gd3Einn jKzclLSPT/y3vx2PW5YALEedaJc1A5F99XReFkTZ9Gi+8ZxeCJh+e/oRBIGiN+1NxrbJ D9wX888WLuowvpeJ8iDfUKYybE0xkfZSS6XsMQbE0ZGBnowGUNxKz6K/qsLzUdrQz+bp o6tv4KUbCUnywWpctMndCqzYrypP1261sp7Xsi89SpMLZj8JBnswdOnHdIRKO+5SMWD4 tV4bVn2ybvuWw7K8Cz4NH5ean2K/rRWhU0N2t0+uYo6kbHr1/syZj3S2iQdJhoTt1NyK Sing== X-Gm-Message-State: AAQBX9eNtWd5H9ekaOLMkp+I23/Ox7YFLXvQC8uLgq2d1EswBOIiaqV3 6WCUdHyloMM/tLE4OVNfzZU= X-Google-Smtp-Source: AKy350byQOy4L1omedzexSzAU2byBGn+c47N2fDo8+2S0flJALDDrH1iY3icL0zV3jg3N5AK/4u2nA== X-Received: by 2002:a17:906:69ca:b0:94a:5925:56e2 with SMTP id g10-20020a17090669ca00b0094a592556e2mr12028586ejs.22.1682411429791; Tue, 25 Apr 2023 01:30:29 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:29 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 15/24] net: dsa: mt7530: switch to if/else statements on mt7530_setup_port6() Date: Tue, 25 Apr 2023 11:29:24 +0300 Message-Id: <20230425082933.84654-16-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL This code is from before this driver was converted to phylink API. Phylink deals with the unsupported interface cases before mt7530_setup_port6() is run. Therefore, the default case would never run. However, it must be defined nonetheless to handle all the remaining enumeration values, the phy-modes. Switch to if/else statements which simplifies the code. Change mt7530_setup_port6() to void now that there're no error cases left. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 35 +++++++++++------------------------ 1 file changed, 11 insertions(+), 24 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 980d59170ba2..ea023e32313c 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -400,11 +400,11 @@ static void mt7530_pll_setup(struct mt7530_priv *priv) } /* Setup port 6 interface mode and TRGMII TX circuit */ -static int +static void mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; - u32 ncpo1, ssc_delta, trgint, xtal, val; + u32 ncpo1, ssc_delta, xtal, val; val = mt7530_read(priv, MT7530_MHWTRAP); val &= ~MHWTRAP_P6_DIS; @@ -412,16 +412,18 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) xtal = mt7530_read(priv, MT7530_HWTRAP) & HWTRAP_XTAL_MASK; - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - trgint = 0; - break; - case PHY_INTERFACE_MODE_TRGMII: - trgint = 1; + if (interface == PHY_INTERFACE_MODE_RGMII) { + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, + P6_INTF_MODE(0)); + } else { + mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, + P6_INTF_MODE(1)); + if (xtal == HWTRAP_XTAL_25MHZ) ssc_delta = 0x57; else ssc_delta = 0x87; + if (priv->id == ID_MT7621) { /* PLL frequency: 125MHz: 1.0GBit */ if (xtal == HWTRAP_XTAL_40MHZ) @@ -434,17 +436,7 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) if (xtal == HWTRAP_XTAL_25MHZ) ncpo1 = 0x1400; } - break; - default: - dev_err(priv->dev, "xMII interface %d not supported\n", - interface); - return -EINVAL; - } - mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, - P6_INTF_MODE(trgint)); - - if (trgint) { /* Disable the MT7530 TRGMII clocks */ core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); @@ -466,8 +458,6 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) /* Enable the MT7530 TRGMII clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); } - - return 0; } static void @@ -2562,14 +2552,11 @@ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; - int ret; if (port == 5) { mt7530_setup_port5(priv->ds, interface); } else if (port == 6) { - ret = mt7530_setup_port6(priv->ds, interface); - if (ret) - return ret; + mt7530_setup_port6(priv->ds, interface); } return 0; From patchwork Tue Apr 25 08:29:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223049 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A0E4C77B71 for ; Tue, 25 Apr 2023 08:32:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233828AbjDYIcz (ORCPT ); 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Tue, 25 Apr 2023 01:30:31 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 16/24] net: dsa: mt7530: set TRGMII RD TAP if trgmii is being used Date: Tue, 25 Apr 2023 11:29:25 +0300 Message-Id: <20230425082933.84654-17-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL This code sets the Read Data (RD) TAP value to 16 for all TRGMII control registers. The for loop iterates over all the TRGMII control registers, and mt7530_rmw() function is used to perform a read-modify-write operation on each register's RD_TAP field to set its value to 16. This operation is used to tune the timing of the read data signal in TRGMII to match the TX signal of the link partner. Run this if trgmii is being used. Since this code doesn't lower the driving, there's no apparent benefit to run this if trgmii is not being used. Add a comment to explain the code. Thanks to 趙皎宏 (Landen Chao) for pointing out what the code does. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index ea023e32313c..0108af681d50 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -404,7 +404,7 @@ static void mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) { struct mt7530_priv *priv = ds->priv; - u32 ncpo1, ssc_delta, xtal, val; + u32 ncpo1, ssc_delta, i, xtal, val; val = mt7530_read(priv, MT7530_MHWTRAP); val &= ~MHWTRAP_P6_DIS; @@ -457,6 +457,11 @@ mt7530_setup_port6(struct dsa_switch *ds, phy_interface_t interface) /* Enable the MT7530 TRGMII clocks */ core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); + + /* Set the Read Data TAP value of the MT7530 TRGMII */ + for (i = 0; i < NUM_TRGMII_CTRL; i++) + mt7530_rmw(priv, MT7530_TRGMII_RD(i), + RD_TAP_MASK, RD_TAP(16)); } } @@ -2214,10 +2219,6 @@ mt7530_setup(struct dsa_switch *ds) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), TD_DM_DRVP(8) | TD_DM_DRVN(8)); - for (i = 0; i < NUM_TRGMII_CTRL; i++) - mt7530_rmw(priv, MT7530_TRGMII_RD(i), - RD_TAP_MASK, RD_TAP(16)); - /* Enable PHY access and operate in manual mode */ val = mt7530_read(priv, MT7530_MHWTRAP); val &= ~MHWTRAP_PHY_ACCESS; From patchwork Tue Apr 25 08:29:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223050 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2C049C6FD18 for ; Tue, 25 Apr 2023 08:32:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233832AbjDYIc5 (ORCPT ); Tue, 25 Apr 2023 04:32:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51358 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233593AbjDYIbp (ORCPT ); Tue, 25 Apr 2023 04:31:45 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 301815FF0; Tue, 25 Apr 2023 01:30:46 -0700 (PDT) Received: by mail-ej1-x633.google.com with SMTP id a640c23a62f3a-94a34a0b9e2so785275866b.1; Tue, 25 Apr 2023 01:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411435; x=1685003435; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JLm5jhMS6rFgBzI8z+1W06D+EQwsGdSNOt8/QtnXpBI=; b=Ap33L6THf74ai+r6w//IbTznSDtVocBHM7PTMhbUVfihCpZZoQIMHkxxJxGeEJcFC/ m7DTVjUb7UVORIdFwiVaP2fX40jbGS+gPtiHiGOl/PJYrToSEyBp8AYAo8enkovg4GFT 4UNqxOpTWde9ytaO7rCQgHe2y9ifeACQWjT3Bwk2AXYZkf0BHGACL98CiV57oeUR7jr0 uJQO69lTIf9GkCBwWdtWCNNfVIZQkCQw8pFL2zFYnURSiNEGHW21iFFJlv2xR46grMhS YRwwT2rwFyD2euHDZhxdEyl3AQfWZIo0WFToBHaa1RGWxwnjIfqla7zrbTT0UglGusru GM8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411435; x=1685003435; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JLm5jhMS6rFgBzI8z+1W06D+EQwsGdSNOt8/QtnXpBI=; b=jmm5LV/nD6x5ZwHeM1QNWB3doP7cJx+48I2AYGvas8LEE81Izle+eH+hNj9lbgqU9L B+uM/T5TTKZ9gSEgShTkx4J+OFloED/iCtTeRFXgjLP1dFa5aXm8ZuVP2RAxwrGPuM5v yw7JBTIlNjqlgqOFuEuEkTC8iyicyPQqGzMceDtuESK/IDdMQ24LOyIslxKo0UaPHsl8 8aNnjrgy4KImGIc8hmav1/ueetWsh65oFoJCcctUWq/2i6qEZfll7n8McsxT9UfE51Ie SgSwvNgz+GtoYdqxNFNiba8PZq3hfIR4XP4LDIZ4OnOerT5/DK257jD2PNL0VVRjkM6o SfaA== X-Gm-Message-State: AAQBX9dw8OH9Ug6r9gslRyJwO6ALEUhK1uWGp/+6XKVc59duvbY2Utkb IdRuMJzJnUIqMlbhlVVX7oQ= X-Google-Smtp-Source: AKy350ZHnHWTezegV98s6VGWqeQ9P96T/8gc+hf2umUdZqmtltCd4D7zYoSKx0DLOxIbyURM78gaRQ== X-Received: by 2002:a17:906:170e:b0:947:c221:eb38 with SMTP id c14-20020a170906170e00b00947c221eb38mr12120196eje.13.1682411434710; Tue, 25 Apr 2023 01:30:34 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:34 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 17/24] net: dsa: mt7530: move lowering port 5 RGMII driving to mt7530_setup() Date: Tue, 25 Apr 2023 11:29:26 +0300 Message-Id: <20230425082933.84654-18-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL Move lowering Tx driving of rgmii on port 5 to right before lowering of Tx driving of trgmii on port 6 on mt7530_setup(). This way, the switch should consume less power regardless of port 5 being used. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 0108af681d50..468c50b3f43b 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -938,10 +938,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) /* P5 RGMII TX Clock Control: delay x */ mt7530_write(priv, MT7530_P5RGMIITXCR, CSR_RGMII_TXC_CFG(0x10 + tx_delay)); - - /* reduce P5 RGMII Tx driving, 8mA */ - mt7530_write(priv, MT7530_IO_DRV_CR, - P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); } mt7530_write(priv, MT7530_MHWTRAP, val); @@ -2214,6 +2210,10 @@ mt7530_setup(struct dsa_switch *ds) mt7530_pll_setup(priv); + /* Lower P5 RGMII Tx driving, 8mA */ + mt7530_write(priv, MT7530_IO_DRV_CR, + P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); + /* Lower Tx driving for TRGMII path */ for (i = 0; i < NUM_TRGMII_CTRL; i++) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), From patchwork Tue Apr 25 08:29:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223051 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69C1FC77B61 for ; Tue, 25 Apr 2023 08:33:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233732AbjDYIc6 (ORCPT ); Tue, 25 Apr 2023 04:32:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233612AbjDYIbs (ORCPT ); Tue, 25 Apr 2023 04:31:48 -0400 Received: from mail-ej1-x62b.google.com (mail-ej1-x62b.google.com [IPv6:2a00:1450:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AFA0913C3C; Tue, 25 Apr 2023 01:30:46 -0700 (PDT) Received: by mail-ej1-x62b.google.com with SMTP id a640c23a62f3a-9536df4b907so1010396066b.0; Tue, 25 Apr 2023 01:30:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411437; x=1685003437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C5hqUQUWJA4Uxj9fJ3Q/CFxmrWCj6ubL+CzXNJi3V1s=; b=l6Zmw5EkxiNQk+byLSELxBUGpq8fx69yVzl8OnHtsAdKEPG57VTkFohAnDFKn5maJV +NupxKI9QlQzq3hcCniFstqkxZdfJxYcKY2T0A6sn37l2eSu7/BUfpmqUTCz/8duqtcz aQ5pf4IWcK/LiFfP/HYsvX/ii1Xu+lP23zV/k/ySZc4iksp8itwYux+s3LaS1DMLoarf IcLPWfjkA9xU2/m95m6aiZQQ/Y9tPsozse6D3dGkalyogZDGE1fg2N2cVbNT0dOljW7m 2/52tKdaFQTEK177jh9lK/TU7+mml47SfUT7jc1NUSlwjpDYSQFgEj3kmcmGqv3WoMkg FdRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411437; x=1685003437; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C5hqUQUWJA4Uxj9fJ3Q/CFxmrWCj6ubL+CzXNJi3V1s=; b=Jyodfs8YBek0Zo0B485HBG7bDazQv4jRMTXWxHca/XMvAXLYy0GmxMNhAj8Or/9NCt 18YGTB0RUYgDavLESDmmUMU5wrdeSNcz+60ksrB+L8IpQ7Zgu+QFmJOKmk1HbN10x5Pa adtL2ROw1bxZuPCImchXeRJ/AUJ+up1i4/ocLDywyfBvVAhnbdv+ws9OBHiJeCmNH8xF hAhDN69ZvvczfPd9NEas1NMbQeXBQk6GwTprKmswqi3QUANDVkKAdh7tnhj8rIRBrep+ jgrvWW+dRsSe9CtUbDm5zZ2C2TEf1u3LJtMawsqgE75wxDWtojaRISwGs/RPJm2uqGH6 BpNg== X-Gm-Message-State: AAQBX9fPOE++TiQv48jRWs4VgHe8w81mpr9uoTRZ60ve2pL4Lj1bQc5Z TvpROM+c/GTOECB4gyf1KjI= X-Google-Smtp-Source: AKy350b37JDSEapeflnu+5zn7Wr27HMEhEoGZYWKkBgRxS9IHg7Eds53wkx91bSWNPonWlDIM7kelA== X-Received: by 2002:a17:907:d21:b0:94f:39d7:6454 with SMTP id gn33-20020a1709070d2100b0094f39d76454mr14917820ejc.63.1682411437241; Tue, 25 Apr 2023 01:30:37 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:36 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 18/24] net: dsa: mt7530: fix port capabilities for MT7988 Date: Tue, 25 Apr 2023 11:29:27 +0300 Message-Id: <20230425082933.84654-19-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL On the switch on the MT7988 SoC, there are only 4 PHYs. That's port 0 to 3. Set the internal phy cases to '0 ... 3'. There's no need to clear the config->supported_interfaces bitmap before reporting the supported interfaces as all bits in the bitmap will already be initialized to zero when the phylink_config structure is allocated. There's no code that would change the bitmap beforehand. Remove it. Fixes: 110c18bfed41 ("net: dsa: mt7530: introduce driver for MT7988 built-in switch") Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 468c50b3f43b..aee1e4d71547 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2532,10 +2532,8 @@ static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, struct phylink_config *config) { - phy_interface_zero(config->supported_interfaces); - switch (port) { - case 0 ... 4: /* Internal phy */ + case 0 ... 3: /* Internal phy */ __set_bit(PHY_INTERFACE_MODE_INTERNAL, config->supported_interfaces); break; From patchwork Tue Apr 25 08:29:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223052 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54FDEC77B71 for ; Tue, 25 Apr 2023 08:33:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233848AbjDYIdA (ORCPT ); Tue, 25 Apr 2023 04:33:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233617AbjDYIbt (ORCPT ); Tue, 25 Apr 2023 04:31:49 -0400 Received: from mail-ej1-x62a.google.com (mail-ej1-x62a.google.com [IPv6:2a00:1450:4864:20::62a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A00213F88; Tue, 25 Apr 2023 01:30:47 -0700 (PDT) Received: by mail-ej1-x62a.google.com with SMTP id a640c23a62f3a-956ff2399c9so938829066b.3; Tue, 25 Apr 2023 01:30:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411440; x=1685003440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1uLav40hri3eanK3Jy4AVy91JvuI98IGXe5BAzhG3qY=; b=cvjH75DPQqlRxJGSfXV8bb+spvakoCPO+pRgYvaHQhjszaR4HJIfty1kIxqdkvg507 /kmGLkGSTYoGmbMSdDzQaG9+PPXEADtQ4T3LOTnowyVyp+boUz166MNb4r9MS4IVaBCE 8CzFmkZtnCdxpmvkzxqpVsN0y2chhZfUo+WhJI7KldRU+TBQzt2inwO0+fEcHnJhZwlQ Bly5F3SodqWFsNQ2jB9pDnnCXnUKKJownQ9HUQhJV9vp9cUyNHNnADgGkl7D1qnmFrvt UUtQ/buQ5W63FzO+dmwUnIh/s/7F/dJ7r+2bo5QrFB3FVigVsnTCD+iNDgJDdWN+AdsK pdew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411440; x=1685003440; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1uLav40hri3eanK3Jy4AVy91JvuI98IGXe5BAzhG3qY=; b=LA9C+/flWixLw0W5nZRqYwXhCcBedHR3qU6Tg9Aa22JVQ9ROrKkXFUOxAArV/NAzhX G+Cf7bsbdpvQ2Qj3wuolXobbLJnYIbYmcVIB/MjL+v2putPZrv61jBvEgcBm0CdyWxVU z9KTabeEBnGYDk5WEVy41AQ36s219O9RuzMGrL6892novdcZodJ4JgEYzn/aHEVg8weK ajyLCR8yUqhJueBo4KYEx/uj+R4T0x4RUAwovVeA3RVqI9gV7gVQRkGtONQDzpz9kTrv xhTB5S1a7pB+NPWLYBUF84keKwtjv1JosYpGBp39pw4gLyBWIav+Bq2NtShLZch1AV1J 7QHQ== X-Gm-Message-State: AAQBX9f09vq6rf0m/Il55Aw1TnxfKYPBRzF6c8IY7J9pvLbmIj327ikk mXC4nsUqn6GtvHAdE4cA5E4= X-Google-Smtp-Source: AKy350ZKkzSKbtmxddOSln/bZb1aezgAR66i8vfy7x3dBj2ysqx42JxhlOsAxkxx3wSoJxv2IlopoA== X-Received: by 2002:a17:906:ecb7:b0:8b1:3467:d71b with SMTP id qh23-20020a170906ecb700b008b13467d71bmr12844134ejb.48.1682411439716; Tue, 25 Apr 2023 01:30:39 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:39 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 19/24] net: dsa: mt7530: remove .mac_port_config for MT7988 and make it optional Date: Tue, 25 Apr 2023 11:29:28 +0300 Message-Id: <20230425082933.84654-20-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL For the switch on the MT7988 SoC, the code in mac_port_config for MT7988 is not needed as the interface of the CPU port is already handled on mt7988_mac_port_get_caps(). Make .mac_port_config optional. Before calling priv->info->mac_port_config(), if there's no mac_port_config member in the priv->info table, exit mt753x_mac_config() successfully. Remove mac_port_config from the sanity check as the sanity check requires a pointer to a mac_port_config function to be non-NULL. This will fail for MT7988 as mac_port_config won't be a member of its info table. Signed-off-by: Arınç ÜNAL Co-authored-by: Daniel Golle Signed-off-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index aee1e4d71547..bdd3f63fe1ef 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2613,17 +2613,6 @@ static bool mt753x_is_mac_port(u32 port) return (port == 5 || port == 6); } -static int -mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, - phy_interface_t interface) -{ - if (dsa_is_cpu_port(ds, port) && - interface == PHY_INTERFACE_MODE_INTERNAL) - return 0; - - return -EINVAL; -} - static int mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) @@ -2664,6 +2653,9 @@ mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, { struct mt7530_priv *priv = ds->priv; + if (!priv->info->mac_port_config) + return 0; + return priv->info->mac_port_config(ds, port, mode, state->interface); } @@ -3107,7 +3099,6 @@ const struct mt753x_info mt753x_table[] = { .phy_write_c45 = mt7531_ind_c45_phy_write, .cpu_port_config = mt7988_cpu_port_config, .mac_port_get_caps = mt7988_mac_port_get_caps, - .mac_port_config = mt7988_mac_config, }, }; EXPORT_SYMBOL_GPL(mt753x_table); @@ -3135,8 +3126,7 @@ mt7530_probe_common(struct mt7530_priv *priv) * properly. */ if (!priv->info->sw_setup || !priv->info->phy_read_c22 || - !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps || - !priv->info->mac_port_config) + !priv->info->phy_write_c22 || !priv->info->mac_port_get_caps) return -EINVAL; priv->id = priv->info->id; From patchwork Tue Apr 25 08:29:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223053 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E7122C77B71 for ; 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Tue, 25 Apr 2023 01:30:42 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:41 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 20/24] net: dsa: mt7530: set interrupt register only for MT7530 Date: Tue, 25 Apr 2023 11:29:29 +0300 Message-Id: <20230425082933.84654-21-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL Setting this register related to interrupts is only needed for the MT7530 switch. Make an exclusive check to ensure this. Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle Tested-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index bdd3f63fe1ef..651c5803706b 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2034,7 +2034,7 @@ mt7530_setup_irq(struct mt7530_priv *priv) } /* This register must be set for MT7530 to properly fire interrupts */ - if (priv->id != ID_MT7531) + if (priv->id == ID_MT7530 || priv->id == ID_MT7621) mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, From patchwork Tue Apr 25 08:29:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223054 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D55C3C77B76 for ; Tue, 25 Apr 2023 08:33:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233862AbjDYIdF (ORCPT ); Tue, 25 Apr 2023 04:33:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233658AbjDYIbz (ORCPT ); Tue, 25 Apr 2023 04:31:55 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05782BB9E; Tue, 25 Apr 2023 01:30:50 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-94ef0a8546fso856486866b.1; Tue, 25 Apr 2023 01:30:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411444; x=1685003444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bmRjRa2oDkXUeWxPTzRhDOzTZE3SAeKxIwHwq/ISwAk=; b=DBYxGKSXdk4uA3rc4AG/6W1nPQOSSBfTQSUfvz3u+0nTc15ULzU2XtwR2YOP4zUuXB g9dS++jTvpO5p67Q07d0kgv7SzDm4IQ4hvGENfLo2H57sHdBeJsYsRMpW8Mw0XC8cQbW Stq/x6ac0sNU5tVHuVB6nC6sNIa6nERDXaWash7fmo39MQ0esUQ2bWE6Ky9VdbZkA2VJ cE7MUTi1Z7h1Hlbec1VbTRhrLvlok+BPOlWzrWK5h2vsszUL8svRvokAA/SJg2PEBGVg LtcBcBHQDcjl3qvGhE/6S0JncoFhs0mB86gcenQU2RizgrqSp8pa2toydLoG3528gEW2 +fEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411444; x=1685003444; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bmRjRa2oDkXUeWxPTzRhDOzTZE3SAeKxIwHwq/ISwAk=; b=kfN8e/ihW9P9eiiK6CZMCi53VhqlKbol7LUoJXr280zu6wcPd5UYUJG8ARj44dLIe0 1+8d6FNZ6BKOm/mvOnjOT7VI78pshnVSWUakn9egJ6FDISYUYFgM7qr1O5yglTs9rXOB tamtn2ooa+aHPpbyv3g0RH7cJw0jGiMwu7Bi3yncxp5Ta6d/Tzk7S7HPYZyeKadoULt2 eOkowVbWx4TYF1D43zaJRhfEfAv9GD6Ua971oWZ944cx8WHF5H/FglHO41THXfiD/rZo UIgvRu0G+MdgEcOc4ygRgngQy5op3cQHQ8NsAr/O1kV2ICXUvkCW954HKrZRD8HJP56G gnUA== X-Gm-Message-State: AAQBX9e52SaMgUEQyklJT9mJT9+tRE5FvamBVnnE2IUqWpH6qMorm20T XnvPlvcfhDqDSeTIFWfXUXQ= X-Google-Smtp-Source: AKy350aei+cFhuN1YP1tESRQQPsUNEL7nvZXcA6lySvdCWF8AKgLyZiUAp0rVgWehPNt7heQKfpNbA== X-Received: by 2002:a17:906:6009:b0:94d:69e0:6098 with SMTP id o9-20020a170906600900b0094d69e06098mr13994747ejj.45.1682411444450; Tue, 25 Apr 2023 01:30:44 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:44 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 21/24] net: dsa: mt7530: force link-down on MACs before reset on MT7530 Date: Tue, 25 Apr 2023 11:29:30 +0300 Message-Id: <20230425082933.84654-22-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL Force link-down on all MACs before internal reset. Let's follow suit commit 728c2af6ad8c ("net: mt7531: ensure all MACs are powered down before reset"). Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 651c5803706b..0bd38323e2b6 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2203,6 +2203,10 @@ mt7530_setup(struct dsa_switch *ds) return -EINVAL; } + /* Force link-down on all MACs before internal reset */ + for (i = 0; i < MT7530_NUM_PORTS; i++) + mt7530_write(priv, MT7530_PMCR_P(i), PMCR_FORCE_LNK); + /* Reset the switch through internal reset */ mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | From patchwork Tue Apr 25 08:29:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223055 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D9FEC77B71 for ; Tue, 25 Apr 2023 08:33:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233868AbjDYIdK (ORCPT ); Tue, 25 Apr 2023 04:33:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51404 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233660AbjDYIbz (ORCPT ); Tue, 25 Apr 2023 04:31:55 -0400 Received: from mail-ej1-x634.google.com (mail-ej1-x634.google.com [IPv6:2a00:1450:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7CDC66E97; Tue, 25 Apr 2023 01:30:50 -0700 (PDT) Received: by mail-ej1-x634.google.com with SMTP id a640c23a62f3a-953343581a4so804686566b.3; Tue, 25 Apr 2023 01:30:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1682411447; x=1685003447; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DcEecCSVjHrfHWDBYIR91HFhVC039k17zyIM1kkNbqQ=; b=h2YPjHK0YyO7kNZZERdjSTIaMFrALCP6RRpluyNBwxaPpj25GQO2pTQy4iso+ZgTWJ m2oELAWptlmGrWwGjYhskz6AsvghdBhJeVgvpptyhUFqAuZE7r64COHv8CMtaFtHmzVy r87HvoD3RlubhBui6i3/vQjE13pc19SUaVhcb3ZWf469GD0W2IlpUt3tu5a5M6kY3o5I r2dQCnOmZjFfnElUeJ2Jw5aE81g9+fdXfDaspf5ID0bsvjPI3enVLMPaX8ebhRM9czR9 Z2QiOyE4q2Wsz3ShuYCqg+GpoxFw3k0TfzImRWkRXNLg2SYldcGZG0BPLedGaQC+zpm/ zp+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682411447; x=1685003447; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DcEecCSVjHrfHWDBYIR91HFhVC039k17zyIM1kkNbqQ=; b=NTAxXk1oXAYmZ+6+5DHtbGTZoNcdiNpLjPzx1ltVdrX/fSjclRsCXQlEMLW51dqZ1w ng02NpxbNdSkV2GG7ItAlYKl6QxUlRelqKq0EFVlD6pe4sim9vGkf8Dh++lT0LghaBwB PPi1Rp2H6+b4IgBTEKpw9XCjj1h62X376a22s24ORB805C6XBivKS57Bj5dMsztWQI0o r7HiPWqnGSr9dphHypQIN2ul6YwJlkF+1BnXSqDdvzIt4k8BC/ld9Ujf+POPc8aGj1tI wsdI+6OjJPFklGF0tQCMcDvZXMt/yVaqQ4c7pDKuWNjg1n9BIJhTPPOiE/T30LJ6qvs1 y8AA== X-Gm-Message-State: AAQBX9e0JlG3Wvo/t6Kw5xub7DM/uXxIshP/LXYs1bD5ApsdRq8fqa7E nuCXxoa4RWMWHhnrAedMsX0= X-Google-Smtp-Source: AKy350abyOKtoHYjyLXq41z67rG+LsmeRwF0MW2/duqF1viLa2JB7MaaggWeLrdoUs9PCpq1t6qKzg== X-Received: by 2002:a17:907:c002:b0:932:ac6c:7ef9 with SMTP id ss2-20020a170907c00200b00932ac6c7ef9mr12445119ejc.22.1682411446671; Tue, 25 Apr 2023 01:30:46 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:46 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 22/24] net: dsa: mt7530: get rid of useless error returns on phylink code path Date: Tue, 25 Apr 2023 11:29:31 +0300 Message-Id: <20230425082933.84654-23-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL Remove error returns on the cases where they are already handled with the function the mac_port_get_caps member points to. mt7531_mac_config() is also called from mt7531_cpu_port_config() outside of phylink but the port and interface modes are already handled there. Change the functions and the mac_port_config function pointer to void now that there're no error returns anymore. Remove mt753x_is_mac_port() that used to help the said error returns. On mt7531_mac_config(), switch to if statements to simplify the code. Remove internal phy cases from mt753x_phylink_mac_config() as there is no configuration to be done for them. There's also no need to check the interface mode as that's already handled with the function the mac_port_get_caps member points to. Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL Acked-by: Daniel Golle Tested-by: Daniel Golle --- drivers/net/dsa/mt7530.c | 81 ++++++++-------------------------------- drivers/net/dsa/mt7530.h | 2 +- 2 files changed, 17 insertions(+), 66 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 0bd38323e2b6..02e6ba5a4403 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2550,7 +2550,7 @@ static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, } } -static int +static void mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { @@ -2561,22 +2561,14 @@ mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, } else if (port == 6) { mt7530_setup_port6(priv->ds, interface); } - - return 0; } -static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, - phy_interface_t interface, - struct phy_device *phydev) +static void mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, + phy_interface_t interface, + struct phy_device *phydev) { u32 val; - if (priv->p5_sgmii) { - dev_err(priv->dev, "RGMII mode is not available for port %d\n", - port); - return -EINVAL; - } - val = mt7530_read(priv, MT7531_CLKGEN_CTRL); val |= GP_CLK_EN; val &= ~GP_MODE_MASK; @@ -2604,20 +2596,14 @@ static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, case PHY_INTERFACE_MODE_RGMII_ID: break; default: - return -EINVAL; + break; } } - mt7530_write(priv, MT7531_CLKGEN_CTRL, val); - return 0; -} - -static bool mt753x_is_mac_port(u32 port) -{ - return (port == 5 || port == 6); + mt7530_write(priv, MT7531_CLKGEN_CTRL, val); } -static int +static void mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface) { @@ -2625,42 +2611,21 @@ mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, struct phy_device *phydev; struct dsa_port *dp; - if (!mt753x_is_mac_port(port)) { - dev_err(priv->dev, "port %d is not a MAC port\n", port); - return -EINVAL; - } - - switch (interface) { - case PHY_INTERFACE_MODE_RGMII: - case PHY_INTERFACE_MODE_RGMII_ID: - case PHY_INTERFACE_MODE_RGMII_RXID: - case PHY_INTERFACE_MODE_RGMII_TXID: + if (phy_interface_mode_is_rgmii(interface)) { dp = dsa_to_port(ds, port); phydev = dp->slave->phydev; - return mt7531_rgmii_setup(priv, port, interface, phydev); - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_NA: - case PHY_INTERFACE_MODE_1000BASEX: - case PHY_INTERFACE_MODE_2500BASEX: - /* handled in SGMII PCS driver */ - return 0; - default: - return -EINVAL; + mt7531_rgmii_setup(priv, port, interface, phydev); } - - return -EINVAL; } -static int +static void mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, const struct phylink_link_state *state) { struct mt7530_priv *priv = ds->priv; - if (!priv->info->mac_port_config) - return 0; - - return priv->info->mac_port_config(ds, port, mode, state->interface); + if (priv->info->mac_port_config) + priv->info->mac_port_config(ds, port, mode, state->interface); } static struct phylink_pcs * @@ -2689,30 +2654,18 @@ mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, u32 mcr_cur, mcr_new; switch (port) { - case 0 ... 4: /* Internal phy */ - if (state->interface != PHY_INTERFACE_MODE_GMII && - state->interface != PHY_INTERFACE_MODE_INTERNAL) - goto unsupported; - break; case 5: /* Port 5, can be used as a CPU port. */ if (priv->p5_configured) break; - if (mt753x_mac_config(ds, port, mode, state) < 0) - goto unsupported; + mt753x_mac_config(ds, port, mode, state); break; case 6: /* Port 6, can be used as a CPU port. */ if (priv->p6_configured) break; - if (mt753x_mac_config(ds, port, mode, state) < 0) - goto unsupported; + mt753x_mac_config(ds, port, mode, state); break; - default: -unsupported: - dev_err(ds->dev, "%s: unsupported %s port: %i\n", - __func__, phy_modes(state->interface), port); - return; } mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); @@ -2805,7 +2758,6 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port) struct mt7530_priv *priv = ds->priv; phy_interface_t interface; int speed; - int ret; switch (port) { case 5: @@ -2830,9 +2782,8 @@ mt7531_cpu_port_config(struct dsa_switch *ds, int port) else speed = SPEED_1000; - ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); - if (ret) - return ret; + mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); + mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPU_PORT_SETTING(priv->id)); mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index f7a504e4c17b..b7f80a487073 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -722,7 +722,7 @@ struct mt753x_info { void (*mac_port_validate)(struct dsa_switch *ds, int port, phy_interface_t interface, unsigned long *supported); - int (*mac_port_config)(struct dsa_switch *ds, int port, + void (*mac_port_config)(struct dsa_switch *ds, int port, unsigned int mode, phy_interface_t interface); }; From patchwork Tue Apr 25 08:29:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223057 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB44DC6FD18 for ; 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Tue, 25 Apr 2023 01:30:48 -0700 (PDT) Received: from arinc9-PC.lan ([149.91.1.15]) by smtp.gmail.com with ESMTPSA id mc2-20020a170906eb4200b0094ca077c985sm6439028ejb.213.2023.04.25.01.30.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 01:30:48 -0700 (PDT) From: arinc9.unal@gmail.com X-Google-Original-From: arinc.unal@arinc9.com To: Sean Wang , Landen Chao , DENG Qingfang , Daniel Golle , Andrew Lunn , Florian Fainelli , Vladimir Oltean , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 23/24] net: dsa: mt7530: rename p5_intf_sel and use only for MT7530 switch Date: Tue, 25 Apr 2023 11:29:32 +0300 Message-Id: <20230425082933.84654-24-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL The p5_intf_sel pointer is used to store the information of whether PHY muxing is used or not. PHY muxing is a feature specific to port 5 of the MT7530 switch. Do not use it for other switch models. Rename the pointer to p5_mode to store the mode the port is being used in. Rename the p5_interface_select enum to mt7530_p5_mode, the string representation to mt7530_p5_mode_str, and the enum elements. If PHY muxing is not detected, the default mode, GMAC5, will be used. Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 61 ++++++++++++++++------------------------ drivers/net/dsa/mt7530.h | 15 +++++----- 2 files changed, 32 insertions(+), 44 deletions(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 02e6ba5a4403..62e55df273cc 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -873,19 +873,15 @@ mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) return 0; } -static const char *p5_intf_modes(unsigned int p5_interface) -{ - switch (p5_interface) { - case P5_DISABLED: - return "DISABLED"; - case P5_INTF_SEL_PHY_P0: - return "PHY P0"; - case P5_INTF_SEL_PHY_P4: - return "PHY P4"; - case P5_INTF_SEL_GMAC5: - return "GMAC5"; +static const char *mt7530_p5_mode_str(unsigned int mode) +{ + switch (mode) { + case MUX_PHY_P0: + return "MUX PHY P0"; + case MUX_PHY_P4: + return "MUX PHY P4"; default: - return "unknown"; + return "GMAC5"; } } @@ -902,23 +898,21 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; - switch (priv->p5_intf_sel) { - case P5_INTF_SEL_PHY_P0: - /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ + switch (priv->p5_mode) { + case MUX_PHY_P0: + /* MUX_PHY_P0: P0 -> P5 -> SoC MAC */ val |= MHWTRAP_PHY0_SEL; fallthrough; - case P5_INTF_SEL_PHY_P4: - /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ + case MUX_PHY_P4: + /* MUX_PHY_P4: P4 -> P5 -> SoC MAC */ val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; /* Setup the MAC by default for the cpu port */ mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); break; - case P5_INTF_SEL_GMAC5: - /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ - val &= ~MHWTRAP_P5_DIS; - break; default: + /* GMAC5: P5 -> SoC MAC or external PHY */ + val &= ~MHWTRAP_P5_DIS; break; } @@ -942,8 +936,8 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) mt7530_write(priv, MT7530_MHWTRAP, val); - dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", - val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); + dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, mode=%s, phy-mode=%s\n", val, + mt7530_p5_mode_str(priv->p5_mode), phy_modes(interface)); mutex_unlock(&priv->reg_mutex); } @@ -2261,13 +2255,11 @@ mt7530_setup(struct dsa_switch *ds) if (ret) return ret; - /* Setup port 5 */ - if (!dsa_is_unused_port(ds, 5)) { - priv->p5_intf_sel = P5_INTF_SEL_GMAC5; - } else { + /* Check for PHY muxing on port 5 */ + if (dsa_is_unused_port(ds, 5)) { /* Scan the ethernet nodes. Look for GMAC1, lookup the used PHY. - * Set priv->p5_intf_sel to the appropriate value if PHY muxing - * is detected. + * Set priv->p5_mode to the appropriate value if PHY muxing is + * detected. */ for_each_child_of_node(dn, mac_np) { if (!of_device_is_compatible(mac_np, @@ -2291,17 +2283,17 @@ mt7530_setup(struct dsa_switch *ds) } id = of_mdio_parse_addr(ds->dev, phy_node); if (id == 0) - priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; + priv->p5_mode = MUX_PHY_P0; if (id == 4) - priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; + priv->p5_mode = MUX_PHY_P4; } of_node_put(mac_np); of_node_put(phy_node); break; } - if (priv->p5_intf_sel == P5_INTF_SEL_PHY_P0 || - priv->p5_intf_sel == P5_INTF_SEL_PHY_P4) + if (priv->p5_mode == MUX_PHY_P0 || + priv->p5_mode == MUX_PHY_P4) mt7530_setup_port5(ds, interface); } @@ -2438,9 +2430,6 @@ mt7531_setup(struct dsa_switch *ds) MT7531_EXT_P_MDIO_12); } - if (!dsa_is_unused_port(ds, 5)) - priv->p5_intf_sel = P5_INTF_SEL_GMAC5; - mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, MT7531_GPIO0_INTERRUPT); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index b7f80a487073..216081fb1c12 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -673,12 +673,11 @@ struct mt7530_port { struct phylink_pcs *sgmii_pcs; }; -/* Port 5 interface select definitions */ -enum p5_interface_select { - P5_DISABLED, - P5_INTF_SEL_PHY_P0, - P5_INTF_SEL_PHY_P4, - P5_INTF_SEL_GMAC5, +/* Port 5 mode definitions of the MT7530 switch */ +enum mt7530_p5_mode { + GMAC5, + MUX_PHY_P0, + MUX_PHY_P4, }; struct mt7530_priv; @@ -746,7 +745,7 @@ struct mt753x_info { * is already configured * @p5_configured: Flag for distinguishing if port 5 of the MT7531 switch * is already configured - * @p5_intf_sel: Holding the current port 5 interface select + * @p5_mode: Holding the current mode of port 5 of the MT7530 switch * @p5_sgmii: Flag for distinguishing if port 5 of the MT7531 switch * has got SGMII * @irq: IRQ number of the switch @@ -768,7 +767,7 @@ struct mt7530_priv { bool mcm; bool p6_configured; bool p5_configured; - enum p5_interface_select p5_intf_sel; + enum mt7530_p5_mode p5_mode; bool p5_sgmii; u8 mirror_rx; u8 mirror_tx; From patchwork Tue Apr 25 08:29:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= X-Patchwork-Id: 13223056 X-Patchwork-Delegate: kuba@kernel.org Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D7ED3C77B61 for ; Tue, 25 Apr 2023 08:33:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233739AbjDYIdO (ORCPT ); Tue, 25 Apr 2023 04:33:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50726 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233741AbjDYIb5 (ORCPT ); Tue, 25 Apr 2023 04:31:57 -0400 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7498F7ECE; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Matthias Brugger , AngeloGioacchino Del Regno , Russell King Cc: =?utf-8?b?QXLEsW7DpyDDnE5BTA==?= , Richard van Schagen , Richard van Schagen , Frank Wunderlich , Bartel Eerdekens , erkin.bozoglu@xeront.com, netdev@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org Subject: [PATCH net-next 24/24] net: dsa: mt7530: run mt7530_pll_setup() only with 40 MHz XTAL Date: Tue, 25 Apr 2023 11:29:33 +0300 Message-Id: <20230425082933.84654-25-arinc.unal@arinc9.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425082933.84654-1-arinc.unal@arinc9.com> References: <20230425082933.84654-1-arinc.unal@arinc9.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org X-Patchwork-Delegate: kuba@kernel.org From: Arınç ÜNAL The code on mt7530_pll_setup() needs to be run only on the MT7530 switch with a 40 MHz oscillator. Introduce a check to do this. Link: https://github.com/BPI-SINOVOIP/BPI-R2-bsp/blob/4a5dd143f2172ec97a2872fa29c7c4cd520f45b5/linux-mt/drivers/net/ethernet/mediatek/gsw_mt7623.c#L1039 Tested-by: Arınç ÜNAL Signed-off-by: Arınç ÜNAL --- drivers/net/dsa/mt7530.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 62e55df273cc..e079b45fad07 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -2206,7 +2206,8 @@ mt7530_setup(struct dsa_switch *ds) SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | SYS_CTRL_REG_RST); - mt7530_pll_setup(priv); + if (xtal == HWTRAP_XTAL_40MHZ) + mt7530_pll_setup(priv); /* Lower P5 RGMII Tx driving, 8mA */ mt7530_write(priv, MT7530_IO_DRV_CR,