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Tue, 25 Apr 2023 06:45:32 -0700 (PDT) Received: from prevas-ravi.prevas.se ([81.216.59.226]) by smtp.gmail.com with ESMTPSA id f10-20020a170906048a00b0094eeea5c649sm6806822eja.114.2023.04.25.06.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 06:45:32 -0700 (PDT) From: Rasmus Villemoes To: Mark Brown , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: Marc Kleine-Budde , Rasmus Villemoes , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] spi: spi-imx: use "controller" variable consistently in spi_imx_probe() Date: Tue, 25 Apr 2023 15:45:25 +0200 Message-Id: <20230425134527.483607-2-linux@rasmusvillemoes.dk> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425134527.483607-1-linux@rasmusvillemoes.dk> References: <20230425134527.483607-1-linux@rasmusvillemoes.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230425_064538_246459_98E05955 X-CRM114-Status: GOOD ( 13.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Near the top of the function, spi_imx->controller is set to controller (and is of course never modified again). The rest of the function uses a mix of the two expressions. For consistency, readability and better code generation, drop all the spi_imx-> indirections. Signed-off-by: Rasmus Villemoes --- drivers/spi/spi-imx.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index e4ccd0c329d0..6fa53a82674a 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -1725,20 +1725,20 @@ static int spi_imx_probe(struct platform_device *pdev) else controller->num_chipselect = 3; - spi_imx->controller->transfer_one = spi_imx_transfer_one; - spi_imx->controller->setup = spi_imx_setup; - spi_imx->controller->cleanup = spi_imx_cleanup; - spi_imx->controller->prepare_message = spi_imx_prepare_message; - spi_imx->controller->unprepare_message = spi_imx_unprepare_message; - spi_imx->controller->slave_abort = spi_imx_slave_abort; - spi_imx->controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; + controller->transfer_one = spi_imx_transfer_one; + controller->setup = spi_imx_setup; + controller->cleanup = spi_imx_cleanup; + controller->prepare_message = spi_imx_prepare_message; + controller->unprepare_message = spi_imx_unprepare_message; + controller->slave_abort = spi_imx_slave_abort; + controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) - spi_imx->controller->mode_bits |= SPI_LOOP | SPI_READY; + controller->mode_bits |= SPI_LOOP | SPI_READY; if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) - spi_imx->controller->mode_bits |= SPI_RX_CPHA_FLIP; + controller->mode_bits |= SPI_RX_CPHA_FLIP; if (is_imx51_ecspi(spi_imx) && device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) @@ -1747,7 +1747,7 @@ static int spi_imx_probe(struct platform_device *pdev) * setting the burst length to the word size. This is * considerably faster than manually controlling the CS. */ - spi_imx->controller->mode_bits |= SPI_CS_WORD; + controller->mode_bits |= SPI_CS_WORD; spi_imx->spi_drctl = spi_drctl; From patchwork Tue Apr 25 13:45:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 13223356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4A6BEC77B76 for ; Tue, 25 Apr 2023 13:46:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Tue, 25 Apr 2023 06:45:34 -0700 (PDT) Received: from prevas-ravi.prevas.se ([81.216.59.226]) by smtp.gmail.com with ESMTPSA id f10-20020a170906048a00b0094eeea5c649sm6806822eja.114.2023.04.25.06.45.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 06:45:34 -0700 (PDT) From: Rasmus Villemoes To: Mark Brown , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: Marc Kleine-Budde , Rasmus Villemoes , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] spi: spi-imx: set max_native_cs for imx51/imx53/imx6 variants Date: Tue, 25 Apr 2023 15:45:26 +0200 Message-Id: <20230425134527.483607-3-linux@rasmusvillemoes.dk> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425134527.483607-1-linux@rasmusvillemoes.dk> References: <20230425134527.483607-1-linux@rasmusvillemoes.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230425_064538_196716_4B510199 X-CRM114-Status: GOOD ( 12.47 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The ecspi IP block on imx51/imx53/imx6 have four native chip selects. Tell that to the spi core so that any non-gpio chip selects get validated against that upper bound. Also set the SPI_MASTER_GPIO_SS so that the core verifies that, in the case where both native and gpio chip selects are in use, there is at least one leftover native chip select (or "channel", in the ecspi language) for use by the slaves sitting on gpio chip selects. Signed-off-by: Rasmus Villemoes --- drivers/spi/spi-imx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 6fa53a82674a..e8f7afbd9847 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -1749,6 +1749,11 @@ static int spi_imx_probe(struct platform_device *pdev) */ controller->mode_bits |= SPI_CS_WORD; + if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) { + controller->max_native_cs = 4; + controller->flags |= SPI_MASTER_GPIO_SS; + } + spi_imx->spi_drctl = spi_drctl; init_completion(&spi_imx->xfer_done); From patchwork Tue Apr 25 13:45:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 13223358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 516D7C77B61 for ; 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Tue, 25 Apr 2023 06:45:35 -0700 (PDT) From: Rasmus Villemoes To: Mark Brown , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: Marc Kleine-Budde , Rasmus Villemoes , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] spi: spi-imx: fix use of more than four chipselects Date: Tue, 25 Apr 2023 15:45:27 +0200 Message-Id: <20230425134527.483607-4-linux@rasmusvillemoes.dk> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425134527.483607-1-linux@rasmusvillemoes.dk> References: <20230425134527.483607-1-linux@rasmusvillemoes.dk> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230425_064539_779609_AE2CDBE0 X-CRM114-Status: GOOD ( 18.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, the spi->chip_select is used unconditionally in code such as /* set chip select to use */ ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); and if (spi->mode & SPI_CPHA) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); else cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); with these macros being #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) However, the CHANNEL_SELECT field in the control register is only two bits wide, so when spi->chip_select >= 4, we end up writing garbage into the BURST_LENGTH field. Similarly, there are only four bits in the SCLK_PHA field, so the code above ends up actually modifying bits in the SCLK_POL (or higher) field. The scrambling of the BURST_LENGTH field itself is probably benign, since that is explicitly completely initialized later, in ->prepare_transfer. But, since we effectively write (spi->chip_select & 3) into the CHANNEL_SELECT field, that value is what the IP block then uses to determine which bits of the configuration register control phase, polarity etc., and those bits are not properly initialized, so communication with the spi device completely fails. Fix this by using the ->unused_native_cs value as channel number for any spi device which uses a gpio as chip select. Signed-off-by: Rasmus Villemoes --- drivers/spi/spi-imx.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index e8f7afbd9847..569a5132f324 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -504,6 +504,13 @@ static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); } +static int mx51_ecspi_channel(const struct spi_device *spi) +{ + if (!spi->cs_gpiod) + return spi->chip_select; + return spi->controller->unused_native_cs; +} + static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, struct spi_message *msg) { @@ -514,6 +521,7 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, u32 testreg, delay; u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); u32 current_cfg = cfg; + int channel = mx51_ecspi_channel(spi); /* set Master or Slave mode */ if (spi_imx->slave_mode) @@ -528,7 +536,7 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); /* set chip select to use */ - ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); + ctrl |= MX51_ECSPI_CTRL_CS(channel); /* * The ctrl register must be written first, with the EN bit set other @@ -549,22 +557,22 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, * BURST_LENGTH + 1 bits are received */ if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) - cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel); else - cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel); if (spi->mode & SPI_CPOL) { - cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); - cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel); + cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel); } else { - cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); - cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel); + cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel); } if (spi->mode & SPI_CS_HIGH) - cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel); else - cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel); if (cfg == current_cfg) return 0; @@ -609,14 +617,15 @@ static void mx51_configure_cpha(struct spi_imx_data *spi_imx, bool cpha = (spi->mode & SPI_CPHA); bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); + int channel = mx51_ecspi_channel(spi); /* Flip cpha logical value iff flip_cpha */ cpha ^= flip_cpha; if (cpha) - cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel); else - cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel); writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); }