From patchwork Tue Apr 25 13:45:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 13223360 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D1AC0C6FD18 for ; Tue, 25 Apr 2023 13:45:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234269AbjDYNpg (ORCPT ); Tue, 25 Apr 2023 09:45:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42074 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229915AbjDYNpf (ORCPT ); Tue, 25 Apr 2023 09:45:35 -0400 Received: from mail-ej1-x635.google.com (mail-ej1-x635.google.com [IPv6:2a00:1450:4864:20::635]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A1C914453 for ; Tue, 25 Apr 2023 06:45:34 -0700 (PDT) Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-94f4b911570so875213266b.0 for ; Tue, 25 Apr 2023 06:45:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rasmusvillemoes.dk; s=google; t=1682430333; x=1685022333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=E4sRdWC2cDHZjejBYhhOCUr1iFuyu6C1Fz1Mden7vTg=; b=Z+SKr1Ux8TXyogmCHsNc4/c9jBYnw/ezmC0VGtD1fZH6kazcZAF/QNVU+NXutbp4tt gDMLMyvaf3VlLPBJN6PxnB9PSBlCbSGoN3hQ67YfPy85ej2Efk2mrrPj5C3R+yEeu5bj b+ID2oi1EGUK8rhRUgZpj6hu8zzOpzOdayHS8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682430333; x=1685022333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=E4sRdWC2cDHZjejBYhhOCUr1iFuyu6C1Fz1Mden7vTg=; b=UUPqbIuFf39IzsEehZzDQd57E1FKlUmwCWtjmtww+L6MnU8yjpAyeTnWdLjgVYqgpW KxOy2IVY+LcgWyzKhDQm3oifnJKKUyn/+9vyIJUlgl0Df85jM9TJ1GxdUb55FUcrnfw1 TrP1xtQ4SayOhJ8uJxRV6hmPEhVEP+J6/9PFNEec8cmiDGBP3Wbsw3oOy9I31a5zQ5YR JYSJfysD5jpLg4DFtqEnetM/5vfMFxxGzTWsogdd/j6a3gDRy29yyxv2eNXzPLeipxD/ vLhUb4r1k/+01NhS2wKkeZI8ZSew8s2tQuQvUOuNf7kW2wDKbgGeXYGmBrl6KZu71rE4 QVjQ== X-Gm-Message-State: AAQBX9dUTD4ZxRLMSbC+n95OV5p8tHDpROWJYEdGgtJuFiDB9RCG1DF1 5I7ydLpgDKacR+jPkDwnrXWPAg== X-Google-Smtp-Source: AKy350bel0saz0NNkLMsNuHNUBFgQRefYyEt6zhsCW5VrBurn20Uw4hMW3itsS+i0T2zY7/JuQWDyw== X-Received: by 2002:a17:906:7686:b0:956:f4f8:23b6 with SMTP id o6-20020a170906768600b00956f4f823b6mr13168543ejm.43.1682430332774; Tue, 25 Apr 2023 06:45:32 -0700 (PDT) Received: from prevas-ravi.prevas.se ([81.216.59.226]) by smtp.gmail.com with ESMTPSA id f10-20020a170906048a00b0094eeea5c649sm6806822eja.114.2023.04.25.06.45.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 06:45:32 -0700 (PDT) From: Rasmus Villemoes To: Mark Brown , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: Marc Kleine-Budde , Rasmus Villemoes , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 1/3] spi: spi-imx: use "controller" variable consistently in spi_imx_probe() Date: Tue, 25 Apr 2023 15:45:25 +0200 Message-Id: <20230425134527.483607-2-linux@rasmusvillemoes.dk> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425134527.483607-1-linux@rasmusvillemoes.dk> References: <20230425134527.483607-1-linux@rasmusvillemoes.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Near the top of the function, spi_imx->controller is set to controller (and is of course never modified again). The rest of the function uses a mix of the two expressions. For consistency, readability and better code generation, drop all the spi_imx-> indirections. Signed-off-by: Rasmus Villemoes --- drivers/spi/spi-imx.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index e4ccd0c329d0..6fa53a82674a 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -1725,20 +1725,20 @@ static int spi_imx_probe(struct platform_device *pdev) else controller->num_chipselect = 3; - spi_imx->controller->transfer_one = spi_imx_transfer_one; - spi_imx->controller->setup = spi_imx_setup; - spi_imx->controller->cleanup = spi_imx_cleanup; - spi_imx->controller->prepare_message = spi_imx_prepare_message; - spi_imx->controller->unprepare_message = spi_imx_unprepare_message; - spi_imx->controller->slave_abort = spi_imx_slave_abort; - spi_imx->controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; + controller->transfer_one = spi_imx_transfer_one; + controller->setup = spi_imx_setup; + controller->cleanup = spi_imx_cleanup; + controller->prepare_message = spi_imx_prepare_message; + controller->unprepare_message = spi_imx_unprepare_message; + controller->slave_abort = spi_imx_slave_abort; + controller->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_NO_CS; if (is_imx35_cspi(spi_imx) || is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) - spi_imx->controller->mode_bits |= SPI_LOOP | SPI_READY; + controller->mode_bits |= SPI_LOOP | SPI_READY; if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) - spi_imx->controller->mode_bits |= SPI_RX_CPHA_FLIP; + controller->mode_bits |= SPI_RX_CPHA_FLIP; if (is_imx51_ecspi(spi_imx) && device_property_read_u32(&pdev->dev, "cs-gpios", NULL)) @@ -1747,7 +1747,7 @@ static int spi_imx_probe(struct platform_device *pdev) * setting the burst length to the word size. This is * considerably faster than manually controlling the CS. */ - spi_imx->controller->mode_bits |= SPI_CS_WORD; + controller->mode_bits |= SPI_CS_WORD; spi_imx->spi_drctl = spi_drctl; From patchwork Tue Apr 25 13:45:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 13223361 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00CA4C6FD18 for ; Tue, 25 Apr 2023 13:45:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234274AbjDYNpj (ORCPT ); Tue, 25 Apr 2023 09:45:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234266AbjDYNpi (ORCPT ); Tue, 25 Apr 2023 09:45:38 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0815A1447E for ; Tue, 25 Apr 2023 06:45:36 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id a640c23a62f3a-953343581a4so860756666b.3 for ; Tue, 25 Apr 2023 06:45:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rasmusvillemoes.dk; s=google; t=1682430334; x=1685022334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zRgabKLq7eTacDKoRbI9FK/SG7BfFMCRKhP9HGH7/VI=; b=DpdsldsksNbrlYrHx72q3FsmVTygzQ8+ILEy/6Z47oNp9+CIsnm7sxSovUbiQbZgg7 imHgDTz+AF0pXiJXTeaGHUgYJ3ib0U2en5rmsPCF0yP23sLsX4UntZCS+HMGFgBqxlkA Cj5e7wrWZ+8OKjCeMrv7BQItLrjPiqb0hugP8= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682430334; x=1685022334; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zRgabKLq7eTacDKoRbI9FK/SG7BfFMCRKhP9HGH7/VI=; b=F14w9f7NyC3aNNSVASmBw0rtRh83t4F6lYV+yz/9aFhjLwpdOPW5LD47WHyCYQiq65 AhTjd9WLc9QjSv7SWsOzWTwA2Ydkd/KmauIR+Iwx6uAJeOEFhIfUsv/iQMEEN0vWMIrC p7LFZNdCflxfO5ZYapZi7dC9WJUVYnA2/gaJXGNjFcTjOGegKGjOZC0cMTx4Rx31YtoS SRhcqyNcfG3A8ZfTClBNm6mp6B67B0l44rodEUduXwUynhxOvugPVSOJtm0J8oVu2D/Z iJfQiBKoFlK09wW3B68ZoXru4bWttubIwyL6+8KU9BWF5THtHAbJrla45VjJK3WQQKOo C0sg== X-Gm-Message-State: AAQBX9dmhAUU8fvA+CHyHR3W06NPjbdhURZLuVfqyg5mao7ukIfZrBlS 4K0jsEjZcTnGw/nw20JcqMpq4XGIOq0Ibagsji+WD0BG X-Google-Smtp-Source: AKy350Z83jsGizwNJRA+mohLxhjiEvtuoiSejIRimuqtdjKMN2jPVPuP7+Lhh1bC8E1iH8chq3akuw== X-Received: by 2002:a17:907:7e9c:b0:957:28b2:560a with SMTP id qb28-20020a1709077e9c00b0095728b2560amr13750121ejc.46.1682430334339; Tue, 25 Apr 2023 06:45:34 -0700 (PDT) Received: from prevas-ravi.prevas.se ([81.216.59.226]) by smtp.gmail.com with ESMTPSA id f10-20020a170906048a00b0094eeea5c649sm6806822eja.114.2023.04.25.06.45.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 06:45:34 -0700 (PDT) From: Rasmus Villemoes To: Mark Brown , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: Marc Kleine-Budde , Rasmus Villemoes , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 2/3] spi: spi-imx: set max_native_cs for imx51/imx53/imx6 variants Date: Tue, 25 Apr 2023 15:45:26 +0200 Message-Id: <20230425134527.483607-3-linux@rasmusvillemoes.dk> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425134527.483607-1-linux@rasmusvillemoes.dk> References: <20230425134527.483607-1-linux@rasmusvillemoes.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org The ecspi IP block on imx51/imx53/imx6 have four native chip selects. Tell that to the spi core so that any non-gpio chip selects get validated against that upper bound. Also set the SPI_MASTER_GPIO_SS so that the core verifies that, in the case where both native and gpio chip selects are in use, there is at least one leftover native chip select (or "channel", in the ecspi language) for use by the slaves sitting on gpio chip selects. Signed-off-by: Rasmus Villemoes --- drivers/spi/spi-imx.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 6fa53a82674a..e8f7afbd9847 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -1749,6 +1749,11 @@ static int spi_imx_probe(struct platform_device *pdev) */ controller->mode_bits |= SPI_CS_WORD; + if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx)) { + controller->max_native_cs = 4; + controller->flags |= SPI_MASTER_GPIO_SS; + } + spi_imx->spi_drctl = spi_drctl; init_completion(&spi_imx->xfer_done); From patchwork Tue Apr 25 13:45:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rasmus Villemoes X-Patchwork-Id: 13223362 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68734C77B61 for ; Tue, 25 Apr 2023 13:45:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233600AbjDYNpu (ORCPT ); Tue, 25 Apr 2023 09:45:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234278AbjDYNpl (ORCPT ); Tue, 25 Apr 2023 09:45:41 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B532413FB3 for ; Tue, 25 Apr 2023 06:45:37 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id 4fb4d7f45d1cf-506767f97f8so10006495a12.1 for ; Tue, 25 Apr 2023 06:45:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rasmusvillemoes.dk; s=google; t=1682430336; x=1685022336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Al0zqUJCRs8AI5Sc47A1KMBnQC63vKqupk6DIofDhiM=; b=ITM1rBhaC1OkA8L7qspcDJ8xbkZrOsaT0dCfP5BjuAZtPW6BBgMTvTknoRUzcp9oGq tRqmd/cXl4V2QIGzwRFD4JMcMxoOdclL3ggk62TG+Qpvg2hU/UqbKiEhRvzwvrY82/G/ ekhBg3pKTFerlph1uFfJZDo9PptMNJ6QMRbtQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682430336; x=1685022336; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Al0zqUJCRs8AI5Sc47A1KMBnQC63vKqupk6DIofDhiM=; b=YJIN/f+UDcm4lbdYJlyDDMWbEYtJQT24S5In5xh/6IyjGPxtkKaie66FEhy05qk0mj BHT8qqrm9rY9a304hcIFVv9eRDgnPptPgt3jBYJ6dNN4mvGL6XBpr0kvJwbi89+81iCU c2ykFRDmzBEHE25r1BeIPQlE0YDnoUzHYoATcknn/3on4hPmPXCUnMl7NYzs9cfc4Pwv Oy6Fp2pg4tXDNWcVU9nS1bwsGlocheVtsujT6bDRaFr8NBOquQOiD7qnrFEybfMyBVvp q5Qc2CHN1ADjPM0KGrNebyy9VuhPKdv23vOc0GnJ2UWEAe9g6wjeEcKqP3KuuzwcpJh2 WAWA== X-Gm-Message-State: AAQBX9cxPW07UebTGs2TUwMAC/O+yEbVT9vtILY5a6CKFsapvUhuHvLD XtdvzVUOnOGNBkNhJKD2jZ2IHA== X-Google-Smtp-Source: AKy350aKN7c3TBlSHw8bGq2LBpYoNswxL+Q4j51QbggX6/tE0dIImeRVxwOgA/3I0vsBbihspOdvSg== X-Received: by 2002:a17:906:8a44:b0:94f:553:6fd6 with SMTP id gx4-20020a1709068a4400b0094f05536fd6mr13433197ejc.24.1682430335987; Tue, 25 Apr 2023 06:45:35 -0700 (PDT) Received: from prevas-ravi.prevas.se ([81.216.59.226]) by smtp.gmail.com with ESMTPSA id f10-20020a170906048a00b0094eeea5c649sm6806822eja.114.2023.04.25.06.45.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Apr 2023 06:45:35 -0700 (PDT) From: Rasmus Villemoes To: Mark Brown , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team Cc: Marc Kleine-Budde , Rasmus Villemoes , linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH 3/3] spi: spi-imx: fix use of more than four chipselects Date: Tue, 25 Apr 2023 15:45:27 +0200 Message-Id: <20230425134527.483607-4-linux@rasmusvillemoes.dk> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20230425134527.483607-1-linux@rasmusvillemoes.dk> References: <20230425134527.483607-1-linux@rasmusvillemoes.dk> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Currently, the spi->chip_select is used unconditionally in code such as /* set chip select to use */ ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); and if (spi->mode & SPI_CPHA) cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); else cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); with these macros being #define MX51_ECSPI_CTRL_CS(cs) ((cs) << 18) #define MX51_ECSPI_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0)) However, the CHANNEL_SELECT field in the control register is only two bits wide, so when spi->chip_select >= 4, we end up writing garbage into the BURST_LENGTH field. Similarly, there are only four bits in the SCLK_PHA field, so the code above ends up actually modifying bits in the SCLK_POL (or higher) field. The scrambling of the BURST_LENGTH field itself is probably benign, since that is explicitly completely initialized later, in ->prepare_transfer. But, since we effectively write (spi->chip_select & 3) into the CHANNEL_SELECT field, that value is what the IP block then uses to determine which bits of the configuration register control phase, polarity etc., and those bits are not properly initialized, so communication with the spi device completely fails. Fix this by using the ->unused_native_cs value as channel number for any spi device which uses a gpio as chip select. Signed-off-by: Rasmus Villemoes --- drivers/spi/spi-imx.c | 31 ++++++++++++++++++++----------- 1 file changed, 20 insertions(+), 11 deletions(-) diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index e8f7afbd9847..569a5132f324 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c @@ -504,6 +504,13 @@ static void mx51_ecspi_disable(struct spi_imx_data *spi_imx) writel(ctrl, spi_imx->base + MX51_ECSPI_CTRL); } +static int mx51_ecspi_channel(const struct spi_device *spi) +{ + if (!spi->cs_gpiod) + return spi->chip_select; + return spi->controller->unused_native_cs; +} + static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, struct spi_message *msg) { @@ -514,6 +521,7 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, u32 testreg, delay; u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); u32 current_cfg = cfg; + int channel = mx51_ecspi_channel(spi); /* set Master or Slave mode */ if (spi_imx->slave_mode) @@ -528,7 +536,7 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, ctrl |= MX51_ECSPI_CTRL_DRCTL(spi_imx->spi_drctl); /* set chip select to use */ - ctrl |= MX51_ECSPI_CTRL_CS(spi->chip_select); + ctrl |= MX51_ECSPI_CTRL_CS(channel); /* * The ctrl register must be written first, with the EN bit set other @@ -549,22 +557,22 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx, * BURST_LENGTH + 1 bits are received */ if (spi_imx->slave_mode && is_imx53_ecspi(spi_imx)) - cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SBBCTRL(channel); else - cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SBBCTRL(channel); if (spi->mode & SPI_CPOL) { - cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); - cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SCLKPOL(channel); + cfg |= MX51_ECSPI_CONFIG_SCLKCTL(channel); } else { - cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select); - cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SCLKPOL(channel); + cfg &= ~MX51_ECSPI_CONFIG_SCLKCTL(channel); } if (spi->mode & SPI_CS_HIGH) - cfg |= MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SSBPOL(channel); else - cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SSBPOL(channel); if (cfg == current_cfg) return 0; @@ -609,14 +617,15 @@ static void mx51_configure_cpha(struct spi_imx_data *spi_imx, bool cpha = (spi->mode & SPI_CPHA); bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only; u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG); + int channel = mx51_ecspi_channel(spi); /* Flip cpha logical value iff flip_cpha */ cpha ^= flip_cpha; if (cpha) - cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + cfg |= MX51_ECSPI_CONFIG_SCLKPHA(channel); else - cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select); + cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(channel); writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG); }