From patchwork Thu May 4 18:14:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13231489 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 46F04C7EE21 for ; Thu, 4 May 2023 18:16:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=o0wMiGfAnjUSKGQeC9oXXNOtiR2UJp+dKUcYlqkn3kI=; b=ekc8Jw9BSdOyaF Vmd71fPTrVNr6jPI7+lN2LSe91pXBpJ4Uweq9DQf2qyJFYlqZ1x3h2Gqp8C2xgCsSr2F3Poue6CYs M+ITatUmAtOHmnQRtGC0V8fRtRtQcuLgwdDkC+JClq4D4ML1mMzPDYOHJKc0HqJTWPGZO0s91eLqe CNuxAU79Sj1F/PEPGczdFu8c03aYYfH01jEng4YbvTm9zqTa7g43p2mDr/3n0c/Wfp2P5hp52SFep ZunU/4Dkddvt3qeWBme5dIGaYXMi0GjcrlNJMhWRtkEX7LVUKPp88rGaw0fjlyz2QKl443jV2gizy cCAmZGC94MEc6RBYbRvA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pudUO-008VQ4-2X; Thu, 04 May 2023 18:15:36 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pudUM-008VPB-13 for linux-riscv@lists.infradead.org; Thu, 04 May 2023 18:15:35 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 93C0263380; Thu, 4 May 2023 18:15:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F597C4339B; Thu, 4 May 2023 18:15:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683224133; bh=s6vTyiYcHYzz7eCz26zTtkB0PMls/rX17S3oalE7DgA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D6M2M2MQc2wfy5KhLLnCy8pSQC3VU7bTcfmkzwDM2HnQoHPUZo5ndsf3qpRBJeBOG wozUMtPZzrhCo4dapeMnJhn3GlA3+mjlE9SolHUJjpBYMZ3rtTmZvHDz6sDt5b1h7s /OSnJWygaWCOTt29TdAcInhSWbEEkzcRRn9v+wHrAsF3zJYKSqa/by4Raim70Eb7bB jPnhW1eaXuZJ3HhyNHvlmGwZnGYZnsXa7f2LTkS0xbPGRT1Wy1ZEcCSPIQD3qyLWlA pLhVBlehmV23t0OZRiG97V9ARzFvOkeZfVczECsUSbHk6cQInENuCMi1AQpNiGsbkk yKNSXd6DsHhsg== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v1 1/7] RISC-V: simplify register width check in ISA string parsing Date: Thu, 4 May 2023 19:14:20 +0100 Message-Id: <20230504-twirl-caution-3a2248aa24bb@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> References: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1642; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=NaWhaFCAYxKjY8ZONY2tqP065oLV7bTeJ/oubaRmp7E=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnBX/9GXZe5kmpq95aRjefSn11XdwktLWY56mn4dVX1W 7bH9703dpSyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAiVcYMf2WEDv8STHolk1fF ckhQV6Jhm8JchrQ++2maTA9CTlb6/mZkaGc4nBTxv3LvvnnTDs16FxGXlH613No0oWI3z4Zm4ef 2bAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_111534_403451_616EB8D0 X-CRM114-Status: GOOD ( 13.38 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: conor@kernel.org, Yangyu Chen , Conor Dooley , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Saving off the `isa` pointer to a temp variable, followed by checking if it has been incremented is a bit of an odd pattern. Perhaps it was done to avoid a funky looking if statement mixed with the ifdeffery. Now that we use IS_ENABLED() here just return from the parser as soon as we detect a mismatch between the string and the currently running kernel. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index cb32658180da..00df7a3a3931 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -115,7 +115,6 @@ void __init riscv_fill_hwcap(void) for_each_of_cpu_node(node) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); - const char *temp; rc = riscv_of_processor_hartid(node, &hartid); if (rc < 0) @@ -126,14 +125,14 @@ void __init riscv_fill_hwcap(void) continue; } - temp = isa; - if (IS_ENABLED(CONFIG_32BIT) && !strncasecmp(isa, "rv32", 4)) - isa += 4; - else if (IS_ENABLED(CONFIG_64BIT) && !strncasecmp(isa, "rv64", 4)) - isa += 4; - /* The riscv,isa DT property must start with rv64 or rv32 */ - if (temp == isa) + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4)) continue; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4)) + continue; + + isa += 4; + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); for (; *isa; ++isa) { const char *ext = isa++; From patchwork Thu May 4 18:14:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13231487 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B1CF0C77B7C for ; Thu, 4 May 2023 18:15:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 4 May 2023 18:15:35 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F164C433D2; Thu, 4 May 2023 18:15:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683224135; bh=bRs7J4f34G8kawlGhlKbnXWQPdGtTPzbSOGb3QMR/sg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GsnvLZutn/QZxNE3+xXh4pOzodr0smHZey7bOje5G3+yCTsreIVqKQUXk86byEP9f dWe9EU0sb5+T8DqYizYk2mYMaAEKwaCAr1NWQF/I1i2SHl2roqnQsOqTwYy0FbUnrR 1eaAZ5PkL9H2LpXRAiGu+XuUUXACfyQ54GY9VR0yfsrLC1TVkiIbAcvH872F8hQ2Vj tc8PbqbXrT3z6fDC75ipKL3P05VdCeWpH5gfId5T/Wsd5EHiXE/diTNvSBgqym0D6P F1B6/0enxiw5xXuZJzMum2FVm5Xdi3D5nNP8HPgdb/MXQk2teT9jt8KDdXUDLl8Jom iTbN4TCK1C6uQ== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v1 2/7] RISC-V: only iterate over possible CPUs in ISA string parser Date: Thu, 4 May 2023 19:14:21 +0100 Message-Id: <20230504-simple-chant-c33c14cc9e4e@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> References: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2334; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=mi7xLokjgaadV28078ayulYwgY2St3rJD+0UZHLOoxA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnBX/+pHvhnYKvuc/vX1Au11eamU5U7lTrfWRfFzZUW1 OH603i8o5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABM5qMPIcMo3RFBHj7mynP3I 1Hfyz0NrAyQmnjdflLTa766G5ooqD0aGTXEpz28vY3jNbrHYctukc8y/p3Gs/pS5ff10i3WzHsr cZAcA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_111536_239945_7AB654F4 X-CRM114-Status: GOOD ( 13.82 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: conor@kernel.org, Yangyu Chen , Conor Dooley , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Sunil V L During boot we call riscv_of_processor_hartid() for each hart that we add to the possible cpus list. Repeating the call again here is not required, if we iterate over the list of possible CPUs, rather than the list of all CPUs. The call to of_property_read_string() for "riscv,isa" cannot fail either, as it has previously succeeded in riscv_of_processor_hartid(), but leaving in the error checking makes the operation of the loop more obvious & provides leeway for future refactoring of riscv_of_processor_hartid(). Partially ripped from Sunil's ACPI support series, with the logic inverted to continue early on failure. Signed-off-by: Sunil V L Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 00df7a3a3931..3ae456413f79 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -99,7 +100,7 @@ void __init riscv_fill_hwcap(void) char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; - unsigned long hartid; + unsigned int cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -112,15 +113,19 @@ void __init riscv_fill_hwcap(void) bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - for_each_of_cpu_node(node) { + for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); - rc = riscv_of_processor_hartid(node, &hartid); - if (rc < 0) + node = of_cpu_device_node_get(cpu); + if (!node) { + pr_warn("Unable to find cpu node\n"); continue; + } - if (of_property_read_string(node, "riscv,isa", &isa)) { + rc = of_property_read_string(node, "riscv,isa", &isa); + of_node_put(node); + if (rc) { pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); continue; } From patchwork Thu May 4 18:14:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13231483 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id ACD43C7EE22 for ; Thu, 4 May 2023 18:15:48 +0000 (UTC) DKIM-Signature: v=1; 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Thu, 04 May 2023 18:15:39 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id D3B3D63529; Thu, 4 May 2023 18:15:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8DF29C4339B; Thu, 4 May 2023 18:15:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683224137; bh=9JfENNR9tgTK4UNoFGHEIVOabute+dkxlDAuBXGtQfY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fYhAo1ODIkVmQoBwdGr6i8SBu8SxzKTjjSwKijH1/c3LjkHLo5JMnPGPSyWnQ+9jB 8Wi27iw1ls6YTTVHt/NyrA8uj8766MrsxulcasaRyntfyI6lfIChg49rXdXflb9i6i HU1ZTSqwtDQVFX/BJ1NNDHdPrBRGI4Yd/+8uDlsdoj6OmgoNXSe03cy6DMowU1BSIM uP6DZ7i0dMk0Zv+FG12HRGE9w/fh3UXHK0bH5nIeha0Af3zgbx1zgQW9XwGxufF2Yt 0eY+G0pvXb2NE/kAS9OU8bWqWahqmr2f4ja00dnrYCC91H8/bkO+xEHKLOyDgoJEtV Fg/d9gtlvJGqQ== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v1 3/7] RISC-V: split early & late of_node to hartid mapping Date: Thu, 4 May 2023 19:14:22 +0100 Message-Id: <20230504-wrongful-unvaried-d4588e49df5d@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> References: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3273; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=mqXlw0fgDUn4br2UCAGz540cPsRpVLpHCsPCQP13VEQ=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnBX/9l/l5VrbIpLWiuXZGU3sbuO7GzLrTPXPsmWVn+j alvbP/9jlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAEzk6TJGhheLp/1UnCDG0yqY MavoUPzffC7B1ctezl7sc6uwUO9TznNGhp92nlIFU6RjQ6OdZovNkApWWcifek33ZpP0/8MO4X0 9DAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_111538_375154_FE65F183 X-CRM114-Status: GOOD ( 15.54 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: conor@kernel.org, Yangyu Chen , Conor Dooley , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Some back and forth with Drew [1] about riscv_fill_hwcap() resulted in the realisation that it is not very useful to parse the DT & perform validation of riscv,isa every time we would like to get the id for a hart. Although it is no longer called in riscv_fill_hwcap(), riscv_of_processor_hartid() is called in several other places. Notably in setup_smp() it forms part of the logic for filling the mask of possible CPUs. Since a possible CPU must have passed this basic validation of riscv,isa, a repeat validation is not required. Rename riscv_of_processor_id() to riscv_early_of_processor_id(), which will be called from setup_smp() & introduce a new riscv_of_processor_id() which makes use of the pre-populated mask of possible cpus. Link: https://lore.kernel.org/linux-riscv/xvdswl3iyikwvamny7ikrxo2ncuixshtg3f6uucjahpe3xpc5c@ud4cz4fkg5dj/ [1] Reviewed-by: Andrew Jones Signed-off-by: Conor Dooley --- arch/riscv/include/asm/processor.h | 1 + arch/riscv/kernel/cpu.c | 22 +++++++++++++++++++++- arch/riscv/kernel/smpboot.c | 2 +- 3 files changed, 23 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 94a0590c6971..3479f9fca4b0 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -75,6 +75,7 @@ static inline void wait_for_interrupt(void) struct device_node; int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); +int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hartid); int riscv_of_parent_hartid(struct device_node *node, unsigned long *hartid); extern void riscv_fill_hwcap(void); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index f4dadbfecd04..7030a5004f8e 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -20,6 +20,26 @@ * isn't an enabled and valid RISC-V hart node. */ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) +{ + int cpu; + + *hart = (unsigned long)of_get_cpu_hwid(node, 0); + if (*hart == ~0UL) { + pr_warn("Found CPU without hart ID\n"); + return -ENODEV; + } + + cpu = riscv_hartid_to_cpuid(*hart); + if (cpu < 0) + return cpu; + + if (!cpu_possible(cpu)) + return -ENODEV; + + return 0; +} + +int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *hart) { const char *isa; @@ -28,7 +48,7 @@ int riscv_of_processor_hartid(struct device_node *node, unsigned long *hart) return -ENODEV; } - *hart = (unsigned long) of_get_cpu_hwid(node, 0); + *hart = (unsigned long)of_get_cpu_hwid(node, 0); if (*hart == ~0UL) { pr_warn("Found CPU without hart ID\n"); return -ENODEV; diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 445a4efee267..626238200010 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -81,7 +81,7 @@ void __init setup_smp(void) cpu_set_ops(0); for_each_of_cpu_node(dn) { - rc = riscv_of_processor_hartid(dn, &hart); + rc = riscv_early_of_processor_hartid(dn, &hart); if (rc < 0) continue; From patchwork Thu May 4 18:14:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13231484 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4EB75C7EE21 for ; Thu, 4 May 2023 18:15:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; 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Thu, 4 May 2023 18:15:39 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ADF8BC433D2; Thu, 4 May 2023 18:15:37 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683224139; bh=WFeiayG63gpQp4occGvr+vuuSR18T6kGBpB8q1BLM2U=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=huRm3EA0yysIW5cW2jSVv8/s+D/eNjyCvqL/09kCh5d2QWiXqBnT/OFw2eQGKuEAo zyzPiYD5oJXOHMlUSgYWLPtrBPEKairF81ajetedeeyrbchPaBF7n6lgz43x/8Mepi gBm19pNtiO3In4U73brGHVpOuay5v9R+xwqj/tPxML+yNol2mMkuKmP+uCj5MrcS2G 8gRK59bwRBAJloqk29EymnOfhcYo+nV1l0dcmkEdZLSgUjThCEM9JHbgsbOy8DyUbw DiJ/BizRBcFd0PuPoCQuVHcvgeBjMeAbMV6WISkFPBjMfJ7IY8kh9v+2WaZLVCQCAj OOJlUX4/cRhdg== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v1 4/7] RISC-V: validate riscv,isa at boot, not during ISA string parsing Date: Thu, 4 May 2023 19:14:23 +0100 Message-Id: <20230504-sultry-frostlike-9dbf19333725@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> References: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Further, "ima" support is required by the kernel, so reject any CPU not fitting the bill. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpu.c | 8 +++++--- arch/riscv/kernel/cpufeature.c | 12 ++++++------ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 7030a5004f8e..b0c3ec0f2f5b 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -63,10 +63,12 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); return -ENODEV; } - if (tolower(isa[0]) != 'r' || tolower(isa[1]) != 'v') { - pr_warn("CPU with hartid=%lu has an invalid ISA of \"%s\"\n", *hart, isa); + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32ima", 7)) + return -ENODEV; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64ima", 7)) return -ENODEV; - } return 0; } diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 3ae456413f79..a79c5c52a174 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -130,12 +130,12 @@ void __init riscv_fill_hwcap(void) continue; } - if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32", 4)) - continue; - - if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64", 4)) - continue; - + /* + * For all possible cpus, we have already validated in + * the boot process that they at least contain "rv" and + * whichever of "32"/"64" this kernel supports, and so this + * section can be skipped. + */ isa += 4; bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); From patchwork Thu May 4 18:14:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13231485 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 463A0C7EE22 for ; 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Thu, 04 May 2023 18:15:45 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pudUU-008VRq-1r for linux-riscv@lists.infradead.org; Thu, 04 May 2023 18:15:44 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 1E57D63582; Thu, 4 May 2023 18:15:42 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CD7B2C4339B; Thu, 4 May 2023 18:15:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683224141; bh=TvakAFbPcrD7hCAm+Dg/e0/oiiwwCFYHsXJHt4QwDVU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=aYV8cmJ1Nnhh/W+VHZmFjvwGW8ajy5UhBaGSd4K9KMTU1m6WEd22OZhJwTmWLCiUS /U47uDUQP3thiwl/0X7ZtePbL+S4zjkN2WPV5yPwQ+x2mdxxCs90pUJshkoFkczN/v DZtwEPSIbnbiDu2NB7rhWgiz8ziid6xaVk9udcUah6kT8kZ4GhB5o+HrPZz+YuaOfH kc3pZSiVN80atvP/0wPQYuPNJ0HYlWBxpHL9LgmkWQj0Hs+rtVbfXE1KVohmfLX6rb SpnoXIy/NFeHXG8WuP3TQKZZ7RO68D8aqChYHrh69IyDI9gGrAzB6biJwaAtVf5ro7 CiGROdaUwKlhQ== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v1 5/7] RISC-V: rework comments in ISA string parser Date: Thu, 4 May 2023 19:14:24 +0100 Message-Id: <20230504-never-childlike-75e2ce7e50d8@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> References: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4630; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=tEHbqETiBb82U3DYdAGcDcmKm/YUwFV3nz4D77zk+xA=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnBX/8FOB89s3/6Pg6x5TZTo7U3ZxXKFLhecdTK7E+fI 91RH2rZUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgImYnWNkmBj0WG/eIoaSG7vY 8tznzfxw+J/wggmtak+axIQFZ+++vYnhn4FiQmuD/3xfO/WYHIO1Xd1BrXr+4vF/iyzKD7U62cU wAQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_111542_685979_DD7AA688 X-CRM114-Status: GOOD ( 23.81 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: conor@kernel.org, Yangyu Chen , Conor Dooley , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley I have found these comments to not be at all helpful whenever I look at the parser. Further, the comments in the default case (single letter parser) are not quite right either. Group the comments into a larger one at the start of each case, that attempts to explain things at a higher level. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 71 ++++++++++++++++++++++++++++------ 1 file changed, 60 insertions(+), 11 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index a79c5c52a174..2fc72f092057 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -146,7 +146,7 @@ void __init riscv_fill_hwcap(void) switch (*ext) { case 's': - /** + /* * Workaround for invalid single-letter 's' & 'u'(QEMU). * No need to set the bit in riscv_isa as 's' & 'u' are * not valid ISA extensions. It works until multi-letter @@ -163,53 +163,102 @@ void __init riscv_fill_hwcap(void) case 'X': case 'z': case 'Z': + /* + * Before attempting to parse the extension itself, we find its end. + * As multi-letter extensions must be split from other multi-letter + * extensions with an "_", the end of a multi-letter extension will + * either be the null character as of_property_read_string() returns + * null-terminated strings, or the "_" at the start of the next + * multi-letter extension. + * + * Next, as the extensions version is currently ignored, we + * eliminate that portion. This is done by parsing backwards from + * the end of the extension, removing any numbers. This may be a + * major or minor number however, so the process is repeated if a + * minor number was found. + * + * ext_end is intended to represent the first character *after* the + * name portion of an extension, but will be decremented to the last + * character itself while eliminating the extensions version number. + * A simple re-increment solves this problem. + */ ext_long = true; - /* Multi-letter extension must be delimited */ for (; *isa && *isa != '_'; ++isa) if (unlikely(!isalnum(*isa))) ext_err = true; - /* Parse backwards */ + ext_end = isa; if (unlikely(ext_err)) break; + if (!isdigit(ext_end[-1])) break; - /* Skip the minor version */ + while (isdigit(*--ext_end)) ; - if (tolower(ext_end[0]) != 'p' - || !isdigit(ext_end[-1])) { - /* Advance it to offset the pre-decrement */ + + if (tolower(ext_end[0]) != 'p' || !isdigit(ext_end[-1])) { ++ext_end; break; } - /* Skip the major version */ + while (isdigit(*--ext_end)) ; + ++ext_end; break; default: + /* + * Things are a little easier for single-letter extensions, as they + * are parsed forwards. + * + * After checking that our starting position is valid, we need to + * ensure that, when isa was incremented at the start of the loop, + * that it arrived at the start of the next extension. + * + * If we are already on a non-digit, there is nothing to do. Either + * we have a multi-letter extension's _, or the start of an + * extension. + * + * Otherwise we have found the current extension's major version + * number. Parse past it, and a subsequent p/minor version number + * if present. The `p` extension must not appear immediately after + * a number, so there is no fear of missing it. + * + */ if (unlikely(!isalpha(*ext))) { ext_err = true; break; } - /* Find next extension */ + if (!isdigit(*isa)) break; - /* Skip the minor version */ + while (isdigit(*++isa)) ; + if (tolower(*isa) != 'p') break; + if (!isdigit(*++isa)) { --isa; break; } - /* Skip the major version */ + while (isdigit(*++isa)) ; + break; } + + /* + * The parser expects that at the start of an iteration isa points to the + * character before the start of the next extension. This will not be the + * case if we have just parsed a single-letter extension and the next + * extension is not a multi-letter extension prefixed with an "_". It is + * also not the case at the end of the string, where it will point to the + * terminating null character. + */ if (*isa != '_') --isa; From patchwork Thu May 4 18:14:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13231486 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 23EC8C7EE21 for ; Thu, 4 May 2023 18:15:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=+lWwzBAPhFx2srh0ohfeFeom4NQV0IL+9NpQp9amu+k=; b=MxYE8xeQdlDT72 DN0tIiX7LabImI1lEPj+sN0L2FcU6QgYHCSQXkCkvXCZN0cJJPjmXdm6/Y8DCBW7OW6RLm+7caVI+ ZLVUjJZOYNi7JmHZypW6q1Pu1PDzzP0ITZ1nxaNcExuocLYr3m8eneXU1C29Uz22x1rVJbkwiU10j b6GIGH8oAeubgwh8BV6VQ7RWDO2Apcp9Zxua+v+W5DRIPXUbnGDWzGpXaJ6ZZp/f31lfU/FcCkgvV urZNhCwwCszLlWCtwyqGn8ieOjMR5Hc2CKz4eaVSO7fiyaHOF02ZCCFusfRkJhYnMaPV9t+u8+rhv +jAOgRW6OuxuqqCPmBEQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pudUZ-008VTa-1t; Thu, 04 May 2023 18:15:47 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pudUW-008VSc-1z for linux-riscv@lists.infradead.org; Thu, 04 May 2023 18:15:46 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3D44F63529; Thu, 4 May 2023 18:15:44 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id ED156C433EF; Thu, 4 May 2023 18:15:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683224143; bh=mfu+QSUbslnmYoxIsk5xdCAJ7L+WSuozBh83epLLhqU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ML3X2/JjcNg00WvHLLe1QADOhK7LysuajvoLcDWS1NAYqfu8ryV3Wuv/xQowqzBJg 1A3NJe5DxBuX14Fx1kv8j12c1eoJ2ioSZ3geoqNbwTo2rWKjawLrfAjDOewW022dht /90Xg+AJAt2qWxWfD7MfL8hND61AQ/FoOSMpeApjWUVmptPjT3pF7+2WJRzENWr0vg s9EdWUJBmhfTIPZHu0YNX6zDvvJniFcelgBqkbm86+fS7id9fuRtAUXqOaIUyutoS2 9U7dawJv/G3eP+VNVg8pp7cu+/OsxG+A//U1ZWcVtptZULmnifq9SgFKV8L+iATF/r cklrvCWc6fmbQ== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v1 6/7] RISC-V: remove decrement/increment dance in ISA string parser Date: Thu, 4 May 2023 19:14:25 +0100 Message-Id: <20230504-barrette-engraver-df0392651854@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> References: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2887; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=RkVJHyeWNPWhbzSEHH1wjwVOmkBTxCXrBd5jxA5fagQ=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnBX//36Exldj15rKe/VKCuSLSxP29+bvWk/h/L5Zim5 q40DgzsKGVhEONgkBVTZEm83dcitf6Pyw7nnrcwc1iZQIYwcHEKwESKzjIy/Htb9Kj/8O8MUW9z ocgb+hyLnb4/OfKu81+6+66yC6/5ghgZnk1K45rc9fP+j9yrnX+ne/+5sF1dqLKiuzEr4fxpUZY 6VgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_111544_727487_52641821 X-CRM114-Status: GOOD ( 20.10 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: conor@kernel.org, Yangyu Chen , Conor Dooley , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley While expanding on the comments in the ISA string parsing code, I noticed that the conditional decrement of `isa` at the end of the loop was a bit odd. The parsing code expects that at the start of the for loop, `isa` will point to the first character of the next unparsed extension. However, depending on what the next extension is, this may not be true. Unless the next extension is a multi-letter extension preceded by an underscore, `isa` will either point to the string's null-terminator or to the first character of the next extension, once the switch statement has been evaluated. Obviously incrementing `isa` at the end of the loop could cause it to increment past the null terminator or miss a single letter extension, so `isa` is conditionally decremented, just so that the loop can increment it again. It's easier to understand the code if, instead of this decrement + increment dance, we instead use a while loop & rely on the handling of individual extension types to leave `isa` pointing to the first character of the next extension. As already mentioned, this won't be the case where the following extension is multi-letter & preceded by an underscore. To handle that, invert the check and increment rather than decrement. Hopefully this eliminates a "huh?!?" moment the next time somebody tries to understand this code. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 2fc72f092057..b425658bbf08 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -139,7 +139,7 @@ void __init riscv_fill_hwcap(void) isa += 4; bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); - for (; *isa; ++isa) { + while (*isa) { const char *ext = isa++; const char *ext_end = isa; bool ext_long = false, ext_err = false; @@ -253,14 +253,12 @@ void __init riscv_fill_hwcap(void) /* * The parser expects that at the start of an iteration isa points to the - * character before the start of the next extension. This will not be the - * case if we have just parsed a single-letter extension and the next - * extension is not a multi-letter extension prefixed with an "_". It is - * also not the case at the end of the string, where it will point to the - * terminating null character. + * first character of the next extension. As we stop parsing an extension + * on meeting a non-alphanumeric character, an extra increment is needed + * where the succeeding extension is a multi-letter prefixed with an "_". */ - if (*isa != '_') - --isa; + if (*isa == '_') + ++isa; #define SET_ISA_EXT_MAP(name, bit) \ do { \ From patchwork Thu May 4 18:14:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13231488 X-Patchwork-Delegate: palmer@dabbelt.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 32A95C7EE29 for ; Thu, 4 May 2023 18:15:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=6VJyEXn/Lp53APl5Iwh3nd2KB0RU9BOhtXczi3TIYks=; b=jsOxTDyqRpJx8/ Xj5Lc9RIJHPGGoFHDbeXPk7HSL8LgpFOaYM4n//ZqUZbWGA/aDw5UR0URyTzEZMvfwiXjyc0Blml4 erHv235AQ2/AuXPQxl82j+IjlsMBAkGOk/ETQGEEO8PrC8rwUlYYifhfI+YOdhU5730NtbY/aYwSm GKuEk+JSTZg9jwRCV17XK4gCHtp2AXPRHJgNy0RRyGzE9TCnFyYhfVfdBaq38cuIVkMPdCV+E6LbD a2KrSrCCvyndYKIGNa1lzTyO0aC4dLQXE1m8Q1sv1gRRLI0BK4Q2CG7CTcFEVMH81OBgrgNYUcAl0 k08/n6kGpiJ/Xi+MVFLQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pudUb-008VU3-0P; Thu, 04 May 2023 18:15:49 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pudUY-008VTG-2Z for linux-riscv@lists.infradead.org; Thu, 04 May 2023 18:15:48 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5E657630AE; Thu, 4 May 2023 18:15:46 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 17584C4339B; Thu, 4 May 2023 18:15:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683224145; bh=IqaZ10/DC7yoaMpXc3z1iSfsNsTNIvDE77+MtWugYOE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=SdR+3qErEM3Ri2n5f38/TXd50BpKj1E02ozgRo3wJYn2juBpMpmRoADAUUN8oei4R fpgrshnkepl3MlMskxSdow11/2BSoTzJub91/395EGP0IpuC8TC7GH2kc/Fp9eDPyW bm9zMgNbpCrIrJaUYSH9L8WBf0FPbEs+MOwoxT7RLF2s3QL7qh4WvSoROImaaUr99E xg8zTgMleWTi+qCYX876snfWAxdPVIY+D7aUtrT3k3jpLZThPe2qTvkc0MqspuUO3j 5sBGqFoSlp9y2rfs1LDOIV9Tj11asttBQNc3Uv2wSckiC0IRsARZNTvDX9dnWMamd7 5Dhzfr0mAPr3g== From: Conor Dooley To: palmer@dabbelt.com Subject: [PATCH v1 7/7] RISC-V: always report presence of Zicsr/Zifencei Date: Thu, 4 May 2023 19:14:26 +0100 Message-Id: <20230504-oncoming-antihero-1ed69bb8f57d@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> References: <20230504-divisive-unsavory-5a2ff0c3c2d1@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2372; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=wm2vukeUAK88wTVTWM3yrfpupCVbuR+rzgaQij/mlIw=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCnBX//HXbs4c+LMGRLZJ59oLnkrlXM08oKGcNcB2+TFJ d97/8r6d5SyMIhxMMiKKbIk3u5rkVr/x2WHc89bmDmsTCBDGLg4BWAigXoM/33tHDd4PxUxl644 PWdOe8YVi/euhqt4vLepCnepfjdSLmT4n8BweG3IzsnJeeV+v1gjPxa7/dj79f5Gl/g0xhiOnqu +7AA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230504_111546_907336_CC5DC8BA X-CRM114-Status: GOOD ( 11.91 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: conor@kernel.org, Yangyu Chen , Conor Dooley , Paul Walmsley , linux-riscv@lists.infradead.org, Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Zicsr/Zifencei were part of i when the port was written and are required by the kernel. There's not much that userspace can do with this extra information, but there is no harm in reporting an ISA string that closer resembles the current versions of the ISA specifications either. Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/include/asm/hwcap.h | 2 ++ arch/riscv/kernel/cpu.c | 2 ++ arch/riscv/kernel/cpufeature.c | 7 +++++++ 3 files changed, 11 insertions(+) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index 9af793970855..aa61031f7923 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -44,6 +44,8 @@ #define RISCV_ISA_EXT_ZIHINTPAUSE 32 #define RISCV_ISA_EXT_SVNAPOT 33 #define RISCV_ISA_EXT_ZICBOZ 34 +#define RISCV_ISA_EXT_ZICSR 35 +#define RISCV_ISA_EXT_ZIFENCEI 36 #define RISCV_ISA_EXT_MAX 64 #define RISCV_ISA_EXT_NAME_LEN_MAX 32 diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index b0c3ec0f2f5b..0d5d580dca61 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -204,8 +204,10 @@ arch_initcall(riscv_cpuinfo_init); * New entries to this struct should follow the ordering rules described above. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), + __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b425658bbf08..92f0e7b78eef 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -292,6 +292,13 @@ void __init riscv_fill_hwcap(void) #undef SET_ISA_EXT_MAP } + /* + * Linux requires Zicsr & Zifencei, so we may as well always + * set them. + */ + set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa); + set_bit(RISCV_ISA_EXT_ZICSR, this_isa); + /* * All "okay" hart should have same isa. Set HWCAP based on * common capabilities of every "okay" hart, in case they don't