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[46.102.197.194]) by smtp.gmail.com with ESMTPSA id b12-20020adfe30c000000b00306423904d6sm3053844wrj.45.2023.05.05.10.57.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 10:57:14 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 452f0c61-eb6e-11ed-b226-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1683309435; x=1685901435; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2enxHJVvB53hhS6w5p4MreN4cLpgSnyXWT9wrZUvS/4=; b=S6WP4jZQqFuckveRJuLLwmmlAWJchVAJAb9jg7PVGcyB+N56rwpZ2AwOxLV671Sz+Q FE2T1YlC1BiiUjDV2uZ8Nf7jEsflLCwPGXr13DpeKCJpId6dtgybo09rgCJXJtEamKwj 4KmLO8o+npkY8s8YD/XtuytYHkOev4UdELeDc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683309435; x=1685901435; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2enxHJVvB53hhS6w5p4MreN4cLpgSnyXWT9wrZUvS/4=; b=dyFGTTtTIzDFPoWnYnalHt6XIBX5P+U+N9mhMCc/bToBPbc16rc2O8qrM6eDeFjlgZ 5uWLn14Jyg52kGqfeYw6AsXWP6by89P+Bk1yxb1g+/xJP6ENip//huhCmJWmSLKC2vb9 JAkhGDSXX9VVmXsuV9ID5Eb0UyHXhVDbmWWbGk6Z3HVtBx2ybwjC1Qf1/O7pGmlhVRUk 870kGyeQ5iN2uIkZ0HqfZR8JlCrUXH0z1vW3SRxZZlDdLvmCTIMqpnJb4XlJdiLie8Qx B1dMRpLaZzF7b6Uu99ryc1klcbyu/psciB3wFyk+aFhLZckwLV65WUEOFIaXkhxwjoaB NeFQ== X-Gm-Message-State: AC+VfDzV5gCsQncdbCCJAFPutJXlTvGeEnEoKfYb6Q0v0l+Lu4gFfDFH A+1FXNpq1V5HLYbEyaazgGjLvmIxJo32bWzQjAE= X-Google-Smtp-Source: ACHHUZ5sPykgAxfLbTpChhsume9wrclYkH7/nFknVv7g/8xzCXnmQiEIye5TXtK5me/BScAefzZtWg== X-Received: by 2002:a05:600c:2310:b0:3f3:fe82:ee79 with SMTP id 16-20020a05600c231000b003f3fe82ee79mr1707787wmo.23.1683309434835; Fri, 05 May 2023 10:57:14 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Wei Liu , Anthony PERARD , Juergen Gross , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= Subject: [PATCH 1/3] x86: Add AMD's CpuidUserDis bit definitions Date: Fri, 5 May 2023 18:57:03 +0100 Message-Id: <20230505175705.18098-2-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505175705.18098-1-alejandro.vallejo@cloud.com> References: <20230505175705.18098-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 AMD reports support for CpuidUserDis in CPUID and provides the toggle in HWCR. This patch adds the positions of both of those bits to both xen and tools. No functional change. Signed-off-by: Alejandro Vallejo --- tools/libs/light/libxl_cpuid.c | 1 + tools/misc/xen-cpuid.c | 2 ++ xen/arch/x86/include/asm/msr-index.h | 1 + xen/include/public/arch-x86/cpufeatureset.h | 1 + 4 files changed, 5 insertions(+) diff --git a/tools/libs/light/libxl_cpuid.c b/tools/libs/light/libxl_cpuid.c index 5f0bf93810..4d2fab5414 100644 --- a/tools/libs/light/libxl_cpuid.c +++ b/tools/libs/light/libxl_cpuid.c @@ -317,6 +317,7 @@ int libxl_cpuid_parse_config(libxl_cpuid_policy_list *cpuid, const char* str) {"lfence+", 0x80000021, NA, CPUID_REG_EAX, 2, 1}, {"nscb", 0x80000021, NA, CPUID_REG_EAX, 6, 1}, + {"cpuid-user-dis", 0x80000021, NA, CPUID_REG_EAX, 17, 1}, {"maxhvleaf", 0x40000000, NA, CPUID_REG_EAX, 0, 8}, diff --git a/tools/misc/xen-cpuid.c b/tools/misc/xen-cpuid.c index d7efc59d31..8ec143ebc8 100644 --- a/tools/misc/xen-cpuid.c +++ b/tools/misc/xen-cpuid.c @@ -199,6 +199,8 @@ static const char *const str_e21a[32] = { [ 2] = "lfence+", [ 6] = "nscb", + + /* 16 */ [17] = "cpuid-user-dis", }; static const char *const str_7b1[32] = diff --git a/xen/arch/x86/include/asm/msr-index.h b/xen/arch/x86/include/asm/msr-index.h index fa771ed0b5..082fb2e0d9 100644 --- a/xen/arch/x86/include/asm/msr-index.h +++ b/xen/arch/x86/include/asm/msr-index.h @@ -337,6 +337,7 @@ #define MSR_K8_HWCR 0xc0010015 #define K8_HWCR_TSC_FREQ_SEL (1ULL << 24) +#define K8_HWCR_CPUID_USER_DIS (1ULL << 35) #define MSR_K7_FID_VID_CTL 0xc0010041 #define MSR_K7_FID_VID_STATUS 0xc0010042 diff --git a/xen/include/public/arch-x86/cpufeatureset.h b/xen/include/public/arch-x86/cpufeatureset.h index 12e3dc80c6..623dcb1bce 100644 --- a/xen/include/public/arch-x86/cpufeatureset.h +++ b/xen/include/public/arch-x86/cpufeatureset.h @@ -287,6 +287,7 @@ XEN_CPUFEATURE(AVX_IFMA, 10*32+23) /*A AVX-IFMA Instructions */ /* AMD-defined CPU features, CPUID level 0x80000021.eax, word 11 */ XEN_CPUFEATURE(LFENCE_DISPATCH, 11*32+ 2) /*A LFENCE always serializing */ XEN_CPUFEATURE(NSCB, 11*32+ 6) /*A Null Selector Clears Base (and limit too) */ +XEN_CPUFEATURE(CPUID_USER_DIS, 11*32+17) /* CPUID disable for non-privileged software */ /* Intel-defined CPU features, CPUID level 0x00000007:1.ebx, word 12 */ XEN_CPUFEATURE(INTEL_PPIN, 12*32+ 0) /* Protected Processor Inventory Number */ From patchwork Fri May 5 17:57:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13232946 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 21FCAC77B75 for ; Fri, 5 May 2023 17:57:41 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.530596.826317 (Exim 4.92) (envelope-from ) id 1puzgH-00073q-SA; Fri, 05 May 2023 17:57:21 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 530596.826317; Fri, 05 May 2023 17:57:21 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1puzgH-00073j-Ox; Fri, 05 May 2023 17:57:21 +0000 Received: by outflank-mailman (input) for mailman id 530596; Fri, 05 May 2023 17:57:19 +0000 Received: from se1-gles-flk1-in.inumbo.com ([94.247.172.50] helo=se1-gles-flk1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1puzgF-0006ws-LN for xen-devel@lists.xenproject.org; Fri, 05 May 2023 17:57:19 +0000 Received: from mail-wm1-x32f.google.com (mail-wm1-x32f.google.com [2a00:1450:4864:20::32f]) by se1-gles-flk1.inumbo.com (Halon) with ESMTPS id 46190858-eb6e-11ed-8611-37d641c3527e; Fri, 05 May 2023 19:57:17 +0200 (CEST) Received: by mail-wm1-x32f.google.com with SMTP id 5b1f17b1804b1-3f19a80a330so14429995e9.2 for ; Fri, 05 May 2023 10:57:17 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id b12-20020adfe30c000000b00306423904d6sm3053844wrj.45.2023.05.05.10.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 10:57:15 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 46190858-eb6e-11ed-8611-37d641c3527e DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1683309436; x=1685901436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ubIK+XYgAIIZcyqAhGOfgJDl4JEExigDY8ufylt9qvw=; b=iUVAAHDp7zE3tBjYt2RmDBRUg2mKNMFd53nbCBsmyRuBT8fWhlFV7g8QWARjB8ygI2 fxg29XQGaCSIq5vPpT61NLslfCNlWHG1Q7E7ijP3E62sfacQeSvj/Lnc2ncHdxFrUXSU CBqrGZcqBIQtYo6p8QFP051fkN/U9nmKodnyQ= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683309436; x=1685901436; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ubIK+XYgAIIZcyqAhGOfgJDl4JEExigDY8ufylt9qvw=; b=Q3a3nADK+czQJIQYO1kVngJ8+cs3bIyDet1zsveRPSuAsfFFUQ4KlkHcG3N0iPwhs1 yYJ+Usd1v6f/RDpc2WfZat8wWUbyIATnvQNvWiQLSCqbjkqH8GrJi7ZiPIrt34oypskH /CJUudRzwR/F/h6LnxylnoCY7u/SA7md3imHHyoZ2P8NVA53LbZg6yWnAJQCcHdfdAt3 cqjK+fPzkfk91uzhfeGHkSQbwWaSzbpsfRsv4c42gRhRndx1US1dATa0l8oSZpyh1rGD Za9/NT2xi9qznx9ADgB0CMwpZ6yCP2h+U2ja9GwoN4pTk2v15dRSyI5pe522ZEws93EH UIOQ== X-Gm-Message-State: AC+VfDw0zTscQzc4gF5wEzVtk98dYm+QqzW//AQD++jwN06rZLICgt/n 06GD2/6vTLYf1bs15+lB5nJatKSaG8kdI2Xxoc8= X-Google-Smtp-Source: ACHHUZ6CrKzTndC7mGLtHexYNG/IMPc8wRB57ggtG2k3REK1pCr2UWWgO52VIUGy8rend9Fb/kIOwg== X-Received: by 2002:a05:600c:257:b0:3f1:800f:cc61 with SMTP id 23-20020a05600c025700b003f1800fcc61mr1771921wmj.13.1683309436339; Fri, 05 May 2023 10:57:16 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH 2/3] x86: Add support for CpuidUserDis Date: Fri, 5 May 2023 18:57:04 +0100 Message-Id: <20230505175705.18098-3-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505175705.18098-1-alejandro.vallejo@cloud.com> References: <20230505175705.18098-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 Includes a refactor to move vendor-specific probes to vendor-specific files. Furthermore, because CpuIdUserDis is reported in Cpuid itself, the extended leaf containing that bit must be retrieved before calling c_early_init() Signed-off-by: Alejandro Vallejo --- xen/arch/x86/cpu/amd.c | 29 ++++++++++++++++++- xen/arch/x86/cpu/common.c | 51 ++++++++++++++++++---------------- xen/arch/x86/cpu/intel.c | 11 +++++++- xen/arch/x86/include/asm/amd.h | 1 + 4 files changed, 66 insertions(+), 26 deletions(-) diff --git a/xen/arch/x86/cpu/amd.c b/xen/arch/x86/cpu/amd.c index caafe44740..9269015edd 100644 --- a/xen/arch/x86/cpu/amd.c +++ b/xen/arch/x86/cpu/amd.c @@ -271,8 +271,20 @@ static void __init noinline amd_init_levelling(void) { const struct cpuidmask *m = NULL; - if (probe_cpuid_faulting()) + /* + * If there's support for CpuidUserDis or CPUID faulting then + * we can skip levelling because CPUID accesses are trapped anyway. + * + * CPUID faulting is an Intel feature analogous to CpuidUserDis, so + * that can only be present when Xen is itself virtualized (because + * it can be emulated) + */ + if ((cpu_has_hypervisor && probe_cpuid_faulting()) || + boot_cpu_has(X86_FEATURE_CPUID_USER_DIS)) { + expected_levelling_cap |= LCAP_faulting; + levelling_caps |= LCAP_faulting; return; + } probe_masking_msrs(); @@ -363,6 +375,21 @@ static void __init noinline amd_init_levelling(void) ctxt_switch_masking = amd_ctxt_switch_masking; } +void amd_set_cpuid_user_dis(bool enable) +{ + const uint64_t msr_addr = MSR_K8_HWCR; + const uint64_t bit = K8_HWCR_CPUID_USER_DIS; + uint64_t val; + + rdmsrl(msr_addr, val); + + if (!!(val & bit) == enable) + return; + + val ^= bit; + wrmsrl(msr_addr, val); +} + /* * Check for the presence of an AMD erratum. Arguments are defined in amd.h * for each known erratum. Return 1 if erratum is found. diff --git a/xen/arch/x86/cpu/common.c b/xen/arch/x86/cpu/common.c index edc4db1335..9bbb385db4 100644 --- a/xen/arch/x86/cpu/common.c +++ b/xen/arch/x86/cpu/common.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -131,17 +132,6 @@ bool __init probe_cpuid_faulting(void) uint64_t val; int rc; - /* - * Don't bother looking for CPUID faulting if we aren't virtualised on - * AMD or Hygon hardware - it won't be present. Likewise for Fam0F - * Intel hardware. - */ - if (((boot_cpu_data.x86_vendor & (X86_VENDOR_AMD | X86_VENDOR_HYGON)) || - ((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && - boot_cpu_data.x86 == 0xf)) && - !cpu_has_hypervisor) - return false; - if ((rc = rdmsr_safe(MSR_INTEL_PLATFORM_INFO, val)) == 0) raw_cpu_policy.platform_info.cpuid_faulting = val & MSR_PLATFORM_INFO_CPUID_FAULTING; @@ -155,8 +145,6 @@ bool __init probe_cpuid_faulting(void) return false; } - expected_levelling_cap |= LCAP_faulting; - levelling_caps |= LCAP_faulting; setup_force_cpu_cap(X86_FEATURE_CPUID_FAULTING); return true; @@ -179,8 +167,10 @@ static void set_cpuid_faulting(bool enable) void ctxt_switch_levelling(const struct vcpu *next) { const struct domain *nextd = next ? next->domain : NULL; + bool enable_cpuid_faulting; - if (cpu_has_cpuid_faulting) { + if (cpu_has_cpuid_faulting || + boot_cpu_has(X86_FEATURE_CPUID_USER_DIS)) { /* * No need to alter the faulting setting if we are switching * to idle; it won't affect any code running in idle context. @@ -201,12 +191,18 @@ void ctxt_switch_levelling(const struct vcpu *next) * an interim escape hatch in the form of * `dom0=no-cpuid-faulting` to restore the older behaviour. */ - set_cpuid_faulting(nextd && (opt_dom0_cpuid_faulting || - !is_control_domain(nextd) || - !is_pv_domain(nextd)) && - (is_pv_domain(nextd) || - next->arch.msrs-> - misc_features_enables.cpuid_faulting)); + enable_cpuid_faulting = nextd && (opt_dom0_cpuid_faulting || + !is_control_domain(nextd) || + !is_pv_domain(nextd)) && + (is_pv_domain(nextd) || + next->arch.msrs-> + misc_features_enables.cpuid_faulting); + + if (cpu_has_cpuid_faulting) + set_cpuid_faulting(enable_cpuid_faulting); + else + amd_set_cpuid_user_dis(enable_cpuid_faulting); + return; } @@ -415,6 +411,17 @@ static void generic_identify(struct cpuinfo_x86 *c) c->apicid = phys_pkg_id((ebx >> 24) & 0xFF, 0); c->phys_proc_id = c->apicid; + eax = cpuid_eax(0x80000000); + if ((eax >> 16) == 0x8000) + c->extended_cpuid_level = eax; + + /* + * These AMD-defined flags are out of place, but we need + * them early for the CPUID faulting probe code + */ + if (c->extended_cpuid_level >= 0x80000021) + c->x86_capability[FEATURESET_e21a] = cpuid_eax(0x80000021); + if (this_cpu->c_early_init) this_cpu->c_early_init(c); @@ -431,10 +438,6 @@ static void generic_identify(struct cpuinfo_x86 *c) (cpuid_ecx(CPUID_PM_LEAF) & CPUID6_ECX_APERFMPERF_CAPABILITY) ) __set_bit(X86_FEATURE_APERFMPERF, c->x86_capability); - eax = cpuid_eax(0x80000000); - if ((eax >> 16) == 0x8000) - c->extended_cpuid_level = eax; - /* AMD-defined flags: level 0x80000001 */ if (c->extended_cpuid_level >= 0x80000001) cpuid(0x80000001, &tmp, &tmp, diff --git a/xen/arch/x86/cpu/intel.c b/xen/arch/x86/cpu/intel.c index 71fc1a1e18..7e5c657758 100644 --- a/xen/arch/x86/cpu/intel.c +++ b/xen/arch/x86/cpu/intel.c @@ -226,8 +226,17 @@ static void cf_check intel_ctxt_switch_masking(const struct vcpu *next) */ static void __init noinline intel_init_levelling(void) { - if (probe_cpuid_faulting()) + /* Intel Fam0f is old enough that probing for CPUID faulting support + * introduces spurious #GP(0) when the appropriate MSRs are read, + * so skip it altogether. In the case where Xen is virtualized these + * MSRs may be emulated though, so we allow it in that case. + */ + if ((cpu_has_hypervisor || boot_cpu_data.x86 !=0xf) && + probe_cpuid_faulting()) { + expected_levelling_cap |= LCAP_faulting; + levelling_caps |= LCAP_faulting; return; + } probe_masking_msrs(); diff --git a/xen/arch/x86/include/asm/amd.h b/xen/arch/x86/include/asm/amd.h index a975d3de26..09ee52dc1c 100644 --- a/xen/arch/x86/include/asm/amd.h +++ b/xen/arch/x86/include/asm/amd.h @@ -155,5 +155,6 @@ extern bool amd_legacy_ssbd; extern bool amd_virt_spec_ctrl; bool amd_setup_legacy_ssbd(void); void amd_set_legacy_ssbd(bool enable); +void amd_set_cpuid_user_dis(bool enable); #endif /* __AMD_H__ */ From patchwork Fri May 5 17:57:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alejandro Vallejo X-Patchwork-Id: 13232947 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A88EEC77B7F for ; Fri, 5 May 2023 17:57:43 +0000 (UTC) Received: from list by lists.xenproject.org with outflank-mailman.530597.826324 (Exim 4.92) (envelope-from ) id 1puzgI-00077k-9L; Fri, 05 May 2023 17:57:22 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 530597.826324; Fri, 05 May 2023 17:57:22 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1puzgI-00077E-2L; Fri, 05 May 2023 17:57:22 +0000 Received: by outflank-mailman (input) for mailman id 530597; Fri, 05 May 2023 17:57:19 +0000 Received: from se1-gles-sth1-in.inumbo.com ([159.253.27.254] helo=se1-gles-sth1.inumbo.com) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1puzgF-0006Yg-LX for xen-devel@lists.xenproject.org; Fri, 05 May 2023 17:57:19 +0000 Received: from mail-wm1-x334.google.com (mail-wm1-x334.google.com [2a00:1450:4864:20::334]) by se1-gles-sth1.inumbo.com (Halon) with ESMTPS id 4724a395-eb6e-11ed-b226-6b7b168915f2; Fri, 05 May 2023 19:57:19 +0200 (CEST) Received: by mail-wm1-x334.google.com with SMTP id 5b1f17b1804b1-3f315735514so108096885e9.1 for ; Fri, 05 May 2023 10:57:19 -0700 (PDT) Received: from localhost.localdomain (default-46-102-197-194.interdsl.co.uk. [46.102.197.194]) by smtp.gmail.com with ESMTPSA id b12-20020adfe30c000000b00306423904d6sm3053844wrj.45.2023.05.05.10.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 05 May 2023 10:57:16 -0700 (PDT) X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" X-Inumbo-ID: 4724a395-eb6e-11ed-b226-6b7b168915f2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cloud.com; s=cloud; t=1683309438; x=1685901438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d6Xql5GXzmjj1oZIuAO041sn7FGeLxwpchTwgQr2k5s=; b=D0MY9e7uNVDRqXI8XB8j0kmwsJFPVA7488rLg9o/qJf8WaepewgG92ynTMnwvzhgog jnRDm8hfKRRxDpUVXyyGyt+JvmlmGkJY3xY6+QDL+STz9HxbWQxpNgRjSyMfgvqjnbwt rjXVlyagTW6MNShOmpa3YA6meVEmH44P4I7Gw= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683309438; x=1685901438; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d6Xql5GXzmjj1oZIuAO041sn7FGeLxwpchTwgQr2k5s=; b=cxvPjfpLe6hYnoyjg9omWzzY8z/PiA4Z0jC6uHqsLPAIN58aCB7MEg9hpvebBJDaTK Fu9S6ACj/3yfhLToUuifSjRRHs9w1pNQS4g3ECGumw7JDFUb1r7+RKervez7Fv3UbPf6 ud0X9ZRfSB0ZJlNrXFsAg1a8sMVx+iv5mrlfEkf56flGVpIZJqrRjj7QiwZrpO7GqUV4 LA3aaMpG/X0fIrfSyYjrgEEc21tDZSYoEfpfMFFm3qrGVu79dr7KjIzqbe6f/RFql83g pXMWso2cbHW70fre956KHcfIi3ZuvRLTxlooLrv1YXIfwXFH+KMdRp4CKrx7Uo0oYouM JGWA== X-Gm-Message-State: AC+VfDxs88VZWpP9t2Uei2hVs4NBKYmRNWs499F+z6CWqQbdOyR5agIu PYIsl1gYCYkVzDiZ2JdJfOl4z3iXdCtmfR3MDJM= X-Google-Smtp-Source: ACHHUZ7HbbsoCdRLwpKFkeV3KYcoZ2tYunzSdAflnU/lJ4BAM1XJOaXtZDpyoaNJmG9s2CmAuNrwFQ== X-Received: by 2002:a05:600c:3d9a:b0:3f1:6ebd:d995 with SMTP id bi26-20020a05600c3d9a00b003f16ebdd995mr2286776wmb.0.1683309438059; Fri, 05 May 2023 10:57:18 -0700 (PDT) From: Alejandro Vallejo To: Xen-devel Cc: Alejandro Vallejo , Jan Beulich , Andrew Cooper , =?utf-8?q?Roger_Pau_Monn=C3=A9?= , Wei Liu Subject: [PATCH 3/3] x86: Use CpuidUserDis if an AMD HVM guest toggles CPUID faulting Date: Fri, 5 May 2023 18:57:05 +0100 Message-Id: <20230505175705.18098-4-alejandro.vallejo@cloud.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230505175705.18098-1-alejandro.vallejo@cloud.com> References: <20230505175705.18098-1-alejandro.vallejo@cloud.com> MIME-Version: 1.0 This is in order to aid guests of AMD hardware that we have exposed CPUID faulting to. If they try to modify the Intel MSR that enables the feature, trigger levelling so AMD's version of it (CpuidUserDis) is used instead. Signed-off-by: Alejandro Vallejo --- xen/arch/x86/msr.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/xen/arch/x86/msr.c b/xen/arch/x86/msr.c index ecf126566d..984aedf180 100644 --- a/xen/arch/x86/msr.c +++ b/xen/arch/x86/msr.c @@ -431,6 +431,13 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) { bool old_cpuid_faulting = msrs->misc_features_enables.cpuid_faulting; + /* + * The boot CPU must support Intel's CPUID faulting _or_ + * AMD's CpuidUserDis. + */ + bool can_fault_cpuid = cpu_has_cpuid_faulting || + boot_cpu_has(X86_FEATURE_CPUID_USER_DIS); + rsvd = ~0ull; if ( cp->platform_info.cpuid_faulting ) rsvd &= ~MSR_MISC_FEATURES_CPUID_FAULTING; @@ -440,7 +447,7 @@ int guest_wrmsr(struct vcpu *v, uint32_t msr, uint64_t val) msrs->misc_features_enables.raw = val; - if ( v == curr && is_hvm_domain(d) && cpu_has_cpuid_faulting && + if ( v == curr && is_hvm_domain(d) && can_fault_cpuid && (old_cpuid_faulting ^ msrs->misc_features_enables.cpuid_faulting) ) ctxt_switch_levelling(v); break;