From patchwork Sat May 6 10:08:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Kumar, Udit" X-Patchwork-Id: 13233478 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2C993C77B7F for ; Sat, 6 May 2023 10:10:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=8aBP4ZC2hN/phRCUIlpR+emTl9dDcqyM7DhIk8D4wGo=; b=JYyoF6uB4Npkls NDQ+DeRehRqpfjtSdNaNL7QrjtE8HjbEkXht9BQoxVQ21Lq8RhZJkrV1WS1+ig8gAhokQ4lQvGE8S aNFTOIjEJgYxxzK5cT0PbwoSmlrS9tJP5roIdc30RSKgqdDJsuDSCmbQ5FcIsTMlIjhvrqqqOt5jo HqLDrEuFjvI0F8iwSooKkjoeu/KbUTvsE7PuVkB450Qsbzxbuu/egvrSfBigorvPar+VfeCj/LZy4 gzwk9UUNa13k0fUpHmZXtPY2Sbmgd96Xz7jooxmEto7CaO0P1JmlpkGcm3gVwRgKDTO/GsCGZO3nI iTOa+aT4zpHJy9Ir94Vw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pvEqd-00D39o-2c; Sat, 06 May 2023 10:09:03 +0000 Received: from fllv0016.ext.ti.com ([198.47.19.142]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pvEqa-00D390-2W for linux-arm-kernel@lists.infradead.org; Sat, 06 May 2023 10:09:02 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 346A8iqt097916; Sat, 6 May 2023 05:08:44 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1683367724; bh=ZcGs+6i6xW4Yu7JgT5yx4TaDMr7IDnOHdOmGqI71KKE=; h=From:To:CC:Subject:Date; b=q7NV2Kl9IHFFShNgd9OZoDYL1x39PLuxG4GFBiiMc1qTzWYcMkhwI4hm81v46R6+M 4d7xL7wVX1eoQ+9VlqUCUVNvf5Ps209LisemW9C7BEG5yso8RlhlgyuuhPcToGtuy0 9DSfSPpdaQLSsol8V+WDVXXGOWDJzD6yWHMCquK4= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 346A8iew118434 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sat, 6 May 2023 05:08:44 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sat, 6 May 2023 05:08:43 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sat, 6 May 2023 05:08:43 -0500 Received: from udit-HP-Z2-Tower-G9-Workstation-Desktop-PC.dhcp.ti.com (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 346A8eAu025949; Sat, 6 May 2023 05:08:40 -0500 From: Udit Kumar To: , , , , , , , , , CC: Udit Kumar Subject: [RFC PATCH v2] arm64: dts: ti: k3-j721s2: Add reserved status in msmc node. Date: Sat, 6 May 2023 15:38:26 +0530 Message-ID: <20230506100826.1525641-1-u-kumar1@ti.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230506_030900_963953_EFC3487F X-CRM114-Status: GOOD ( 11.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org TI K3 SOCs have msmc sram, part of it can be configured as L3 cache depending upon system firmware configuration file. This could be possible to have no L3 cache or variable size of L3 cache. In either case top of 64KB of SRAM has to be reserved for system firmware called tifs. https://software-dl.ti.com/tisci/esd/latest/2_tisci_msgs/general/core.html?highlight=msmc Section: TISCI_MSG_QUERY_MSMC. But u-boot as part of fix up is deleting sysfw and l3cache node before passing DT to OS https://github.com/u-boot/u-boot/blob/master/arch/arm/mach-k3/common.c#L412 But keeping tifs subnode as is, tifs subnode memory region is also not accessible to OS. In my view we can handle in two ways 1) delete tifs node as well In this case, only accessible sram will be visible to OS https://lore.kernel.org/all/20230420081128.3617214-1-u-kumar1@ti.com/ 2) make these nodes (tifs, atf and l3cache) as reserved, so that OS has complete view of memory. This is patch for option 2 to mark atf, l3-cache and tifs as reserved. and let u-boot to set correct size for these nodes as part of runtime fixup. Nishanth suggested to discuss in k.org group https://lore.kernel.org/all/20230502230022.5pjywy6h7oqrkmwh@elusive/ So sending this patch for suggestion for selection right option. Also other options are welcome. Signed-off-by: Udit Kumar --- Changes since v1: https://lore.kernel.org/all/20230503144706.1265672-1-u-kumar1@ti.com/ - remove cover letter for 1 patch arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index 2dd7865f7654..791993060f44 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -14,14 +14,17 @@ msmc_ram: sram@70000000 { ranges = <0x0 0x0 0x70000000 0x400000>; atf-sram@0 { + status = "reserved"; reg = <0x0 0x20000>; }; tifs-sram@1f0000 { + status = "reserved"; reg = <0x1f0000 0x10000>; }; l3cache-sram@200000 { + status = "reserved"; reg = <0x200000 0x200000>; }; };