From patchwork Mon May 8 12:47:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13234497 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id EFD9DC77B7F for ; Mon, 8 May 2023 12:52:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 866A310E281; Mon, 8 May 2023 12:51:59 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0953510E27E for ; Mon, 8 May 2023 12:51:57 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683550317; x=1715086317; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XqgeCestFlTlWqj3F4Q7RCVmHUWZ4b3AHXnkF/UhdX0=; b=nBH0B9bO0eEdZ9PeHO+dYCLt1fidB2uH80fh1wg6eBUEwijcSvv3Wgn8 IKAvya8GLC+GOpwWYK5VwWs06l9yduRMrrpRwC78v0EGJ18lEAhQ1RbLO 0jsLVFRpjXk0NGUB3/Tuy9nBI2tYrLHfwbXfTSLF48kYxkDT68TyZW0fI bmb0fy1rq/zC5uNWm8dU1q95LMwoMO4ZvbhEeHGi6gOvbIyn6HNkAwipX We09NPf85+ot98MVnZS2SNxS2K9C6/4gcAT4Vt0c9ViucLlZbEGYoQUDY qNpHJc7kj6+plXnaj422hJBiEKOKCv9P/yHo1WatmAHKBi35Nl86Myfw3 A==; X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329994799" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="329994799" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:51:56 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="842675300" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="842675300" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:51:55 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 8 May 2023 18:17:10 +0530 Message-Id: <20230508124715.2242478-2-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> References: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 1/6] drm/i915/dp: Consider output_format while computing dsc bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" While using DSC the compressed bpp is computed assuming RGB output format. Consider the output_format and compute the compressed bpp during mode valid and compute config steps. For DP-MST we currently use RGB output format only, so continue using RGB while computing compressed bpp for MST case. v2: Use output_bpp instead for pipe_bpp to clamp compressed_bpp. (Ville) Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 19 +++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 1 + 3 files changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0cc57681dc4d..263c30948117 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -734,6 +734,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner, + enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots) { @@ -758,6 +759,10 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, bits_per_pixel = ((link_clock * lane_count) * timeslots) / (intel_dp_mode_to_fec_clock(mode_clock) * 8); + /* Bandwidth required for 420 is half, that of 444 format */ + if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) + bits_per_pixel *= 2; + drm_dbg_kms(&i915->drm, "Max link bpp is %u for %u timeslots " "total bw %u pixel clock %u\n", bits_per_pixel, timeslots, @@ -1151,11 +1156,16 @@ intel_dp_mode_valid(struct drm_connector *_connector, if (HAS_DSC(dev_priv) && drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + enum intel_output_format sink_format, output_format; + int pipe_bpp; + + sink_format = intel_dp_sink_format(connector, mode); + output_format = intel_dp_output_format(connector, sink_format); /* * TBD pass the connector BPC, * for now U8_MAX so that max BPC on that platform would be picked */ - int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); /* * Output bpp is stored in 6.4 format so right shift by 4 to get the @@ -1175,6 +1185,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, target_clock, mode->hdisplay, bigjoiner, + output_format, pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, @@ -1707,6 +1718,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, + pipe_config->output_format, pipe_bpp, timeslots); /* @@ -1742,9 +1754,12 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * calculation procedure is bit different for MST case. */ if (compute_pipe_bpp) { + u16 output_bpp = intel_dp_output_bpp(pipe_config->output_format, + pipe_config->pipe_bpp); + pipe_config->dsc.compressed_bpp = min_t(u16, dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index ef39e4f7a329..db86c2b71c1f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -107,6 +107,7 @@ u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, u32 link_clock, u32 lane_count, u32 mode_clock, u32 mode_hdisplay, bool bigjoiner, + enum intel_output_format output_format, u32 pipe_bpp, u32 timeslots); u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 63d61e610210..ee28bb89bffe 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -973,6 +973,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, target_clock, mode->hdisplay, bigjoiner, + INTEL_OUTPUT_FORMAT_RGB, pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, From patchwork Mon May 8 12:47:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13234498 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F077C7EE26 for ; Mon, 8 May 2023 12:52:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 63EA210E282; Mon, 8 May 2023 12:52:01 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id A648110E281 for ; Mon, 8 May 2023 12:51:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683550318; x=1715086318; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iAadFXnkWqcQNACvR6t+jtKxjs0cQRsVzqc4Lxvyz2A=; b=E1ygNn0IsVHAruQT+G2jvbnZ4p+tjV792wnD34g6btFcyFJaBFl915hv B/+qYhTidC5WH583pZ54PQ0QJ9EcUNX/H7z73YkaypAzJ13zIEWiLW4rK pOCwioUN+0HlJEU1GDsqbmgpgW8/JJ8zDjX6HtGbx09vAMScOeF6v7ZR6 ID7+5QYmpD6S/wxmQ+uc3Kd7LYQVhAzxEf+UgfDZddk9K+4i6mk8vrUjp iDAEinf2P544WeAOvEFe1U2lsNzKIr7XL7fQDmBrUyvGAdG+igtMdAJdu HUFaBJ3TiwEc3hc14ux4OmExG/sbpVAG/xChCAacd8FU37g3TjlK5Jrce Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329994807" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="329994807" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:51:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="842675320" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="842675320" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:51:56 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 8 May 2023 18:17:11 +0530 Message-Id: <20230508124715.2242478-3-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> References: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/6] drm/i915/dp_mst: Use output_format to get the final link bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" The final link bpp used to calculate the m_n values depend on the output_format. Though the output_format is set to RGB for MST case and the link bpp will be same as the pipe bpp, for the sake of semantics, lets calculate the m_n values with the link bpp, instead of pipe_bpp. Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 2 +- drivers/gpu/drm/i915/display/intel_dp.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++++- 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 263c30948117..67d09c49de6f 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -946,7 +946,7 @@ int intel_dp_min_bpp(enum intel_output_format output_format) return 8 * 3; } -static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) +int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) { /* * bpp value was assumed to RGB format. And YCbCr 4:2:0 output diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index db86c2b71c1f..856172bfa13e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -140,5 +140,6 @@ void intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, void intel_dp_phy_test(struct intel_encoder *encoder); void intel_dp_wait_source_oui(struct intel_dp *intel_dp); +int intel_dp_output_bpp(enum intel_output_format output_format, int bpp); #endif /* __INTEL_DP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index ee28bb89bffe..2c2d258a3a77 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -155,6 +155,7 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode; int slots = -EINVAL; + int link_bpp; slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp, limits->min_bpp, limits, @@ -163,7 +164,9 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, if (slots < 0) return slots; - intel_link_compute_m_n(crtc_state->pipe_bpp, + link_bpp = intel_dp_output_bpp(crtc_state->output_format, crtc_state->pipe_bpp); + + intel_link_compute_m_n(link_bpp, crtc_state->lane_count, adjusted_mode->crtc_clock, crtc_state->port_clock, From patchwork Mon May 8 12:47:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13234499 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 94ACFC77B7F for ; Mon, 8 May 2023 12:52:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id DD4F210E287; Mon, 8 May 2023 12:52:04 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2E66810E287 for ; Mon, 8 May 2023 12:52:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683550322; x=1715086322; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5ymNAmzFTdias85UIppFw+0oIdYPTXfHa32LlrOSsJE=; b=GIw6wt5d+IeEdAG2wDXs7XNQNO4lVE1lABuO8VkLsN1pO1Z+nFVjERjb 6NgyjcVSJ4N5GdBGkOLcxquxWSbex89MiIGxJL1O7lHDhSLAkMa6i5beQ HMln/3pyBnwPa0X+7kJ6s1ucKyNuyVdsS1V+FqBd0kka0rrf/0ZASOry0 2MMk2NuaIVOvB4qUv4Q9xQnYTp+YJnXKMLL2Qdwf1Dv77bhMEHGWiY1qt 5O3+07AHs5tbddADTDoniDGqPxOAZFRZFGdf7VDLJTgzRpPQwog/SjFxm 5E9Y5aUYb+15xPDIlI0bSVtfYEsaBmhag44AUXUM4FVJcvT5cOccQwqnn w==; X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329994810" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="329994810" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:52:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="842675326" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="842675326" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:51:58 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 8 May 2023 18:17:12 +0530 Message-Id: <20230508124715.2242478-4-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> References: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 3/6] drm/i915/dp: Use consistent name for link bpp and compressed bpp X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently there are many places where we use output_bpp for link bpp and compressed bpp. Lets use consistent naming: output_bpp : The intermediate value taking into account the output_format chroma subsampling. compressed_bpp : target bpp for the DSC encoder. link_bpp : final bpp used in the link. For 444 sampling without DSC: link_bpp = output_bpp = pipe_bpp For 420 sampling without DSC: output_bpp = pipe_bpp / 2 link_bpp = output_bpp For 444 sampling with DSC: output_bpp = pipe_bpp link_bpp = compressed_bpp, computed with output_bpp (i.e. pipe_bpp in this case) For 420 sampling with DSC: output_bpp = pipe_bpp/2 link_bpp = compressed_bpp, computed with output_bpp Signed-off-by: Ankit Nautiyal Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/display/intel_dp.c | 88 +++++++++++---------- drivers/gpu/drm/i915/display/intel_dp.h | 14 ++-- drivers/gpu/drm/i915/display/intel_dp_mst.c | 22 +++--- 3 files changed, 63 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 67d09c49de6f..24de25551a49 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -730,13 +730,13 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p return bits_per_pixel; } -u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - enum intel_output_format output_format, - u32 pipe_bpp, - u32 timeslots) +u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + enum intel_output_format output_format, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; @@ -1117,7 +1117,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, int target_clock = mode->clock; int max_rate, mode_rate, max_lanes, max_link_clock; int max_dotclk = dev_priv->max_dotclk_freq; - u16 dsc_max_output_bpp = 0; + u16 dsc_max_compressed_bpp = 0; u8 dsc_slice_count = 0; enum drm_mode_status status; bool dsc = false, bigjoiner = false; @@ -1172,21 +1172,21 @@ intel_dp_mode_valid(struct drm_connector *_connector, * integer value since we support only integer values of bpp. */ if (intel_dp_is_edp(intel_dp)) { - dsc_max_output_bpp = + dsc_max_compressed_bpp = drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; dsc_slice_count = drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, true); } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { - dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - max_link_clock, - max_lanes, - target_clock, - mode->hdisplay, - bigjoiner, - output_format, - pipe_bpp, 64) >> 4; + dsc_max_compressed_bpp = + intel_dp_dsc_get_max_compressed_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + output_format, + pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1194,7 +1194,7 @@ intel_dp_mode_valid(struct drm_connector *_connector, bigjoiner); } - dsc = dsc_max_output_bpp && dsc_slice_count; + dsc = dsc_max_compressed_bpp && dsc_slice_count; } /* @@ -1476,9 +1476,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, int mode_rate, link_rate, link_avail; for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { - int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); + int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); - mode_rate = intel_dp_link_required(clock, output_bpp); + mode_rate = intel_dp_link_required(clock, link_bpp); for (i = 0; i < intel_dp->num_common_rates; i++) { link_rate = intel_dp_common_rate(intel_dp, i); @@ -1707,20 +1707,20 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } } else { - u16 dsc_max_output_bpp = 0; + u16 dsc_max_compressed_bpp = 0; u8 dsc_dp_slice_count; if (compute_pipe_bpp) { - dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - pipe_config->port_clock, - pipe_config->lane_count, - adjusted_mode->crtc_clock, - adjusted_mode->crtc_hdisplay, - pipe_config->bigjoiner_pipes, - pipe_config->output_format, - pipe_bpp, - timeslots); + dsc_max_compressed_bpp = + intel_dp_dsc_get_max_compressed_bpp(dev_priv, + pipe_config->port_clock, + pipe_config->lane_count, + adjusted_mode->crtc_clock, + adjusted_mode->crtc_hdisplay, + pipe_config->bigjoiner_pipes, + pipe_config->output_format, + pipe_bpp, + timeslots); /* * According to DSC 1.2a Section 4.1.1 Table 4.1 the maximum * supported PPS value can be 63.9375 and with the further @@ -1728,9 +1728,11 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, * restricting our target bpp to be 31.9375 at max */ if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) - dsc_max_output_bpp = min_t(u16, dsc_max_output_bpp, 31 << 4); + dsc_max_compressed_bpp = min_t(u16, + dsc_max_compressed_bpp, + 31 << 4); - if (!dsc_max_output_bpp) { + if (!dsc_max_compressed_bpp) { drm_dbg_kms(&dev_priv->drm, "Compressed BPP not supported\n"); return -EINVAL; @@ -1758,7 +1760,7 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, pipe_config->pipe_bpp); pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, + dsc_max_compressed_bpp >> 4, output_bpp); } pipe_config->dsc.slice_count = dsc_dp_slice_count; @@ -2134,7 +2136,7 @@ static bool can_enable_drrs(struct intel_connector *connector, static void intel_dp_drrs_compute_config(struct intel_connector *connector, struct intel_crtc_state *pipe_config, - int output_bpp) + int link_bpp) { struct drm_i915_private *i915 = to_i915(connector->base.dev); const struct drm_display_mode *downclock_mode = @@ -2159,7 +2161,7 @@ intel_dp_drrs_compute_config(struct intel_connector *connector, if (pipe_config->splitter.enable) pixel_clock /= pipe_config->splitter.link_count; - intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, + intel_link_compute_m_n(link_bpp, pipe_config->lane_count, pixel_clock, pipe_config->port_clock, &pipe_config->dp_m2_n2, pipe_config->fec_enable); @@ -2256,7 +2258,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); const struct drm_display_mode *fixed_mode; struct intel_connector *connector = intel_dp->attached_connector; - int ret = 0, output_bpp; + int ret = 0, link_bpp; if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && encoder->port != PORT_A) pipe_config->has_pch_encoder = true; @@ -2306,10 +2308,10 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_limited_color_range(pipe_config, conn_state); if (pipe_config->dsc.compression_enable) - output_bpp = pipe_config->dsc.compressed_bpp; + link_bpp = pipe_config->dsc.compressed_bpp; else - output_bpp = intel_dp_output_bpp(pipe_config->output_format, - pipe_config->pipe_bpp); + link_bpp = intel_dp_output_bpp(pipe_config->output_format, + pipe_config->pipe_bpp); if (intel_dp->mso_link_count) { int n = intel_dp->mso_link_count; @@ -2333,7 +2335,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_dp_audio_compute_config(encoder, pipe_config, conn_state); - intel_link_compute_m_n(output_bpp, + intel_link_compute_m_n(link_bpp, pipe_config->lane_count, adjusted_mode->crtc_clock, pipe_config->port_clock, @@ -2349,7 +2351,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, intel_vrr_compute_config(pipe_config, conn_state); intel_psr_compute_config(intel_dp, pipe_config, conn_state); - intel_dp_drrs_compute_config(connector, pipe_config, output_bpp); + intel_dp_drrs_compute_config(connector, pipe_config, link_bpp); intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index 856172bfa13e..42b98546c140 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -103,13 +103,13 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); -u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - enum intel_output_format output_format, - u32 pipe_bpp, - u32 timeslots); +u16 intel_dp_dsc_get_max_compressed_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + enum intel_output_format output_format, + u32 pipe_bpp, + u32 timeslots); u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, int mode_clock, int mode_hdisplay, bool bigjoiner); diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 2c2d258a3a77..d92af6122763 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -915,7 +915,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_rate, mode_rate, max_lanes, max_link_clock; int ret; bool dsc = false, bigjoiner = false; - u16 dsc_max_output_bpp = 0; + u16 dsc_max_compressed_bpp = 0; u8 dsc_slice_count = 0; int target_clock = mode->clock; @@ -969,15 +969,15 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { - dsc_max_output_bpp = - intel_dp_dsc_get_output_bpp(dev_priv, - max_link_clock, - max_lanes, - target_clock, - mode->hdisplay, - bigjoiner, - INTEL_OUTPUT_FORMAT_RGB, - pipe_bpp, 64) >> 4; + dsc_max_compressed_bpp = + intel_dp_dsc_get_max_compressed_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + INTEL_OUTPUT_FORMAT_RGB, + pipe_bpp, 64) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -985,7 +985,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, bigjoiner); } - dsc = dsc_max_output_bpp && dsc_slice_count; + dsc = dsc_max_compressed_bpp && dsc_slice_count; } /* From patchwork Mon May 8 12:47:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13234500 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 24A16C77B73 for ; Mon, 8 May 2023 12:52:07 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4B33810E289; Mon, 8 May 2023 12:52:05 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E24710E287 for ; Mon, 8 May 2023 12:52:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683550323; x=1715086323; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O8tPXy2tfQgrW+OJMwmm34SzHzn3kiXDJb8Pp8HbnHc=; b=X9TOyoI8O6PNx6xUgXSHvIGhO22KkYR9VC7/ySe1qflXExSEQAylMuOO fep+OxxUeLzFdIkgjkpILBqjWstx1cNSF2p9N/qsH6zWGmOuonRIav7vH u6+t8Z0TqpNqe5ZHSNdbXq3BCsKcDBkdYoauB0APYEcVtKufA8dIzMsZ7 qYGL5APZ7i8C/mt5+zMb9RJnw8S0vSv7fxAo5MWb5Ap6OnbGCb9w6Rwdi 60lkU653ekv32wVd5uAT3ZYLll+e5ndU63XNjeQxenMjC2ZqkHRi6n0FN 5fDQQmrpyyI0eFf7qzmeO6oGrl/O9XYHDRzA6jpjLRG20PV46WxRuHVs9 w==; X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329994815" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="329994815" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:52:02 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="842675337" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="842675337" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:52:00 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 8 May 2023 18:17:13 +0530 Message-Id: <20230508124715.2242478-5-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> References: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 4/6] drm/i915/dp: Handle BPP where HDMI2.1 DFP doesn't support DSC X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Currently we use the highest input BPC supported by DP sink while using DSC.In cases where PCON with HDMI2.1 as branch device, if PCON supports DSC but HDMI2.1 sink does not supports DSC, The PCON tries to use same input BPC that is used between Source and the PCON without DSC, which might not work even with the maximum FRL rate supported by HDMI2.1 sink. This patch calculates the max BPC that can be sufficient with either RGB or YCBCR420 format for the maximum FRL rate supported. v2: Rebase v3: Use the sink_format in the functions instead of ycbcr420 flag. v4: Rebase Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 60 ++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 24de25551a49..cc126a1a08b5 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -118,6 +118,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) return dig_port->base.type == INTEL_OUTPUT_EDP; } +static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); static void intel_dp_unset_edid(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ @@ -1645,6 +1646,39 @@ static bool intel_dp_dsc_supports_format(struct intel_dp *intel_dp, return drm_dp_dsc_sink_supports_format(intel_dp->dsc_dpcd, sink_dsc_format); } +static int +intel_dp_pcon_hdmi21_get_bpp_nodsc(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + int max_bpc) +{ + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; + const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int req_rate_gbps; + int max_frl_rate = connector->display_info.hdmi.max_lanes * + connector->display_info.hdmi.max_frl_rate_per_lane; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (dsc_bpc[i] > max_bpc) + continue; + + req_rate_gbps = DIV_ROUND_UP(dsc_bpc[i] * 3 * adjusted_mode->clock, 1000000); + + /* YCBCR420 reduces data rate by 2 */ + if (pipe_config->sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + req_rate_gbps /= 2; + + if (req_rate_gbps < max_frl_rate) + return dsc_bpc[i] * 3; + } + + return 0; +} + int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state, @@ -1653,6 +1687,8 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, bool compute_pipe_bpp) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct intel_connector *intel_connector = intel_dp->attached_connector; + struct drm_connector *connector = &intel_connector->base; struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; @@ -1668,10 +1704,30 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, if (!intel_dp_dsc_supports_format(intel_dp, pipe_config->output_format)) return -EINVAL; - if (compute_pipe_bpp) + /* + * In cases where PCON with HDMI2.1 as branch device, if PCON supports + * DSC but HDMI2.1 sink does not supports DSC, there can be issues due + * to the bpc used. + * With DSC, a source-PCON pair can support the mode with higher bpcs. + * But PCON->Sink pair, cannot support the same bpc without sink having + * DSC support. + * So use the max BPC as input BPC that will be sufficient to show the + * mode without DSC from PCON->HDMI2.1 + */ + if (intel_dp_is_hdmi_2_1_sink(intel_dp) && + !connector->display_info.hdmi.dsc_cap.v_1p2) { + pipe_bpp = intel_dp_pcon_hdmi21_get_bpp_nodsc(intel_dp, pipe_config, + conn_state->max_requested_bpc); + if (!pipe_bpp) { + drm_dbg_kms(&dev_priv->drm, + "No BPC possible to support the mode without HDMI2.1 DSC\n"); + return -EINVAL; + } + } else if (compute_pipe_bpp) { pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); - else + } else { pipe_bpp = pipe_config->pipe_bpp; + } if (intel_dp->force_dsc_bpc) { pipe_bpp = intel_dp->force_dsc_bpc * 3; From patchwork Mon May 8 12:47:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13234501 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E6E9C77B73 for ; Mon, 8 May 2023 12:52:09 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B7DFA10E28B; Mon, 8 May 2023 12:52:08 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2B9B110E287 for ; Mon, 8 May 2023 12:52:04 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1683550324; x=1715086324; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zR+ouCzlvxi8xmEaLmFMoPPTVZhy+ZZw1na0GFmbL7o=; b=PEAVrEfDFPiJ4fOuA9Vai5mbftsGVTPE4nPE5tCDnk7R1fUzxdaz6t4y CfDg/O7tVs5ZXICzQMJtQM7Ef1WdUaLsDG4UdgrcWXrsssRFLmHWBDFAE lgxaSI03sIXXTzWzDy4pQ80/Ntt6vzt3YCWcElG+yglkdAYsv4Ve6P1MN r4E5HuezjHLzmLqPlS//TKAUHFc6prMQCbU23PL01rX5O6gMeBlTndaLm dv6uzGnkxiJFyK1hwr7nxotHHcW3OGE0pCx5ujg9UqHwmnT/q0tz7XEPT 5n7yPaLg+XgEeWG/FRQr/aziYgJmxfmXSZy1BaD5Wj605pj93VIy+R4DD A==; X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="329994826" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="329994826" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:52:04 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10703"; a="842675357" X-IronPort-AV: E=Sophos;i="5.99,259,1677571200"; d="scan'208";a="842675357" Received: from srr4-3-linux-103-aknautiy.iind.intel.com ([10.223.34.160]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 May 2023 05:52:02 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 8 May 2023 18:17:14 +0530 Message-Id: <20230508124715.2242478-6-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> References: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 5/6] drm/i915/dp: Fix FRL BW check for HDMI2.1 DFP X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" During FRL bandwidth check for downstream HDMI2.1 sink, the min BPC supported is incorrectly taken for DP, and the check does not consider ybcr420 only modes. This patch fixes the bandwidth calculation similar to the TMDS case, by taking min 8Bpc and considering Ycbcr420 only modes. v2: Rebase Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 57 ++++++++++++++++++------- 1 file changed, 41 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index cc126a1a08b5..af7d6cdbab11 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -120,6 +120,7 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp); static void intel_dp_unset_edid(struct intel_dp *intel_dp); +static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -1042,6 +1043,32 @@ intel_dp_tmds_clock_valid(struct intel_dp *intel_dp, return MODE_OK; } +static enum drm_mode_status +intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, + int bpc, enum intel_output_format sink_format) +{ + int target_bw; + int max_frl_bw; + int bpp = bpc * 3; + + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420) + target_clock /= 2; + + target_bw = bpp * target_clock; + + /* check for MAX FRL BW for both PCON and HDMI2.1 sink */ + max_frl_bw = min(intel_dp->dfp.pcon_max_frl_bw, + intel_dp_hdmi_sink_max_frl(intel_dp)); + + /* converting bw from Gbps to Kbps*/ + max_frl_bw = max_frl_bw * 1000000; + + if (target_bw > max_frl_bw) + return MODE_CLOCK_HIGH; + + return MODE_OK; +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -1050,23 +1077,23 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, struct intel_dp *intel_dp = intel_attached_dp(connector); const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; - enum intel_output_format sink_format; + enum intel_output_format sink_format = intel_dp_sink_format(connector, mode); /* If PCON supports FRL MODE, check FRL bandwidth constraints */ if (intel_dp->dfp.pcon_max_frl_bw) { - int target_bw; - int max_frl_bw; - int bpp = intel_dp_mode_min_output_bpp(connector, mode); - - target_bw = bpp * target_clock; - - max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; - - /* converting bw from Gbps to Kbps*/ - max_frl_bw = max_frl_bw * 1000000; - - if (target_bw > max_frl_bw) - return MODE_CLOCK_HIGH; + /* Assume 8bpc for the HDMI2.1 FRL BW check */ + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + if (status != MODE_OK) { + if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || + !connector->base.ycbcr_420_allowed || + !drm_mode_is_420_also(info, mode)) + return status; + + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; + status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + if (status != MODE_OK) + return status; + } return MODE_OK; } @@ -1075,8 +1102,6 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - sink_format = intel_dp_sink_format(connector, mode); - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ status = intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true); From patchwork Mon May 8 12:47:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Nautiyal, Ankit K" X-Patchwork-Id: 13234502 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 83AA0C77B7F for ; Mon, 8 May 2023 12:52:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F0A0A10E28D; Mon, 8 May 2023 12:52:08 +0000 (UTC) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by gabe.freedesktop.org (Postfix) with ESMTPS id E055410E28B for ; Mon, 8 May 2023 12:52:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; 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08 May 2023 05:52:04 -0700 From: Ankit Nautiyal To: intel-gfx@lists.freedesktop.org Date: Mon, 8 May 2023 18:17:15 +0530 Message-Id: <20230508124715.2242478-7-ankit.k.nautiyal@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> References: <20230508124715.2242478-1-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 6/6] drm/i915/dp: Add a wrapper to check frl/tmds downstream constraints X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Add a wrapper function to check dp_downstream clock/bandwidth constraints. Based on whether the sink supports FRL/TMDS the wrapper calls the appropriate FRL/TMDS functions. Signed-off-by: Ankit Nautiyal --- drivers/gpu/drm/i915/display/intel_dp.c | 43 +++++++++++-------------- 1 file changed, 18 insertions(+), 25 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index af7d6cdbab11..099465a40080 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -1069,6 +1069,18 @@ intel_dp_frl_bw_valid(struct intel_dp *intel_dp, int target_clock, return MODE_OK; } +static enum drm_mode_status +intel_dp_hdmi_bw_check(struct intel_dp *intel_dp, + int target_clock, int bpc, + enum intel_output_format sink_format, + bool is_frl) +{ + if (is_frl) + return intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); + + return intel_dp_tmds_clock_valid(intel_dp, target_clock, 8, sink_format, true); +} + static enum drm_mode_status intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_mode *mode, @@ -1078,42 +1090,23 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, const struct drm_display_info *info = &connector->base.display_info; enum drm_mode_status status; enum intel_output_format sink_format = intel_dp_sink_format(connector, mode); + bool is_frl = intel_dp->dfp.pcon_max_frl_bw ? true : false; + int bpc = 8; /* Assume 8bpc for the DP++/HDMI/DVI TMDS/FRL bw check */ - /* If PCON supports FRL MODE, check FRL bandwidth constraints */ - if (intel_dp->dfp.pcon_max_frl_bw) { - /* Assume 8bpc for the HDMI2.1 FRL BW check */ - status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); - if (status != MODE_OK) { - if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || - !connector->base.ycbcr_420_allowed || - !drm_mode_is_420_also(info, mode)) - return status; - - sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_frl_bw_valid(intel_dp, target_clock, 8, sink_format); - if (status != MODE_OK) - return status; - } - - return MODE_OK; - } - - if (intel_dp->dfp.max_dotclock && + if (!is_frl && intel_dp->dfp.max_dotclock && target_clock > intel_dp->dfp.max_dotclock) return MODE_CLOCK_HIGH; - /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl); if (status != MODE_OK) { if (sink_format == INTEL_OUTPUT_FORMAT_YCBCR420 || !connector->base.ycbcr_420_allowed || !drm_mode_is_420_also(info, mode)) return status; + sink_format = INTEL_OUTPUT_FORMAT_YCBCR420; - status = intel_dp_tmds_clock_valid(intel_dp, target_clock, - 8, sink_format, true); + status = intel_dp_hdmi_bw_check(intel_dp, target_clock, bpc, sink_format, is_frl); if (status != MODE_OK) return status; }