From patchwork Mon May 8 18:16:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13234801 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A1769C7EE22 for ; Mon, 8 May 2023 18:17:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=tnQ+AE+ABplMGKe/RRx4AMXFLjZvFTnSTJgowSK1Nz0=; b=gDPUU1Sj4UcB4u StAUsek4HNjDxsfwdj5nNnqvmczJMoBtcnrPzan4bRvkZg38VbkEG7DbBYBnn8o9eT6VLdAxri6mo 7GaF2IVCOB6n3NLAOBiAjH1G+TfMx1JNW1hVJLSMxg5MAtlaHolqmVZznhX2WLdKhyLf8I68WsuOe pXu2Eq95o9KzkK415o+JrbygXZ8cZ3pXzVP28afqtV7vdr1EW+hYLpW07RGK6ZbreaqxWMzBmk5kI lYfH6Mbb5x3Q/lglXPD2BX54GWvriH3HOGtQWT7WiaREBnAPVDoiBetPA1K9EFp8QO3DGUApx2e1F rR8dKbJRDLhNNxxYVAaQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pw5Q3-0016dQ-2w; Mon, 08 May 2023 18:17:07 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pw5Pw-0016c8-0z for linux-riscv@lists.infradead.org; Mon, 08 May 2023 18:17:05 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 98CA461EB2; Mon, 8 May 2023 18:16:59 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6522DC433A0; Mon, 8 May 2023 18:16:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569819; bh=05ZEnpDryaZ3pWwm2uM1BaK+nfW//+toX2uQFMeA9T4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=HJGrfWGsDd1s7R5AE+0X9NTaSLnSiTl1CDjI2qlfcq8hhAqOCmAzMcydtEFIvBxYf kEQuQgx6k6zACnTIy2DQIAThvlziT4MzdAtavBoIJ+AoY6AMxPuJU2dXPxW+YKuNqX ZcWyVTekYnD9VAlWfQ/qEk0odrHvs1Z4RfkKOJ84kpsCTlZja+VwTzuSkmWSxSUY65 cAt7YdetUsJq7H6vdJPHzQtJoEEzngINLFx80lTw1eJvepAaziMwmcfh8NXI2fXban nScP2fYPcgIYUuIXBjKAceSEWgoe4x2zOVy7EpGAFoQeSPnkxqFwFQpSmiPXRRgqHR h0Yt4/U4EPHrg== From: Conor Dooley To: linux-riscv@lists.infradead.org Subject: [RFC 1/6] dt-bindings: riscv: clarify what an unversioned extension means Date: Mon, 8 May 2023 19:16:21 +0100 Message-Id: <20230508-decibel-fender-532248c8f8ed@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1402; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=pGmr6rcDfQk2g8LcKq7L3T1Gg5LY7Zpc7WjhfhPcmv8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNqXs1UuN814vn8Sa0ftPPlY/qv0kw/MDHrvlzNnmL fZ+EqTUUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgIkYqjAy9C6zY3LI67n333be fu4JGzQVn7mGCx7aetLUcHrggz8Z6gz/E/Ncdueu3ZM/WX156Ko9SwoPMs54b6hXwKaUckDT+Fw 3NwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230508_111700_409074_06A3F249 X-CRM114-Status: GOOD ( 12.05 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Conor Dooley , Heiko Stuebner , conor@kernel.org, Yangyu Chen , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley C'est la vie, the spec folks reserve the ability to make incompatible changes between major versions of an extension. Their idea of backwards compatibility appears driven by the hardware perspective - it's backwards compatible if a later version is a subset of the existing extension. IOW, if you supported `x` in vN, you still support `x` in vN+1. However in software terms, code that was built for the vN's `x` extension may not work with the new definition. Signed-off-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/riscv/cpus.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index db5253a2a74a..405915b04d69 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -91,6 +91,9 @@ properties: Notably, riscv,isa was defined prior to the creation of the Zicsr and Zifencei extensions and thus "i" implies "zicsr_zifencei". + For the sake of backwards compatibility, an unversioned + extension means that the hart/platform is capable of + supporting version 1.0.0 of the extension. While the isa strings in ISA specification are case insensitive, letters in the riscv,isa string must be all From patchwork Mon May 8 18:16:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13234805 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 59ABFC7EE24 for ; Mon, 8 May 2023 18:17:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=vxxPIrred1e6+bk7h9JOoG2kD9dmSlh/tVevQgd4CHs=; b=fhJTuma3XOsBJf aa0k/zwXFnMYXpQZwJKhm/WouEv8A/VyS8Qgd49+i8tBf+JwmdVTlM5938DiPT1Rznf/LdQPKCMRQ 8RKSUdVlCkW2YCeoF+cS3Xtzw+kgu7t5riwVPBQ4Kpk3h4Am+GOYChCAAw5yQ0sI6sqHFcriOZAuH gaISmPKQsBxCQsByh9teMsxViVSH3AfL7u1pGprHd7mKRe+95IJJSO8ZLh/BteYttR3d9GiaGqZIp LAK0g5V+/RnF5IRllCtmarsnYBFXgWAnxFTnfsApXAjUCWbL+4hg2MYh4TghtWFl+bUDF806dlof+ TfDswYhwB5YidS7FUhNw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pw5Q3-0016d9-1I; Mon, 08 May 2023 18:17:07 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pw5Pz-0016ca-17 for linux-riscv@lists.infradead.org; Mon, 08 May 2023 18:17:05 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id AC02B62F14; Mon, 8 May 2023 18:17:02 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7550CC4339C; Mon, 8 May 2023 18:16:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569822; bh=pEkQiWBINoXiTLpYTJ+D1743e4SOfUpdwjwXGQmi2Nk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LpCAVUaxcJjhoad5gbeqsUQCfaua+zg6IbA5rkPbTdwywu2JKINyDuAdkH7BIzECp FGXurYzC2J/OgJgceOMyePFn0+i9ll10Xs7l1qSVdNvvZmGQFn5BlxkCIGLPSCU7Zx 78U2CcMMAvcG+15+JBjCBSaHVNmjA/4WRs7O0R7+7JCOnbBBn/KbvcH0TYsXod7j71 hJ82onfdcnNyPY9edo8xz8xHVmu1Mt1BZLTmb8YdVvVRKz9ntuemhnyiTB9LFKPwhL EJ7W6SOmU2xtJe/ihfsP/hpaThNWYHyze+7zwmOAwvF44liqTxobAPUbWEHYwRZaO5 6VNDvFIWa1yPA== From: Conor Dooley To: linux-riscv@lists.infradead.org Subject: [RFC 2/6] dt-bindings: riscv: add riscv,isa-extension-* property and incompatible example Date: Mon, 8 May 2023 19:16:22 +0100 Message-Id: <20230508-sneeze-cesarean-d1aff8be9cc8@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3388; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=mr+KTOsZI6CeMW3M1d3JDMm2IRvhFpi9WHx/17JxyMg=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNqUqQpc3/nj4h//xeaPUtb86SlI0GVYZLykrf5tq+ 1RzZ5FJRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbyTIPhn7rL/Jb6hHuPuW2L P6o2LojcddjYO/DrjX82F5QKUw7fvsvwT2F1xbvzjdWcjxW2+t92Welp6KV85kzi7oD8O1f7eI/ 5cgEA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230508_111703_472573_34AFD301 X-CRM114-Status: GOOD ( 14.02 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Conor Dooley , Heiko Stuebner , conor@kernel.org, Yangyu Chen , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley This dt-binding is illustrative *only*, it doesn't yet do what I want it to do in terms of enforcement etc. I am yet to figure out exactly how to wrangle the binding such that the individual properties have more generous versions than the generic pattern property. This binding *will* generate errors, and needs rework before it can seriously be considered. Nevertheless, it should demonstrate how I intend such a property be used. Not-signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/cpus.yaml | 61 ++++++++++++++++++- 1 file changed, 60 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 405915b04d69..cccb3b2ae23d 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -100,6 +100,15 @@ properties: lowercase. $ref: "/schemas/types.yaml#/definitions/string" pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + deprecated: true + + riscv,isa-base: + description: + Identifies the base ISA supported by a hart. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - rv32i + - rv64i # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false @@ -136,8 +145,32 @@ properties: DMIPS/MHz, relative to highest capacity-dmips-mhz in the system. + riscv,isa-extension-v: + description: RISC-V Vector extension + $ref: "/schemas/types.yaml#/definitions/string" + oneOf: + - const: v1.0.0 + description: the original incarnation + - const: v1.0.1 + description: backwards compat was broken here + +patternProperties: + "^riscv,isa-extension-*": + description: + Catch-all property for ISA extensions that do not need any special + handling, and of which all known versions are compatible with their + original revision. + $ref: "/schemas/types.yaml#/definitions/string" + enum: + - v1.0.0 + +oneOf: + - required: + - riscv,isa-base + - required: + - riscv,isa + required: - - riscv,isa - interrupt-controller additionalProperties: true @@ -208,4 +241,30 @@ examples: }; }; }; + + - | + // Example 3: Extension specification + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + reg = <0>; + compatible = "riscv"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v2.0.0"; + riscv,isa-extension-v = "v1.0.1"; + mmu-type = "riscv,sv48"; + interrupt-controller { + #interrupt-cells = <1>; + interrupt-controller; + compatible = "riscv,cpu-intc"; + }; + }; + }; ... From patchwork Mon May 8 18:16:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13234802 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7EDE2C7EE2A for ; Mon, 8 May 2023 18:17:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:References:In-Reply-To: Message-Id:Date:Subject:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=x43IEqJZS3Z5NPfQ8chlfRIPzuY4M48Zcj8D1QCFYB0=; b=p5KBXXulpwFm34 Pq3/vpJTtJjhr37yQJ3SeNxqVHQ0iXSri2MuYHyue7UdUzUDtUa04mCWWYT0/agoPz+1ouezQZq7P xkakWfKVRG4O2UMeqmWWkGRq/CBs6vp9y8pEHLNLc6e1UvCtjNTsem2Gm1sdxT6Stxjpw2Q4TNNIg 5qYOdXkd6IEBZWD5lhpXr8Tia+p/OCd6E2EStAOjQ5DLrWxhos+c1/pFMHJdzgdwe5vCRC9xJlzSa ChCf228e4HXkdX1Ks0s0qU89hRYRuya6/YCSLMfXuonEGSTkvzDvM7hrJ8CixsigPKXo5LWpNqPim lYP74V8YZ08zELeKiVvA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.96 #2 (Red Hat Linux)) id 1pw5QA-0016eb-1o; Mon, 08 May 2023 18:17:14 +0000 Received: from dfw.source.kernel.org ([139.178.84.217]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pw5Q3-0016d3-1H for linux-riscv@lists.infradead.org; Mon, 08 May 2023 18:17:13 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B98C062F0F; Mon, 8 May 2023 18:17:05 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 834AEC433D2; Mon, 8 May 2023 18:17:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569825; bh=m1G1BRdMTCNy9nabH55EoneK/uJPRkjoflMbNgoNWdo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mcnCkZ46j6oxLE98sDmh6+9bihhKsTWmz/1OOC5GKP0XmkLqaeqADDLokqO8i2yeg f04WfpOOh7G2n8F6cSgdUhEastHka1mlLkZIt8mtRKnp102avvMJYzENux1Z1+LXWi P45lZp21BpAkhV0PLNbuN2gnXbJJNB8y+QwDKcEhK+a23j8B4c4D1YJZoP0o8uU0o5 s1b4gEScPK7oi5WCNBNwmxZzWzsEu3Q5F+EZ5PNTPED9CUMXQbSQQ4hlvQlIT8JXS0 sDQeJYlgXljowOIh7WXW9HrHs/FSF+Fc2Rlh2onuZWEzxvMW5Lxub/6uJkX6Ahtgp9 Kl5lM+98qEjsA== From: Conor Dooley To: linux-riscv@lists.infradead.org Subject: [RFC 3/6] RISC-V: deprecate riscv,isa & replace it with per-extension properties Date: Mon, 8 May 2023 19:16:23 +0100 Message-Id: <20230508-luckiness-skimmer-c4a3b7ab35d5@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9031; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=EZX0K7JP6BwAIxrZk7szxRZe/KOVJqORkMa2rW8UkA8=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNmUsmly+aqoNO8qY/Se3cc8z/vUgrPzTF9uyFfaz5 W76Oid2lLIwiHEwyIopsiTe7muRWv/HZYdzz1uYOaxMIEMYuDgFYCJaQYwMzdHcGhn2hzleHot9 oZnw3y1gkccVxZds0QaVe47yhRg5MvyVmOnHZ/3B7/Dq1NSigrbymr6wqomP+XIq6gz29F1W4WQ GAA== X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230508_111707_536925_B860E7C3 X-CRM114-Status: GOOD ( 20.70 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Conor Dooley , Heiko Stuebner , conor@kernel.org, Yangyu Chen , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley riscv,isa is a bit of a problem-in-waiting, as we don't have control over what the extensions mean. Give us the ability to define what the versions of an extension mean, and provide a compatible-like interface for a dts to specify which known-version of an extension a hart is compatible with. Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 25 +++++- arch/riscv/kernel/cpufeature.c | 147 +++++++++++++++++++++++++++------ 2 files changed, 146 insertions(+), 26 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index aa61031f7923..f963a7a82ce1 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -14,15 +14,20 @@ #include #define RISCV_ISA_EXT_a ('a' - 'a') +#define RISCV_ISA_EXT_b ('b' - 'a') #define RISCV_ISA_EXT_c ('c' - 'a') #define RISCV_ISA_EXT_d ('d' - 'a') #define RISCV_ISA_EXT_f ('f' - 'a') #define RISCV_ISA_EXT_h ('h' - 'a') #define RISCV_ISA_EXT_i ('i' - 'a') +#define RISCV_ISA_EXT_j ('j' - 'a') +#define RISCV_ISA_EXT_k ('k' - 'a') #define RISCV_ISA_EXT_m ('m' - 'a') +#define RISCV_ISA_EXT_p ('p' - 'a') +#define RISCV_ISA_EXT_q ('q' - 'a') #define RISCV_ISA_EXT_s ('s' - 'a') #define RISCV_ISA_EXT_u ('u' - 'a') - +#define RISCV_ISA_EXT_v ('v' - 'a') /* * These macros represent the logical IDs of each multi-letter RISC-V ISA * extension and are used in the ISA bitmap. The logical IDs start from @@ -61,6 +66,24 @@ struct riscv_isa_ext_data { unsigned int isa_ext_id; }; +struct riscv_isa_extension { + const u64 key; + const char *name; + const char *version; + const char *prop_name; + const bool multi_letter; +}; + +#define RISCV_ISA_EXT_CFG(_name, _key, _version, _multi) { \ + .name = #_name, \ + .prop_name = "riscv,isa-extension-" #_name, \ + .key = _key, \ + .version = _version, \ + .multi_letter = _multi, \ +} + +extern const struct riscv_isa_extension riscv_isa_extensions[]; + unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 92f0e7b78eef..1ead76adf60f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -93,12 +93,39 @@ static bool riscv_isa_extension_check(int id) return true; } -void __init riscv_fill_hwcap(void) +const struct riscv_isa_extension riscv_isa_extensions[] = { + RISCV_ISA_EXT_CFG(i, RISCV_ISA_EXT_i, "v1.0.0", false), + RISCV_ISA_EXT_CFG(m, RISCV_ISA_EXT_m, "v1.0.0", false), + RISCV_ISA_EXT_CFG(a, RISCV_ISA_EXT_a, "v1.0.0", false), + RISCV_ISA_EXT_CFG(f, RISCV_ISA_EXT_f, "v1.0.0", false), + RISCV_ISA_EXT_CFG(d, RISCV_ISA_EXT_d, "v1.0.0", false), + RISCV_ISA_EXT_CFG(q, RISCV_ISA_EXT_q, "v1.0.0", false), + RISCV_ISA_EXT_CFG(c, RISCV_ISA_EXT_c, "v1.0.0", false), + RISCV_ISA_EXT_CFG(b, RISCV_ISA_EXT_b, "v1.0.0", false), + RISCV_ISA_EXT_CFG(k, RISCV_ISA_EXT_k, "v1.0.0", false), + RISCV_ISA_EXT_CFG(j, RISCV_ISA_EXT_j, "v1.0.0", false), + RISCV_ISA_EXT_CFG(p, RISCV_ISA_EXT_p, "v1.0.0", false), + RISCV_ISA_EXT_CFG(v, RISCV_ISA_EXT_v, "v1.0.0", false), + RISCV_ISA_EXT_CFG(h, RISCV_ISA_EXT_h, "v1.0.0", false), + RISCV_ISA_EXT_CFG(zicbom, RISCV_ISA_EXT_ZICBOM, "v1.0.0", true), + RISCV_ISA_EXT_CFG(zicboz, RISCV_ISA_EXT_ZICBOZ, "v1.0.0", true), + RISCV_ISA_EXT_CFG(zicsr, RISCV_ISA_EXT_ZICSR, "v1.0.0", true), + RISCV_ISA_EXT_CFG(zifencei, RISCV_ISA_EXT_ZIFENCEI, "v1.0.0", true), + RISCV_ISA_EXT_CFG(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE, "v1.0.0", true), + RISCV_ISA_EXT_CFG(zbb, RISCV_ISA_EXT_ZBB, "v1.0.0", true), + RISCV_ISA_EXT_CFG(sscofpmf, RISCV_ISA_EXT_SSCOFPMF, "v1.0.0", true), + RISCV_ISA_EXT_CFG(sstc, RISCV_ISA_EXT_SSTC, "v1.0.0", true), + RISCV_ISA_EXT_CFG(svinval, RISCV_ISA_EXT_SVINVAL, "v1.0.0", true), + RISCV_ISA_EXT_CFG(svnapot, RISCV_ISA_EXT_SVNAPOT, "v1.0.0", true), + RISCV_ISA_EXT_CFG(svpbmt, RISCV_ISA_EXT_SVPBMT, "v1.0.0", true), + RISCV_ISA_EXT_CFG("", RISCV_ISA_EXT_MAX, "", false), +}; + +static void __init riscv_fill_hwcap_isa_string(void) { struct device_node *node; const char *isa; - char print_str[NUM_ALPHA_EXTS + 1]; - int i, j, rc; + int rc; unsigned long isa2hwcap[26] = {0}; unsigned int cpu; @@ -109,13 +136,12 @@ void __init riscv_fill_hwcap(void) isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; - elf_hwcap = 0; - - bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); + pr_info("Falling back to reading hwcap from deprecated riscv,isa\n"); for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); node = of_cpu_device_node_get(cpu); if (!node) { @@ -138,7 +164,6 @@ void __init riscv_fill_hwcap(void) */ isa += 4; - bitmap_zero(this_isa, RISCV_ISA_EXT_MAX); while (*isa) { const char *ext = isa++; const char *ext_end = isa; @@ -278,26 +303,77 @@ void __init riscv_fill_hwcap(void) set_bit(nr, this_isa); } } else { - /* sorted alphabetically */ - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); - SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); - SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); - SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB); - SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); - SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ); - SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + for (int i = 0; i < ARRAY_SIZE(riscv_isa_extensions); i++) + SET_ISA_EXT_MAP(riscv_isa_extensions[i].name, riscv_isa_extensions[i].key); } #undef SET_ISA_EXT_MAP } - /* - * Linux requires Zicsr & Zifencei, so we may as well always - * set them. - */ - set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa); - set_bit(RISCV_ISA_EXT_ZICSR, this_isa); + /* + * Linux requires Zicsr & Zifencei, so we may as well always + * set them. + */ + set_bit(RISCV_ISA_EXT_ZIFENCEI, this_isa); + set_bit(RISCV_ISA_EXT_ZICSR, this_isa); + + /* + * All "okay" hart should have same isa. Set HWCAP based on + * common capabilities of every "okay" hart, in case they don't + * have. + */ + if (elf_hwcap) + elf_hwcap &= this_hwcap; + else + elf_hwcap = this_hwcap; + + if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX)) + bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + else + bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); + } +} + +static bool __init riscv_fill_hwcap_new(void) +{ + struct device_node *node; + bool detected; + unsigned long isa2hwcap[26] = {0}; + unsigned int cpu; + + isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; + isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; + isa2hwcap['a' - 'a'] = COMPAT_HWCAP_ISA_A; + isa2hwcap['f' - 'a'] = COMPAT_HWCAP_ISA_F; + isa2hwcap['d' - 'a'] = COMPAT_HWCAP_ISA_D; + isa2hwcap['c' - 'a'] = COMPAT_HWCAP_ISA_C; + + for_each_possible_cpu(cpu) { + unsigned long this_hwcap = 0; + DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); + + node = of_cpu_device_node_get(cpu); + if (!node) { + pr_warn("Unable to find cpu node\n"); + continue; + } + + for (int k = 0; k < ARRAY_SIZE(riscv_isa_extensions) - 1; k++) { + const char *tmp; + + of_property_read_string(node, riscv_isa_extensions[k].prop_name, &tmp); + if (!tmp) + continue; + + detected = true; + + if (riscv_isa_extension_check(riscv_isa_extensions[k].key) && + !strcmp(riscv_isa_extensions[k].version, tmp)) { + if (!riscv_isa_extensions[k].multi_letter) + this_hwcap |= isa2hwcap[riscv_isa_extensions[k].key]; + + set_bit(riscv_isa_extensions[k].key, this_isa); + } + } /* * All "okay" hart should have same isa. Set HWCAP based on @@ -315,8 +391,29 @@ void __init riscv_fill_hwcap(void) bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); } - /* We don't support systems with F but without D, so mask those out - * here. */ + return detected; +} + +void __init riscv_fill_hwcap(void) +{ + char print_str[NUM_ALPHA_EXTS + 1]; + int i, j; + + elf_hwcap = 0; + + bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); + + /* + * Since old dtbs must continue to work just as well/badly as they ever + * did, fall back to the isa string if the new method doesn't work. + */ + if (!riscv_fill_hwcap_new()) + riscv_fill_hwcap_isa_string(); + + /* + * We don't support systems with F but without D, so mask those out + * here. + */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { pr_info("This kernel does not support systems with F but not D\n"); elf_hwcap &= ~COMPAT_HWCAP_ISA_F; From patchwork Mon May 8 18:16:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13234806 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 72B46C77B75 for ; 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Mon, 08 May 2023 18:17:17 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pw5Q5-0016dU-0g for linux-riscv@lists.infradead.org; Mon, 08 May 2023 18:17:16 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id C57E462A6B; Mon, 8 May 2023 18:17:08 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 92CB0C4339E; Mon, 8 May 2023 18:17:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569828; bh=gDn1qNH4xsBYthgkWZ/em1+NKvHh2zOBpGtKE3Kkd9E=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fy0R37YJZ+qpMbPvgvndws5ZRECKzZAA0rPv9fBFCZ5RDt6lPp3ZQS9YpHUdlEjs3 EpOsR/MTJRTk3VlrX97HGv9a7dZaitvOksgQ6zNz71wxhTl4tvdMvdZ32hl+/G8+jS HK/UpBPYtWdViiU9JEfj2v7o4AKaeH7V8bXSD72G4srhVpLVBx3mIqP6eBfk4Oo5pn zFhl8eYUIOV5673izj4FirYSR/GfTWDoUuwMhBnlnWtPKdqUx7C2mdZgWSq6TJU4uB BZxlXEvsRfG140EKi9KkXdwwpFa8YMevkljNfeHGlioWEfhm01yHF75OOhj7G/xoGV ZclSh88zLAPIw== From: Conor Dooley To: linux-riscv@lists.infradead.org Subject: [RFC 4/6] RISC-V: add support for riscv,isa-base property Date: Mon, 8 May 2023 19:16:24 +0100 Message-Id: <20230508-village-robotics-54fdbcb96ee5@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=9974; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=X1JoMdz0XypRBvha+Fq4gfZjd7/ZEaml0zIsOaAfMPE=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNmXXEnd9sfxbW63MLP0ksi1Ifovs3piU92fy/Z6vu tU+cf7FjlIWBjEOBlkxRZbE230tUuv/uOxw7nkLM4eVCWQIAxenAExk1TWG/5U/nX4ZKKdNM7rE tHKRs7rYJYlNrRz1kmZOhu6ve+SPljMyvKn+lepQonj+1OM1Vs4T5pR9XOhsr5Y7oSpP4NF1ddE 8dgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230508_111709_333124_6D877E54 X-CRM114-Status: GOOD ( 27.40 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Conor Dooley , Heiko Stuebner , conor@kernel.org, Yangyu Chen , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley I'm not entirely sure if this is needed, but I felt we still needed a mechanism for communicating the base ISA. Perhaps the i here should not even be present, but a way to encode the bit-width is missing from my key-value stuff. Very much open to suggestions on this aspect. Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 8 +-- arch/riscv/kernel/cpu.c | 119 +++++++++------------------------ arch/riscv/kernel/cpufeature.c | 41 ++++++++++++ 3 files changed, 73 insertions(+), 95 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index f963a7a82ce1..cb4b3df0a5d5 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -59,13 +59,6 @@ #include -struct riscv_isa_ext_data { - /* Name of the extension displayed to userspace via /proc/cpuinfo */ - char uprop[RISCV_ISA_EXT_NAME_LEN_MAX]; - /* The logical ISA extension ID */ - unsigned int isa_ext_id; -}; - struct riscv_isa_extension { const u64 key; const char *name; @@ -83,6 +76,7 @@ struct riscv_isa_extension { } extern const struct riscv_isa_extension riscv_isa_extensions[]; +extern const size_t riscv_isa_extensions_count; unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap); diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 0d5d580dca61..c29643dca0f7 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -59,8 +59,25 @@ int riscv_early_of_processor_hartid(struct device_node *node, unsigned long *har return -ENODEV; } + if (of_property_read_string(node, "riscv,isa-base", &isa)) + goto old_interface; + + if (IS_ENABLED(CONFIG_32BIT) && strncasecmp(isa, "rv32i", 5)) + return -ENODEV; + + if (IS_ENABLED(CONFIG_64BIT) && strncasecmp(isa, "rv64i", 5)) + return -ENODEV; + + if (!of_property_present(node, "riscv,isa-extension-m") || + !of_property_present(node, "riscv,isa-extension-a")) + return -ENODEV; + + return 0; + +old_interface: if (of_property_read_string(node, "riscv,isa", &isa)) { - pr_warn("CPU with hartid=%lu has no \"riscv,isa\" property\n", *hart); + pr_warn("CPU with hartid=%lu has no \"riscv,isa-base\" or \"riscv,isa\" property\n", + *hart); return -ENODEV; } @@ -157,106 +174,33 @@ static int __init riscv_cpuinfo_init(void) arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS - -#define __RISCV_ISA_EXT_DATA(UPROP, EXTID) \ - { \ - .uprop = #UPROP, \ - .isa_ext_id = EXTID, \ - } - -/* - * The canonical order of ISA extension names in the ISA string is defined in - * chapter 27 of the unprivileged specification. - * - * Ordinarily, for in-kernel data structures, this order is unimportant but - * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. - * - * The specification uses vague wording, such as should, when it comes to - * ordering, so for our purposes the following rules apply: - * - * 1. All multi-letter extensions must be separated from other extensions by an - * underscore. - * - * 2. Additional standard extensions (starting with 'Z') must be sorted after - * single-letter extensions and before any higher-privileged extensions. - - * 3. The first letter following the 'Z' conventionally indicates the most - * closely related alphabetical extension category, IMAFDQLCBKJTPVH. - * If multiple 'Z' extensions are named, they must be ordered first by - * category, then alphabetically within a category. - * - * 3. Standard supervisor-level extensions (starting with 'S') must be listed - * after standard unprivileged extensions. If multiple supervisor-level - * extensions are listed, they must be ordered alphabetically. - * - * 4. Standard machine-level extensions (starting with 'Zxm') must be listed - * after any lower-privileged, standard extensions. If multiple - * machine-level extensions are listed, they must be ordered - * alphabetically. - * - * 5. Non-standard extensions (starting with 'X') must be listed after all - * standard extensions. If multiple non-standard extensions are listed, they - * must be ordered alphabetically. - * - * An example string following the order is: - * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux - * - * New entries to this struct should follow the ordering rules described above. - */ -static struct riscv_isa_ext_data isa_ext_arr[] = { - __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR), - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ), - __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), - __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), - __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), - __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), - __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), - __RISCV_ISA_EXT_DATA(svnapot, RISCV_ISA_EXT_SVNAPOT), - __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), -}; - static void print_isa_ext(struct seq_file *f) { - struct riscv_isa_ext_data *edata; int i = 0, arr_sz; - arr_sz = ARRAY_SIZE(isa_ext_arr) - 1; + arr_sz = riscv_isa_extensions_count - 1; /* No extension support available */ if (arr_sz <= 0) return; - for (i = 0; i <= arr_sz; i++) { - edata = &isa_ext_arr[i]; - if (!__riscv_isa_extension_available(NULL, edata->isa_ext_id)) + for (i = 0; i < arr_sz; i++) { + if (!__riscv_isa_extension_available(NULL, riscv_isa_extensions[i].key)) continue; - seq_printf(f, "_%s", edata->uprop); + if (riscv_isa_extensions[i].multi_letter) + seq_printf(f, "_"); + + seq_printf(f, "%s", riscv_isa_extensions[i].name); } } -/* - * These are the only valid base (single letter) ISA extensions as per the spec. - * It also specifies the canonical order in which it appears in the spec. - * Some of the extension may just be a place holder for now (B, K, P, J). - * This should be updated once corresponding extensions are ratified. - */ -static const char base_riscv_exts[13] = "imafdqcbkjpvh"; - -static void print_isa(struct seq_file *f, const char *isa) +static void print_isa(struct seq_file *f) { - int i; + if (IS_ENABLED(CONFIG_64BIT)) + seq_puts(f, "isa\t\t: rv64"); + else + seq_puts(f, "isa\t\t: rv32"); - seq_puts(f, "isa\t\t: "); - /* Print the rv[64/32] part */ - seq_write(f, isa, 4); - for (i = 0; i < sizeof(base_riscv_exts); i++) { - if (__riscv_isa_extension_available(NULL, base_riscv_exts[i] - 'a')) - /* Print only enabled the base ISA extensions */ - seq_write(f, &base_riscv_exts[i], 1); - } print_isa_ext(f); seq_puts(f, "\n"); } @@ -312,8 +256,7 @@ static int c_show(struct seq_file *m, void *v) seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); + print_isa(m); print_mmu(m); if (!of_property_read_string(node, "compatible", &compat) && strcmp(compat, "riscv")) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 1ead76adf60f..d415a86a11e7 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -93,6 +93,45 @@ static bool riscv_isa_extension_check(int id) return true; } +/* + * The canonical order of ISA extension names in the ISA string is defined in + * chapter 27 of the unprivileged specification. + * + * Ordinarily, for in-kernel data structures, this order is unimportant but + * isa_ext_arr defines the order of the ISA string in /proc/cpuinfo. + * + * The specification uses vague wording, such as should, when it comes to + * ordering, so for our purposes the following rules apply: + * + * 1. All multi-letter extensions must be separated from other extensions by an + * underscore. + * + * 2. Additional standard extensions (starting with 'Z') must be sorted after + * single-letter extensions and before any higher-privileged extensions. + + * 3. The first letter following the 'Z' conventionally indicates the most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they must be ordered first by + * category, then alphabetically within a category. + * + * 3. Standard supervisor-level extensions (starting with 'S') must be listed + * after standard unprivileged extensions. If multiple supervisor-level + * extensions are listed, they must be ordered alphabetically. + * + * 4. Standard machine-level extensions (starting with 'Zxm') must be listed + * after any lower-privileged, standard extensions. If multiple + * machine-level extensions are listed, they must be ordered + * alphabetically. + * + * 5. Non-standard extensions (starting with 'X') must be listed after all + * standard extensions. If multiple non-standard extensions are listed, they + * must be ordered alphabetically. + * + * An example string following the order is: + * rv64imadc_zifoo_zigoo_zafoo_sbar_scar_zxmbaz_xqux_xrux + * + * New entries to this struct should follow the ordering rules described above. + */ const struct riscv_isa_extension riscv_isa_extensions[] = { RISCV_ISA_EXT_CFG(i, RISCV_ISA_EXT_i, "v1.0.0", false), RISCV_ISA_EXT_CFG(m, RISCV_ISA_EXT_m, "v1.0.0", false), @@ -121,6 +160,8 @@ const struct riscv_isa_extension riscv_isa_extensions[] = { RISCV_ISA_EXT_CFG("", RISCV_ISA_EXT_MAX, "", false), }; +const size_t riscv_isa_extensions_count = ARRAY_SIZE(riscv_isa_extensions); + static void __init riscv_fill_hwcap_isa_string(void) { struct device_node *node; From patchwork Mon May 8 18:16:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13234803 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8C193C77B75 for ; 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Mon, 08 May 2023 18:17:17 +0000 Received: from dfw.source.kernel.org ([2604:1380:4641:c500::1]) by bombadil.infradead.org with esmtps (Exim 4.96 #2 (Red Hat Linux)) id 1pw5Q8-0016e9-22 for linux-riscv@lists.infradead.org; Mon, 08 May 2023 18:17:14 +0000 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3733361EB2; Mon, 8 May 2023 18:17:12 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9D76CC433EF; Mon, 8 May 2023 18:17:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1683569831; bh=VPla/phlxrLYHeG47Y11HycCuElwiwJdnJJp2FxR8K0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nGQZz+lFtUgvsJNWM6Ro5wavaNIeeMU8SpIkcsNn8wBJMtajmC/SVvaTKx5gcZYSM MjIWhTdy9v46X10zxrgN7QlTCY6uhVRnC2iThRiIGhlNx0Nv+RFiFVFoaVWgYSYHZF Z5Q3ReMFSC5Di+U4HKI7uMNHCukrBYaAPztj51syjFQgePq35Mw77i0sXzwaaJJy87 4aWx+Zi7UhejL5eFkouQ8ASVIhl8WVJw/LQyb8zIKPQ9Ia5hdPFVF5t4OqJ1s/m+IB wKR4GriB71PRcwfNnbfVIPlR18QLlUf8ALOCLtJk667MqFwjzA+QrJp/iH4rMQL594 O7iX7bR4KTA9Q== From: Conor Dooley To: linux-riscv@lists.infradead.org Subject: [RFC 5/6] RISC-V: drop a needless check in print_isa_ext() Date: Mon, 8 May 2023 19:16:25 +0100 Message-Id: <20230508-strenuous-mustiness-412fdf2402b0@spud> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230508-hypnotic-phobia-99598439d828@spud> References: <20230508-hypnotic-phobia-99598439d828@spud> MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index c29643dca0f7..bc32207b7d86 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -176,15 +176,8 @@ arch_initcall(riscv_cpuinfo_init); #ifdef CONFIG_PROC_FS static void print_isa_ext(struct seq_file *f) { - int i = 0, arr_sz; - arr_sz = riscv_isa_extensions_count - 1; - - /* No extension support available */ - if (arr_sz <= 0) - return; - - for (i = 0; i < arr_sz; i++) { + for (int i = 0; i < riscv_isa_extensions_count - 1; i++) { if (!__riscv_isa_extension_available(NULL, riscv_isa_extensions[i].key)) continue; if (riscv_isa_extensions[i].multi_letter) From patchwork Mon May 8 18:16:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 13234804 X-Patchwork-Delegate: mail@conchuod.ie Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id B431AC7EE22 for ; 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a=openpgp-sha256; l=2933; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=sxz5UhIOaJj8Re9+hSvtSwbaV+pJMl6xzcAp79D9KJ0=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDCmRNmWBZjpFz00vJS05+L9L+f2fzB2CqnuOxv4vyjCY1 aDQqX6io5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABM5JcXIsDaoQu7ndSPHiFVZ b6r+XVDUX7+QO+WEwN/4JVafG774vWT4n/X1LGvk2k8PHu2w26F8MObA3czOT/KLMu2ezbrw/db +2UwA X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20230508_111715_569005_A218F7BA X-CRM114-Status: GOOD ( 10.16 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Conor Dooley , Heiko Stuebner , conor@kernel.org, Yangyu Chen , Conor Dooley , Rob Herring , Palmer Dabbelt , Krzysztof Kozlowski , Paul Walmsley , Andrew Jones Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org From: Conor Dooley Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 42 ++++++++++++++++++++++--- 1 file changed, 37 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..53efb5e03c64 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -21,7 +21,11 @@ cpu0: cpu@0 { i-cache-sets = <128>; i-cache-size = <16384>; reg = <0>; - riscv,isa = "rv64imac"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; status = "disabled"; @@ -47,7 +51,14 @@ cpu1: cpu@1 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <1>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -75,7 +86,14 @@ cpu2: cpu@2 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <2>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -103,7 +121,14 @@ cpu3: cpu@3 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <3>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>; @@ -131,7 +156,14 @@ cpu4: cpu@4 { i-tlb-size = <32>; mmu-type = "riscv,sv39"; reg = <4>; - riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extension-i = "v1.0.0"; + riscv,isa-extension-m = "v1.0.0"; + riscv,isa-extension-a = "v1.0.0"; + riscv,isa-extension-f = "v1.0.0"; + riscv,isa-extension-d = "v1.0.0"; + riscv,isa-extension-c = "v1.0.0"; + riscv,isa-extension-zicsr = "v1.0.0"; clocks = <&clkcfg CLK_CPU>; tlb-split; next-level-cache = <&cctrllr>;