From patchwork Mon May 8 22:01:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13235164 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0725BC7EE2C for ; Mon, 8 May 2023 22:02:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234390AbjEHWCA (ORCPT ); Mon, 8 May 2023 18:02:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40216 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234528AbjEHWBm (ORCPT ); Mon, 8 May 2023 18:01:42 -0400 Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7BE877D87; Mon, 8 May 2023 15:01:31 -0700 (PDT) Received: by mail-qt1-x829.google.com with SMTP id d75a77b69052e-3f394fe5465so4127861cf.3; Mon, 08 May 2023 15:01:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683583290; x=1686175290; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=WMcPX7+XH5SaqSZhnB/TBndNwmDuSe3GPgEuJujl4r8=; b=VdVNDZe3sBM86o4kgh7s/hG71/9NvX4vBEcRwSjXafvuy8kTj5uCwAKBNW0rPbZXhj 3TJdQblny3mIevgZDOEOl6eiAwM2FfWWbQzyrCh2SVp9VPEJvniSty+muMR9doizTMni TDHr3M6l6KJtIdzOILw8beUbiReg50M4GaOtK342qRYhQSOEpmAYp2gjw1v5krXj3oEz oCr0L4OzueQ7MKOPv+H/crWucDhawcM1r+o5BguJ3VNCBYk+RaMi5rZTIIwk6JrGX8Jq YHsVCWABEWWpRE5FGig22JcNR3efG4V4x2UDsHsJaPrH4ycpXD/bXc1qMRS95PfdD55J 9YqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683583290; x=1686175290; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=WMcPX7+XH5SaqSZhnB/TBndNwmDuSe3GPgEuJujl4r8=; b=JL9pvdxSFMtGyRryj40LRrYyJBI5ZAyBZRkXtJW2YtKBZJFtxBJWId0+W7razc3h5P BlmhDUUuahG9HxlofFaZwopplJx336E4pUlqLMjlt3vNV6StB2c0TOvvjGU3KVczqwtD fZhiEbXJQXikf/AX/G7LfUNoUP2Vt5buUwiHSRLXEjrSYcOglXIq1QHO4HlVfkcdUBQf k6E3nJPPavjqCl5rba1eMO4NCnCMaPIAkqgiGBx7cfkbLPnUPjszRRJRiu78Sdkq1VUH 6fFOhSMhZo1dADzjCpoh53L5j9Zk54VpOtyklTNXAdd7XjFCmX31WUrRGj2cVl7o5/lq Axaw== X-Gm-Message-State: AC+VfDx9fVcCA24LFMWVUDoxBsGr/wwrCXvBoIemkcRSXwTOr4pYqvPv oxSOfrHH0mzJ8zs7fGMmyEcy3FHHFHc= X-Google-Smtp-Source: ACHHUZ74X+AdPVZ7ThRjyNYy/SKDI899Z3VKFuulzxP9kSFMSkbPUpl6w4tWh9H/0/Kn2xVCRxUdaQ== X-Received: by 2002:a05:622a:308:b0:3f3:633b:2888 with SMTP id q8-20020a05622a030800b003f3633b2888mr15816018qtw.54.1683583290242; Mon, 08 May 2023 15:01:30 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id e11-20020ac8010b000000b003d7e923736asm3315176qtg.6.2023.05.08.15.01.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 15:01:29 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 1/5] dt-bindings: PCI: brcmstb: Add brcm,enable-l1ss property Date: Mon, 8 May 2023 18:01:21 -0400 Message-Id: <20230508220126.16241-2-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230508220126.16241-1-jim2101024@gmail.com> References: <20230508220126.16241-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org This commit adds the boolean "brcm,enable-l1ss" property: The Broadcom STB/CM PCIe HW -- a core that is also used by RPi SOCs -- requires the driver probe() to deliberately place the HW one of three CLKREQ# modes: (a) CLKREQ# driven by the RC unconditionally (b) CLKREQ# driven by the EP for ASPM L0s, L1 (c) Bidirectional CLKREQ#, as used for L1 Substates (L1SS). The HW+driver can tell the difference between downstream devices that need (a) and (b), but does not know when to configure (c). All devices should work fine when the driver chooses (a) or (b), but (c) may be desired to realize the extra power savings that L1SS offers. So we introduce the boolean "brcm,enable-l1ss" property to inform the driver that (c) is desired. Setting this property only makes sense when the downstream device is L1SS-capable and the OS is configured to activate this mode (e.g. policy==powersupersave). This property is already present in the Raspian version of Linux, but the upstream driver implementation that follows adds more details and discerns between (a) and (b). Signed-off-by: Jim Quinlan Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml index 7e15aae7d69e..8b61c2179608 100644 --- a/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,stb-pcie.yaml @@ -64,6 +64,15 @@ properties: aspm-no-l0s: true + brcm,enable-l1ss: + description: Indicates that PCIe L1SS power savings + are desired, the downstream device is L1SS-capable, and the + OS has been configured to enable this mode. For boards + using a mini-card connector, this mode may not meet the + TCRLon maximum time of 400ns, as specified in 3.2.5.2.2 + of the PCI Express Mini CEM 2.0 specification. + type: boolean + brcm,scb-sizes: description: u64 giving the 64bit PCIe memory viewport size of a memory controller. There may be up to From patchwork Mon May 8 22:01:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13235165 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8891CC7EE22 for ; Mon, 8 May 2023 22:02:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233787AbjEHWCC (ORCPT ); Mon, 8 May 2023 18:02:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234538AbjEHWBm (ORCPT ); Mon, 8 May 2023 18:01:42 -0400 Received: from mail-qt1-x834.google.com (mail-qt1-x834.google.com [IPv6:2607:f8b0:4864:20::834]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9C94B7EF5; Mon, 8 May 2023 15:01:32 -0700 (PDT) Received: by mail-qt1-x834.google.com with SMTP id d75a77b69052e-3f390fb063cso6536471cf.2; Mon, 08 May 2023 15:01:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683583291; x=1686175291; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=JVDegyPLBHaeO/WL6svk+oLQ/anSvMh7xAxroWOQujU=; b=kTuy8jqFysJuvLb7gnRL5Tqn246Ww5uOuoqtvhrdCLtHoEmtnlt8PK/43Z7pITTDOV 0vupBIf44m/pTISNw1bmMG0cV2wD9WebIfnAfOLxoBK/BrbKHvA4nleqlNy2AnzZLPRU 993+98UWaf6T4pBTh5nIuWxlgU01PMqT2ux0X8hxiebpWklXCMQdWdA0ToljzxxJFDPy 4nbFbJFsoysAwpZzlwTK5DQ7Y21wNrORYodO3bQKcmWXC2/GHMsEOtTYNrXKEUZmZwPr 0tXJqcif20Cpp8l4FfYT8D3gRr5o9j8O7tbGwLtDRkYE5UMEBlLRt3Jl0l30iGb2FrJ6 NyEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683583291; x=1686175291; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=JVDegyPLBHaeO/WL6svk+oLQ/anSvMh7xAxroWOQujU=; b=GWK2wYPWbriZR0kMJf3blDzjqIugjBDuO7nw1tzuHeZBfEkLot2niU4HltRnJ696Mc bbCQmahgUI48jkgKPI/jQbMV8eqUv7BUjBIsPZnNYJ6dz98FlQ7McgW+wp0IAFo7pD6G YZPr6ibSZyi8HZpSCk4owkgoxPf6nzaGU6WZTF/QqfgWBfPxmMfK1ZXrvVntTZN5vxer n7gzPnqhIvOOsnGThhPD2Aye5NZFiTaLR/4yjlNFc8EHPd0QmlqHaO1z8fazpsgrqsGm 8y+sIGkT233hZl3iOkzgU0HyHwSxNTOxponcwuX5KXoT0GOw4aDJg/KTk5emz8yMcDTQ w1vA== X-Gm-Message-State: AC+VfDx11petd08/sKIYtTGLCVXwmfKTYHUcVTz/PKlbGsGIM3K2sf99 3ReFV8WVPKt3zA+ls+L0zkv4C7RWGfw= X-Google-Smtp-Source: ACHHUZ5tYolHrufdF+0JL6lhhjvNKX9zGy6sdY2SImZ4jU4plm9dpx5gneEl3qUFV/aey1NA6jqiSw== X-Received: by 2002:a05:622a:11c3:b0:3ee:b9bd:8da2 with SMTP id n3-20020a05622a11c300b003eeb9bd8da2mr18681205qtk.19.1683583291398; Mon, 08 May 2023 15:01:31 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id e11-20020ac8010b000000b003d7e923736asm3315176qtg.6.2023.05.08.15.01.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 15:01:31 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 2/5] PCI: brcmstb: Configure HW CLKREQ# mode appropriate for downstream device Date: Mon, 8 May 2023 18:01:22 -0400 Message-Id: <20230508220126.16241-3-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230508220126.16241-1-jim2101024@gmail.com> References: <20230508220126.16241-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The Broadcom STB/CM PCIe HW core, which is also used in RPi SOCs, must be deliberately set by the RC probe() into one of three mutually exclusive modes: (a) No CLKREQ# expected or required, refclk is always available. (b) CLKREQ# is expected to be driven by downstream device when needed. (c) Bidirectional CLKREQ# for L1SS capable devices. Previously, only (b) was supported by the driver, as almost all STB/CM boards operate in this mode. But now there is interest in activating L1SS power savings from STB/CM customers, and also interest in accommodating mode (a) for designs such as the RPi CM4 with IO board. The HW+driver is able to tell us when mode (a) or (b) is needed. All devices should be functional using the RC-driver selected (a) or (b) mode. For those with L1SS-capable devices that desire the power savings that come with mode (c) we rely on the DT prop "brcm,enable-l1ss". It would be nice to do this automatically but there is no easy way to determine this at the time the PCI RC driver executes its probe(). Using this mode only makes sense when the downstream device is L1SS-capable and the OS has been configured to activate L1SS (e.g. policy==powersupersave). The "brcm,enable-l1ss" property has already been in use by Raspian Linux, but this implementation adds more details and discerns between (a) and (b) automatically. Link: https://bugzilla.kernel.org/show_bug.cgi?id=217276 Tested-by: Florian Fainelli Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 69 +++++++++++++++++++++++---- 1 file changed, 59 insertions(+), 10 deletions(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index edf283e2b5dd..d30636a725d7 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -48,10 +48,17 @@ #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY 0x04dc #define PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK 0xc00 +#define PCIE_RC_CFG_PRIV1_ROOT_CAP 0x4f8 +#define PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK 0xf8 + #define PCIE_RC_DL_MDIO_ADDR 0x1100 #define PCIE_RC_DL_MDIO_WR_DATA 0x1104 #define PCIE_RC_DL_MDIO_RD_DATA 0x1108 +#define PCIE_0_RC_PL_PHY_DBG_CLKREQ2_0 0x1e30 +#define CLKREQ2_0_CLKREQ_IN_CNT_MASK 0x3f000000 +#define CLKREQ2_0_CLKREQ_IN_MASK 0x40000000 + #define PCIE_MISC_MISC_CTRL 0x4008 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_64B_MODE_MASK 0x80 #define PCIE_MISC_MISC_CTRL_PCIE_RCB_MPS_MODE_MASK 0x400 @@ -121,9 +128,12 @@ #define PCIE_MISC_HARD_PCIE_HARD_DEBUG 0x4204 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK 0x2 +#define PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK 0x200000 #define PCIE_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x08000000 #define PCIE_BMIPS_MISC_HARD_PCIE_HARD_DEBUG_SERDES_IDDQ_MASK 0x00800000 - +#define PCIE_CLKREQ_MASK \ + (PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK | \ + PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK) #define PCIE_INTR2_CPU_BASE 0x4300 #define PCIE_MSI_INTR2_BASE 0x4500 @@ -1024,13 +1034,58 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return 0; } +static void brcm_config_clkreq(struct brcm_pcie *pcie) +{ + bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss"); + void __iomem *base = pcie->base; + u32 clkreq_set, tmp = readl(base + PCIE_0_RC_PL_PHY_DBG_CLKREQ2_0); + bool clkreq_in_seen; + + /* + * We have "seen" CLKREQ# if it is asserted or has been in the past. + * Note that the CLKREQ_IN_MASK is 1 if CLKREQ# is asserted. + */ + clkreq_in_seen = !!(tmp & CLKREQ2_0_CLKREQ_IN_MASK) || + !!FIELD_GET(CLKREQ2_0_CLKREQ_IN_CNT_MASK, tmp); + + /* Start with safest setting where we provide refclk regardless */ + clkreq_set = readl(pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG) & + ~PCIE_CLKREQ_MASK; + + if (l1ss && IS_ENABLED(CONFIG_PCIEASPM)) { + /* + * Note: For boards using a mini-card connector, this mode + * (L1SS CLKREQ# mode) may not meet the TCRLon maximum time + * of 400ns, as specified in 3.2.5.2.2 of the PCI Express + * Mini CEM 2.0 specification. + */ + clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK; + dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings"); + } else { + if (clkreq_in_seen && IS_ENABLED(CONFIG_PCIEASPM)) { + clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; + dev_info(pcie->dev, "uni-dir CLKREQ# for L0s, L1 ASPM\n"); + } else { + dev_info(pcie->dev, "CLKREQ# ignored; no ASPM\n"); + /* Might as well unadvertise ASPM */ + tmp = readl(base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY) & + ~PCIE_RC_CFG_PRIV1_LINK_CAPABILITY_ASPM_SUPPORT_MASK; + writel(tmp, base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); + } + /* Setting the field to 2 unadvertises L1SS support */ + tmp = readl(base + PCIE_RC_CFG_PRIV1_ROOT_CAP); + u32p_replace_bits(&tmp, 2, PCIE_RC_CFG_PRIV1_ROOT_CAP_L1SS_MODE_MASK); + writel(tmp, base + PCIE_RC_CFG_PRIV1_ROOT_CAP); + } + writel(clkreq_set, pcie->base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); +} + static int brcm_pcie_start_link(struct brcm_pcie *pcie) { struct device *dev = pcie->dev; void __iomem *base = pcie->base; u16 nlw, cls, lnksta; bool ssc_good = false; - u32 tmp; int ret, i; /* Unassert the fundamental reset */ @@ -1055,6 +1110,8 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) return -ENODEV; } + brcm_config_clkreq(pcie); + if (pcie->gen) brcm_pcie_set_gen(pcie, pcie->gen); @@ -1073,14 +1130,6 @@ static int brcm_pcie_start_link(struct brcm_pcie *pcie) pci_speed_string(pcie_link_speed[cls]), nlw, ssc_good ? "(SSC)" : "(!SSC)"); - /* - * Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1 - * is enabled => setting the CLKREQ_DEBUG_ENABLE field to 1. - */ - tmp = readl(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); - tmp |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_CLKREQ_DEBUG_ENABLE_MASK; - writel(tmp, base + PCIE_MISC_HARD_PCIE_HARD_DEBUG); - return 0; } From patchwork Mon May 8 22:01:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13235166 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 88437C7EE25 for ; Mon, 8 May 2023 22:02:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233235AbjEHWCD (ORCPT ); Mon, 8 May 2023 18:02:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40808 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234534AbjEHWBm (ORCPT ); Mon, 8 May 2023 18:01:42 -0400 Received: from mail-qk1-x72b.google.com (mail-qk1-x72b.google.com [IPv6:2607:f8b0:4864:20::72b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9731A86B4; Mon, 8 May 2023 15:01:33 -0700 (PDT) Received: by mail-qk1-x72b.google.com with SMTP id af79cd13be357-7576ecfa4e7so240632285a.3; Mon, 08 May 2023 15:01:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683583292; x=1686175292; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=kcpsE+wXJIHOwOwJebkaqKb6ksrC76geutECDHqWm0M=; b=nQZCsAkpKbZH+NBSmthHZ4XSxFw4l7H/EfLchf9T90RXuolhnNuzAV2fQ8rScXRq91 Ip/j5Zd0ka3ezfaM739EkextCL6k5czlmge55HVclKTdiCO3S3TQzVp+j8zeq/9bsxw3 d5qafuY9OaskMjGQiz3XodwF4Q/XklCV4dWKrUAvt13CefnxU3NQ8kbrEKziMdN1xbHm 7FTDQ6ppzxM5v2DcIyOsICQaHnF1fbqDYyVVb9lSckFAESuJURCX+AjooJc0VQUu/ncq f7o5F9rrYVmLmgQMUFIg+bUr1rP26spKPqmc1lb+QMcmBcz+H4ix7paA7xyDaeKcbJAP 5orw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683583292; x=1686175292; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=kcpsE+wXJIHOwOwJebkaqKb6ksrC76geutECDHqWm0M=; b=CD7XxRIVtWlkQK3vBuBBMLxGPYsuZMC31Xo4XyJ5ubx99Jrm4n3x7+orV3LEmEM+ia L0k7aPCuVP19oII9lBZrGmv8it2cdGKXldYSwJoSQVFolBhYKPkxNsNTeGYbCmGA2aOV VzOvNRcGbshiBFyN0wxTM6+oTQbyjvisEZ+g+VnLj332LAskAKH4vFl5OEIdyYRAZyMq 6e+wIwKEyMeUJ6m2ETk2RrUaQw5W2ed85J4kAJwG8NMScEgkQD0iUfriIxNmbZvzVTb7 Bf4O7Xg9DXqpMOWveeFcWuSD+9FF9fVkvfIV0qvQCKfj/VPdbVHh7blk/2PoLpbsb/qR JhUg== X-Gm-Message-State: AC+VfDwiBBYnir4NrbTOAq25Sw6FzfbOC22/DXXQO42b2QweWR/0kq0v 3o9Y3VfMrPF9RpbTteC0ZG4AI5QS1Mg= X-Google-Smtp-Source: ACHHUZ4Wz75x9v6n2Zda1aQQbZCKWO4yU29ClORYfdWR/7zwukW4VnTCowYWV5YO9m0VFBayAYREug== X-Received: by 2002:a05:622a:4cf:b0:3ef:344b:2099 with SMTP id q15-20020a05622a04cf00b003ef344b2099mr17431319qtx.4.1683583292550; Mon, 08 May 2023 15:01:32 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id e11-20020ac8010b000000b003d7e923736asm3315176qtg.6.2023.05.08.15.01.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 15:01:32 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 3/5] PCI: brcmstb: Set higher value for internal bus timeout Date: Mon, 8 May 2023 18:01:23 -0400 Message-Id: <20230508220126.16241-4-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230508220126.16241-1-jim2101024@gmail.com> References: <20230508220126.16241-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org During long periods of the PCIe RC HW being in an L1SS sleep state, there may be a timeout on an internal bus access, even though there may not be any PCIe access involved. Such a timeout will cause a subsequent CPU abort. So, when "brcm,enable-l1ss" is observed, we increase the timeout value to four seconds instead of using its HW default. Tested-by: Florian Fainelli Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index d30636a725d7..fe0415a98c63 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -1034,6 +1034,21 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) return 0; } +/* + * This extends the timeout period for an access to an internal bus. This + * access timeout may occur during L1SS sleep periods even without the + * presence of a PCIe access. + */ +static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) +{ + /* TIMEOUT register is two registers before RGR1_SW_INIT_1 */ + const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; + u32 timeout_us = 4000000; /* 4 seconds, our setting for L1SS */ + + /* Each unit in timeout register is 1/216,000,000 seconds */ + writel(216 * timeout_us, pcie->base + REG_OFFSET); +} + static void brcm_config_clkreq(struct brcm_pcie *pcie) { bool l1ss = of_property_read_bool(pcie->np, "brcm,enable-l1ss"); @@ -1059,6 +1074,7 @@ static void brcm_config_clkreq(struct brcm_pcie *pcie) * of 400ns, as specified in 3.2.5.2.2 of the PCI Express * Mini CEM 2.0 specification. */ + brcm_extend_rbus_timeout(pcie); clkreq_set |= PCIE_MISC_HARD_PCIE_HARD_DEBUG_L1SS_ENABLE_MASK; dev_info(pcie->dev, "bi-dir CLKREQ# for L1SS power savings"); } else { From patchwork Mon May 8 22:01:24 2023 Content-Type: text/plain; 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Mon, 08 May 2023 15:01:33 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id e11-20020ac8010b000000b003d7e923736asm3315176qtg.6.2023.05.08.15.01.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 15:01:33 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 4/5] PCI: brcmstb: Don't assume 2711 bootloader leaves PERST# asserted Date: Mon, 8 May 2023 18:01:24 -0400 Message-Id: <20230508220126.16241-5-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230508220126.16241-1-jim2101024@gmail.com> References: <20230508220126.16241-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The current PCIe driver assumes PERST# is asserted when probe() is invoked. The reasons are as follows: (1) One Broadcom SOC (7278) causes a panic if the PERST# register is written during this time window. (2) If PERST# is deasserted at Linux probe() time, experience and QA suspend/resume tests have shown that some endpoint devices fail if the PERST# is pulsed (deasserted => asserted => deasserted) quickly in this fashion, even though the timing is in accordance with their datasheets. (3) Keeping things in reset tends to save power, if for some reason the PCIe driver is not yet present. Broadcom STB and CM SOCs bootloaders always have PERST# asserted at probe(). This is not necessarily the case for the 2711/RPi bootloader, so, for 2711/RPi SOCs, do what Raspian OS does and assert PERST#. [1] https://lore.kernel.org/linux-pci/20230411165919.23955-1-jim2101024@gmail.com/T/#m39ebab8bc2827b2304aeeff470a6c6a58f46f987 Signed-off-by: Jim Quinlan --- drivers/pci/controller/pcie-brcmstb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index fe0415a98c63..7b698a9a851e 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -884,6 +884,11 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie) /* Reset the bridge */ pcie->bridge_sw_init_set(pcie, 1); + + /* Ensure that PERST# is asserted; some bootloaders may deassert it. */ + if (pcie->type == BCM2711) + pcie->perst_set(pcie, 1); + usleep_range(100, 200); /* Take the bridge out of reset */ From patchwork Mon May 8 22:01:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jim Quinlan X-Patchwork-Id: 13235167 X-Patchwork-Delegate: kw@linux.com Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D080C7EE26 for ; Mon, 8 May 2023 22:02:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234438AbjEHWCF (ORCPT ); Mon, 8 May 2023 18:02:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234303AbjEHWBo (ORCPT ); Mon, 8 May 2023 18:01:44 -0400 Received: from mail-qk1-x733.google.com (mail-qk1-x733.google.com [IPv6:2607:f8b0:4864:20::733]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AB9A98A7A; Mon, 8 May 2023 15:01:35 -0700 (PDT) Received: by mail-qk1-x733.google.com with SMTP id af79cd13be357-75785057afeso128971485a.3; Mon, 08 May 2023 15:01:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683583294; x=1686175294; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date:message-id:reply-to; bh=pCt3fs/yt+9j4nJyZEyIyBbz3ydO6tgld+CtAn09VxI=; b=O66dAvPPs2CQpnu+jPSBwMhFwMizGeRGvwdwnC/tapuHPzrY6ubNibVBXz8X3zLEPM vzeOUPnjE1agVfmXqrMbUBB6+wW3pZLz0zpVBJybj/JEyGRkdws//wa77Qj6oyYk9kvd mWh+LZMZ5bSQgAKc7lBQG+LKVNYleJRiNKTEn9tSA0sIxIXgZziFcMoVG3Pgg8CYkPUr WmxgAbcVKclCjP4N7MBsnawEzH6A/dW4gaKFOPKwCcadbLQWyY+liMJxgRBajGRQOmnr jsbVlCshTvjd6fYZK34vYLbdCJETIVVcswi0HcRi2UzVMAWbdX+AExVD9U1EBkNVSIf1 OoaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683583294; x=1686175294; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=pCt3fs/yt+9j4nJyZEyIyBbz3ydO6tgld+CtAn09VxI=; b=gyq8nIH4Wcpi//wWjHNHGO979eSv2xh0KdAddInDRlQioo5swRUsWY1TBmWQ8jF6VN SdTplSXb5/IoG916jhW4Z/biX6GmrZyTqfb8+RqfGSmHldeOzR4D7H+nB1br+v1DORKN NJoZeAnT82TY3MEBcIA5RkDJThSH0xDaWDeMlmM4/dOieq3dK9xrR8Ou0W+XH/BkZEXj 2rCp/wLQXouitESTdoLnxHoA8rysdfDZCJAWoPu7uVjvNJzEX/cPK1VpeoKsO42ym3kN tWaQkCEkgNH1VG6HfNswKfJguAP6IZYdXg/uj+kK9STuVMgEtQ2bMn3YHCewaMzG1/Yn BWvA== X-Gm-Message-State: AC+VfDzh2ZmLeOfKz/of5HHTHPtebwCwvm/vle2hbGZ9DFPsfal0QMHN O67S92LPIcp+s7d7ze8Ndi38yye+4vY= X-Google-Smtp-Source: ACHHUZ7xSK+QevIq0p3hBj+58HTRkq4ohElRL00PBCdMCP3uGE82Ms/affum43cqE0BMUDlwa6q98g== X-Received: by 2002:ac8:5cd2:0:b0:3ef:4c4b:7e1e with SMTP id s18-20020ac85cd2000000b003ef4c4b7e1emr17619302qta.29.1683583294692; Mon, 08 May 2023 15:01:34 -0700 (PDT) Received: from stbsrv-and-01.and.broadcom.net ([192.19.144.250]) by smtp.gmail.com with ESMTPSA id e11-20020ac8010b000000b003d7e923736asm3315176qtg.6.2023.05.08.15.01.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 15:01:34 -0700 (PDT) From: Jim Quinlan To: linux-pci@vger.kernel.org, Nicolas Saenz Julienne , Bjorn Helgaas , Lorenzo Pieralisi , Cyril Brulebois , Phil Elwell , bcm-kernel-feedback-list@broadcom.com, jim2101024@gmail.com, james.quinlan@broadcom.com Cc: Florian Fainelli , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v5 5/5] PCI: brcmstb: Remove stale comment Date: Mon, 8 May 2023 18:01:25 -0400 Message-Id: <20230508220126.16241-6-jim2101024@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230508220126.16241-1-jim2101024@gmail.com> References: <20230508220126.16241-1-jim2101024@gmail.com> Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org A comment says that Multi-MSI is not supported by the driver. A past commit [1] added this feature, so the comment is incorrect and is removed. [1] commit 198acab1772f22f2 ("PCI: brcmstb: Enable Multi-MSI") Signed-off-by: Jim Quinlan Acked-by: Florian Fainelli --- drivers/pci/controller/pcie-brcmstb.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 7b698a9a851e..acd478edbe2f 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -449,7 +449,6 @@ static struct irq_chip brcm_msi_irq_chip = { }; static struct msi_domain_info brcm_msi_domain_info = { - /* Multi MSI is supported by the controller, but not by this driver */ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | MSI_FLAG_MULTI_PCI_MSI), .chip = &brcm_msi_irq_chip,