From patchwork Wed May 10 01:58:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?V2VuYmluIE1laSAo5qKF5paH5b2sKQ==?= X-Patchwork-Id: 13236229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D747C77B75 for ; Wed, 10 May 2023 01:59:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230188AbjEJB7D (ORCPT ); Tue, 9 May 2023 21:59:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229527AbjEJB7D (ORCPT ); Tue, 9 May 2023 21:59:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E060EE74; Tue, 9 May 2023 18:59:01 -0700 (PDT) X-UUID: 384caefeeed611ed9cb5633481061a41-20230510 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=goFtPwMVn64ABIQNA1G7S20XXap5d/VUqT3HlPpXTwI=; b=iEAABm8V9UNxhd5TZLe039wJheG78Rf9sThM/2Wuhg1dZOaYc6whINhpA1wEOB4I7t5GicvsdpGPr7TQB9Hz3FNCIsvfb8IwMcovJoT8ipCwVvZ8aSNrzAtuqoyVc9TSkahPa/XNtPmxA3eu4m2WUkWrtY5wVwCafdW9pL9l9Fw=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.24,REQID:3655507c-7708-469f-b67c-fb2c98c3a849,IP:0,U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:178d4d4,CLOUDID:c8c753c0-e32c-4c97-918d-fbb3fc224d4e,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-UUID: 384caefeeed611ed9cb5633481061a41-20230510 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 610202397; Wed, 10 May 2023 09:58:55 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Wed, 10 May 2023 09:58:54 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Wed, 10 May 2023 09:58:53 +0800 From: Wenbin Mei To: Ulf Hansson CC: Chaotian Jing , Matthias Brugger , AngeloGioacchino Del Regno , , , , , Wenbin Mei Subject: [PATCH v2] mmc: mtk-sd: reduce CIT for better performance Date: Wed, 10 May 2023 09:58:51 +0800 Message-ID: <20230510015851.11830-1-wenbin.mei@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org CQHCI_SSC1 indicates to CQE the polling period to use when using periodic SEND_QUEUE_STATUS(CMD13) polling. The default value 0x1000 that corresponds to 150us, let's decrease it to 0x40 that corresponds to 3us, which can improve the performance of some eMMC devices. Signed-off-by: Wenbin Mei --- drivers/mmc/host/mtk-sd.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/mmc/host/mtk-sd.c b/drivers/mmc/host/mtk-sd.c index edade0e54a0c..ffeccddcd028 100644 --- a/drivers/mmc/host/mtk-sd.c +++ b/drivers/mmc/host/mtk-sd.c @@ -2453,6 +2453,7 @@ static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, static void msdc_cqe_enable(struct mmc_host *mmc) { struct msdc_host *host = mmc_priv(mmc); + struct cqhci_host *cq_host = mmc->cqe_private; /* enable cmdq irq */ writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); @@ -2462,6 +2463,9 @@ static void msdc_cqe_enable(struct mmc_host *mmc) msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); /* default read data timeout 1s */ msdc_set_timeout(host, 1000000000ULL, 0); + + /* decrease the send status command idle timer to 3us */ + cqhci_writel(cq_host, 0x40, CQHCI_SSC1); } static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)