From patchwork Wed May 10 08:11:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13236602 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 072DCC7EE22 for ; Wed, 10 May 2023 08:12:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236562AbjEJIL7 (ORCPT ); Wed, 10 May 2023 04:11:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58344 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236543AbjEJILr (ORCPT ); Wed, 10 May 2023 04:11:47 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BF15F109; Wed, 10 May 2023 01:11:45 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id 5b1f17b1804b1-3f417ea5252so30521065e9.0; Wed, 10 May 2023 01:11:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683706304; x=1686298304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8Qz4LzR1x4XZFp0u1LWMlSQ1HYwXXgzIFPiahRVFlGE=; b=jcAW8pADW5wrQPFMxuV7lCESCNGQ7Mktzd+xzZ8iPUVsCAnQ6YuF7TwVsiY+XRUoMN g8FyEXCzZQT5k4K5nVUZfC697YtZ+zh9t6TNwm79/9TceGFIz4m904zkzKVoFoJRhvPB 618soVvnIxK+YS78XxBtjJG9TqoM2Nw7kSCYpbYb/zBzQ57IjcDuIeWpeoVm1AmjzD/U xZPSQUov2WFyN0n26jvgxhYI8PsSN1FZwPSBu1HhODBdiNBpQzGIk1gKU+2F7rtuOZaf P555z9qkvEqF0PDkB5MnMluAyEsgHVzlgBr/3uNlfTdQN4X6W20ybGCLZInpCjWonoQa XT5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683706304; x=1686298304; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8Qz4LzR1x4XZFp0u1LWMlSQ1HYwXXgzIFPiahRVFlGE=; b=GeigxkDAY70AxyH6GLn/DDO/VmqUMrydyw3/F59y+0iP7VDxQVzuIsXesrbu6FQXcO ZvgPc5FLK39tas0wNuJ3gLURc0C/1K/Rmmk7+XBZfMQxBVq08nRxFmOiaaGEniDVpRn4 rpH0ZrMf+0xapAhDC25z+uCoLfsUJMjF3z2pBCsDnnHj66w/J2THDkmVDxD4TjD0cGlQ VLrjDYhNeo7Stsmy95ceiNbCuoM9f0v9nnOxJiYMy+7VZvk4H3tr+O4hpTJmexeMkrtk sj6AVrAbma5GXm2GlY0c7mLc3+4bSDndabTBxDSj+LGium3NXA4AuRADMER+0SV9RSdN e5Tg== X-Gm-Message-State: AC+VfDx20bYFxo++0P0/4NS6lyHE8h6YKhr3z7Zlv010w1YqdI3Fn6i5 U4IV9wvE+IncXvJTY8c7cYM= X-Google-Smtp-Source: ACHHUZ7PLnbhBi7vF8l7BFUZ2Ef1MzGS52Yc/K80mJCYCiMT6ANzAX7IY5wv1U8XJB5LXjpxzcKLiQ== X-Received: by 2002:a05:600c:2317:b0:3f1:76d4:d43f with SMTP id 23-20020a05600c231700b003f176d4d43fmr11272984wmo.8.1683706303974; Wed, 10 May 2023 01:11:43 -0700 (PDT) Received: from localhost.localdomain ([176.221.215.212]) by smtp.gmail.com with ESMTPSA id f16-20020a5d4dd0000000b003062ad45243sm16496375wru.14.2023.05.10.01.11.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 01:11:43 -0700 (PDT) From: Maksim Kiselev To: Andre Przywara Cc: Icenowy Zheng , Maksim Kiselev , Krzysztof Kozlowski , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Cristian Ciocaltea , Maxime Ripard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 1/5] dt-bindings: spi: sun6i: add DT bindings for Allwinner R329/D1/R528/T113s SPI Date: Wed, 10 May 2023 11:11:08 +0300 Message-Id: <20230510081121.3463710-2-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230510081121.3463710-1-bigunclemax@gmail.com> References: <20230510081121.3463710-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Listed above Allwinner SoCs has two SPI controllers. First is the regular SPI controller and the second one has additional functionality for MIPI-DBI Type C. Add compatible strings for these controllers Signed-off-by: Maksim Kiselev Acked-by: Krzysztof Kozlowski Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec --- .../bindings/spi/allwinner,sun6i-a31-spi.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml index de36c6a34a0f..fa5260eca531 100644 --- a/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml +++ b/Documentation/devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml @@ -19,6 +19,7 @@ properties: compatible: oneOf: + - const: allwinner,sun50i-r329-spi - const: allwinner,sun6i-a31-spi - const: allwinner,sun8i-h3-spi - items: @@ -28,6 +29,15 @@ properties: - allwinner,sun50i-h616-spi - allwinner,suniv-f1c100s-spi - const: allwinner,sun8i-h3-spi + - items: + - enum: + - allwinner,sun20i-d1-spi + - allwinner,sun50i-r329-spi-dbi + - const: allwinner,sun50i-r329-spi + - items: + - const: allwinner,sun20i-d1-spi-dbi + - const: allwinner,sun50i-r329-spi-dbi + - const: allwinner,sun50i-r329-spi reg: maxItems: 1 From patchwork Wed May 10 08:11:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13236603 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 58030C7EE22 for ; Wed, 10 May 2023 08:12:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236532AbjEJIMD (ORCPT ); Wed, 10 May 2023 04:12:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58342 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236290AbjEJIMA (ORCPT ); Wed, 10 May 2023 04:12:00 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB4234EFE; Wed, 10 May 2023 01:11:55 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-3062db220a3so4456678f8f.0; Wed, 10 May 2023 01:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683706314; x=1686298314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=77wc1d6atkrSEJWlP3Ir0nLtSYker340vhK9d9PW+mI=; b=ae0I6iddFisGGANa9OOcfirX9cB0n+MSDzgjiH+0SR+KzIbiMhbsU7lKAKHsINsAdL nlio9quJn2D75JzGpvuSrFuC5wonhJgndyBVjQSmqjmxQD5mx7C0iZ2Nl0fMI5ofuiGK BtLscgOl6d764lfDlUAHFezOowTkPUQMQmgoydbi6QPB0EQHOeEcHAgQQjEHgtrayVjF HMXJIZCsQEiKq1GX1YZwmchI5biSj/INjJWi2JS4jYF/yUbqclmtucW1Ib2Hogj7pRXf 5WBWYeHZ8q1SZ/N5RItG3Iy0T4epZmLAPvICMtxCUZ46dJVk7yS9n3e+6LmO1m4mQlCf hBMg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683706314; x=1686298314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=77wc1d6atkrSEJWlP3Ir0nLtSYker340vhK9d9PW+mI=; b=O8kQh/vDkx02cntUxnsuV/B2ZaqPQMQJXqMpOtccUq12CnJawtOPA/FrZ6z6M+x0ma +yyW7MyIlmhMfqpZ28eHyNI7X3qV60+DYVs/ywU5J+dpjmGPehcUbjxOSLTnplNVnlKB qqgIwECv6ggXM5khPpfaRwrCNAGh7U4w48jZ/NcG3Zd3MAXMzGd45MhZabaC0To3I3zu Vaywd64ZYzMyIXBRLCeU7CGoEiMX7TtF1cIjhBVlOJUljBaCWvilZYE2slh4dn8G4nSJ Tu5GGjJEVa1rrE72/vX2285/0OGI+oz0Ma+GKrsXMppRwj2Nvq2GJ0ONRRne6THf2hQR wKpw== X-Gm-Message-State: AC+VfDypqyQM1Em9AgPR05FlZQHi9YyXBSkczy8q6owRox2RoXO9+PSI 3rTEqYyULB1Py/arN28y5FTDCLSbNoWyCfzt X-Google-Smtp-Source: ACHHUZ7LOXg/DkoBru/U76rMVLiEGmaOUTu4YooGzoHGu24IFRnzbR7KaWi2Y+Iz6Mo8QI4e9lZzGQ== X-Received: by 2002:a5d:43c4:0:b0:307:6278:611a with SMTP id v4-20020a5d43c4000000b003076278611amr12190947wrr.21.1683706314126; Wed, 10 May 2023 01:11:54 -0700 (PDT) Received: from localhost.localdomain ([176.221.215.212]) by smtp.gmail.com with ESMTPSA id f16-20020a5d4dd0000000b003062ad45243sm16496375wru.14.2023.05.10.01.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 01:11:53 -0700 (PDT) From: Maksim Kiselev To: Andre Przywara Cc: Icenowy Zheng , Maksim Kiselev , Samuel Holland , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Paul Walmsley , Palmer Dabbelt , Albert Ou , Cristian Ciocaltea , Maxime Ripard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 2/5] spi: sun6i: change OF match data to a struct Date: Wed, 10 May 2023 11:11:09 +0300 Message-Id: <20230510081121.3463710-3-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230510081121.3463710-1-bigunclemax@gmail.com> References: <20230510081121.3463710-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org From: Icenowy Zheng As we're adding more properties to the OF match data, convert it to a struct now. Signed-off-by: Icenowy Zheng Signed-off-by: Maksim Kiselev Reviewed-by: Samuel Holland Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/spi/spi-sun6i.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 7532c85a352c..01a01cd86db5 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -85,6 +85,10 @@ #define SUN6I_TXDATA_REG 0x200 #define SUN6I_RXDATA_REG 0x300 +struct sun6i_spi_cfg { + unsigned long fifo_depth; +}; + struct sun6i_spi { struct spi_master *master; void __iomem *base_addr; @@ -99,7 +103,7 @@ struct sun6i_spi { const u8 *tx_buf; u8 *rx_buf; int len; - unsigned long fifo_depth; + const struct sun6i_spi_cfg *cfg; }; static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) @@ -156,7 +160,7 @@ static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi) u8 byte; /* See how much data we can fit */ - cnt = sspi->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); + cnt = sspi->cfg->fifo_depth - sun6i_spi_get_tx_fifo_count(sspi); len = min((int)cnt, sspi->len); @@ -289,14 +293,14 @@ static int sun6i_spi_transfer_one(struct spi_master *master, * the hardcoded value used in old generation of Allwinner * SPI controller. (See spi-sun4i.c) */ - trig_level = sspi->fifo_depth / 4 * 3; + trig_level = sspi->cfg->fifo_depth / 4 * 3; } else { /* * Setup FIFO DMA request trigger level * We choose 1/2 of the full fifo depth, that value will * be used as DMA burst length. */ - trig_level = sspi->fifo_depth / 2; + trig_level = sspi->cfg->fifo_depth / 2; if (tfr->tx_buf) reg |= SUN6I_FIFO_CTL_TF_DRQ_EN; @@ -410,9 +414,9 @@ static int sun6i_spi_transfer_one(struct spi_master *master, reg = SUN6I_INT_CTL_TC; if (!use_dma) { - if (rx_len > sspi->fifo_depth) + if (rx_len > sspi->cfg->fifo_depth) reg |= SUN6I_INT_CTL_RF_RDY; - if (tx_len > sspi->fifo_depth) + if (tx_len > sspi->cfg->fifo_depth) reg |= SUN6I_INT_CTL_TF_ERQ; } @@ -543,7 +547,7 @@ static bool sun6i_spi_can_dma(struct spi_master *master, * the fifo length we can just fill the fifo and wait for a single * irq, so don't bother setting up dma */ - return xfer->len > sspi->fifo_depth; + return xfer->len > sspi->cfg->fifo_depth; } static int sun6i_spi_probe(struct platform_device *pdev) @@ -582,7 +586,7 @@ static int sun6i_spi_probe(struct platform_device *pdev) } sspi->master = master; - sspi->fifo_depth = (unsigned long)of_device_get_match_data(&pdev->dev); + sspi->cfg = of_device_get_match_data(&pdev->dev); master->max_speed_hz = 100 * 1000 * 1000; master->min_speed_hz = 3 * 1000; @@ -695,9 +699,17 @@ static void sun6i_spi_remove(struct platform_device *pdev) dma_release_channel(master->dma_rx); } +static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = { + .fifo_depth = SUN6I_FIFO_DEPTH, +}; + +static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = { + .fifo_depth = SUN8I_FIFO_DEPTH, +}; + static const struct of_device_id sun6i_spi_match[] = { - { .compatible = "allwinner,sun6i-a31-spi", .data = (void *)SUN6I_FIFO_DEPTH }, - { .compatible = "allwinner,sun8i-h3-spi", .data = (void *)SUN8I_FIFO_DEPTH }, + { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg }, + { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg }, {} }; MODULE_DEVICE_TABLE(of, sun6i_spi_match); From patchwork Wed May 10 08:11:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13236604 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4340DC77B7D for ; Wed, 10 May 2023 08:12:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236565AbjEJIMK (ORCPT ); Wed, 10 May 2023 04:12:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235952AbjEJIMI (ORCPT ); Wed, 10 May 2023 04:12:08 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D90DB5258; Wed, 10 May 2023 01:12:04 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-3078cc99232so3873913f8f.3; Wed, 10 May 2023 01:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683706323; x=1686298323; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=T8Xbue+dZrUS0EtWBIjxZwNQ7G1HJWZPzEox+l8G5TM=; b=ilLqa4TIHk3vsCNzQPNPreZVusj7unaBLMLeM5ZUQEL7RYDEKZGyeg6Po5XgRyhIM9 NA1ZpzcrniOt2D/B7rIgjZ5dguaybhSBgQHaALXnjc5VlMDXyq0xs/QdKFcOys/TZGW4 vfwyqrnNqNV3tj35MYu03Fv6DvU1p7bjrEXFmXw1+gBOLB38BEy7zxp1A/8t6IMtVneX 1fyW66M5JjhJoef7SqkDgV5AxnoEz9lNfxDn+zaPZNrzgYid6uW6PUFiJKiOpuLgK5D+ SvsQKlIyiVtn8oUNmBLBVf831eKxd5n9Y6fIvgxxsq7gGZCdBGPMRWbwQuUNjQmFIUbM O71w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683706323; x=1686298323; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=T8Xbue+dZrUS0EtWBIjxZwNQ7G1HJWZPzEox+l8G5TM=; b=dUh50OKmSzFrhWh7PTJ0iFa5ac7oTy6KyFd1nEx742S+UmCiP0xmN5QwMVZPozrW0N 2vg/8EExLIsn83ZD+s56zWtCGpCfKtMTJlqiFDPu73wbJs4k71W+A+3nfV81vFMBjdag kow8d/MzOvafKmvSsx/WBCK9Cjr4RxXe+Wo6wnXlrB6t9ZiBeZkmDige2ZHYeZzT8Aqr nvycDH4JGbaPEqOLoucJZD59mbuWYP4+et5Mzxs8faGFKd/rL38eiZ6L+840ng0PPyBO tY1dzO076XNumpm2XXHxUOmiH3b1xMjdyn1Mwg8AVP0faA7+l2HqiyKQP9j+DOve+OUt /QBA== X-Gm-Message-State: AC+VfDztj1jJHfm30RccwyCnOaWIQds8Ewg07R9iybf5kauZr42VkfZh 3ZnnFeqWeNldKrxRoMBO/H8= X-Google-Smtp-Source: ACHHUZ6U+cGMbulmj6nJrRqn5l5Tf1FQijCWZ80FeaYUifagQC6IDHhOU5heb6VUO5cb2bd5NXRAjg== X-Received: by 2002:a5d:4c82:0:b0:307:a77c:c167 with SMTP id z2-20020a5d4c82000000b00307a77cc167mr3678929wrs.57.1683706323286; Wed, 10 May 2023 01:12:03 -0700 (PDT) Received: from localhost.localdomain ([176.221.215.212]) by smtp.gmail.com with ESMTPSA id f16-20020a5d4dd0000000b003062ad45243sm16496375wru.14.2023.05.10.01.12.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 01:12:02 -0700 (PDT) From: Maksim Kiselev To: Andre Przywara Cc: Icenowy Zheng , Maksim Kiselev , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Cristian Ciocaltea , Maxime Ripard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 3/5] spi: sun6i: add quirk for in-controller clock divider Date: Wed, 10 May 2023 11:11:10 +0300 Message-Id: <20230510081121.3463710-4-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230510081121.3463710-1-bigunclemax@gmail.com> References: <20230510081121.3463710-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Previously SPI controllers in Allwinner SoCs has a clock divider inside. However now the clock divider is removed and to set the transfer clock rate it's only needed to set the SPI module clock to the target value and configure a proper work mode. According to the datasheet there are three work modes: | SPI Sample Mode | SDM(bit13) | SDC(bit11) | Run Clock | |-------------------------|------------|------------|-----------| | normal sample | 1 | 0 | <= 24 MHz | | delay half cycle sample | 0 | 0 | <= 40 MHz | | delay one cycle sample | 0 | 1 | >= 80 MHz | Add a quirk for this kind of SPI controllers. Co-developed-by: Icenowy Zheng Signed-off-by: Maksim Kiselev Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/spi/spi-sun6i.c | 91 +++++++++++++++++++++++++++-------------- 1 file changed, 61 insertions(+), 30 deletions(-) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index 01a01cd86db5..e4efab310469 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -42,7 +42,9 @@ #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) #define SUN6I_TFR_CTL_DHB BIT(8) +#define SUN6I_TFR_CTL_SDC BIT(11) #define SUN6I_TFR_CTL_FBS BIT(12) +#define SUN6I_TFR_CTL_SDM BIT(13) #define SUN6I_TFR_CTL_XCH BIT(31) #define SUN6I_INT_CTL_REG 0x10 @@ -87,6 +89,7 @@ struct sun6i_spi_cfg { unsigned long fifo_depth; + bool has_clk_ctl; }; struct sun6i_spi { @@ -260,7 +263,7 @@ static int sun6i_spi_transfer_one(struct spi_master *master, struct spi_transfer *tfr) { struct sun6i_spi *sspi = spi_master_get_devdata(master); - unsigned int mclk_rate, div, div_cdr1, div_cdr2, timeout; + unsigned int div, div_cdr1, div_cdr2, timeout; unsigned int start, end, tx_time; unsigned int trig_level; unsigned int tx_len = 0, rx_len = 0; @@ -350,39 +353,65 @@ static int sun6i_spi_transfer_one(struct spi_master *master, sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); - /* Ensure that we have a parent clock fast enough */ - mclk_rate = clk_get_rate(sspi->mclk); - if (mclk_rate < (2 * tfr->speed_hz)) { - clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); - mclk_rate = clk_get_rate(sspi->mclk); - } + if (sspi->cfg->has_clk_ctl) { + unsigned int mclk_rate = clk_get_rate(sspi->mclk); - /* - * Setup clock divider. - * - * We have two choices there. Either we can use the clock - * divide rate 1, which is calculated thanks to this formula: - * SPI_CLK = MOD_CLK / (2 ^ cdr) - * Or we can use CDR2, which is calculated with the formula: - * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) - * Wether we use the former or the latter is set through the - * DRS bit. - * - * First try CDR2, and if we can't reach the expected - * frequency, fall back to CDR1. - */ - div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); - div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); - if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { - reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; - tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); + /* Ensure that we have a parent clock fast enough */ + if (mclk_rate < (2 * tfr->speed_hz)) { + clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); + mclk_rate = clk_get_rate(sspi->mclk); + } + + /* + * Setup clock divider. + * + * We have two choices there. Either we can use the clock + * divide rate 1, which is calculated thanks to this formula: + * SPI_CLK = MOD_CLK / (2 ^ cdr) + * Or we can use CDR2, which is calculated with the formula: + * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) + * Wether we use the former or the latter is set through the + * DRS bit. + * + * First try CDR2, and if we can't reach the expected + * frequency, fall back to CDR1. + */ + div_cdr1 = DIV_ROUND_UP(mclk_rate, tfr->speed_hz); + div_cdr2 = DIV_ROUND_UP(div_cdr1, 2); + if (div_cdr2 <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { + reg = SUN6I_CLK_CTL_CDR2(div_cdr2 - 1) | SUN6I_CLK_CTL_DRS; + tfr->effective_speed_hz = mclk_rate / (2 * div_cdr2); + } else { + div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); + reg = SUN6I_CLK_CTL_CDR1(div); + tfr->effective_speed_hz = mclk_rate / (1 << div); + } + + sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); } else { - div = min(SUN6I_CLK_CTL_CDR1_MASK, order_base_2(div_cdr1)); - reg = SUN6I_CLK_CTL_CDR1(div); - tfr->effective_speed_hz = mclk_rate / (1 << div); + clk_set_rate(sspi->mclk, tfr->speed_hz); + tfr->effective_speed_hz = clk_get_rate(sspi->mclk); + + /* + * Configure work mode. + * + * There are three work modes depending on the controller clock + * frequency: + * - normal sample mode : CLK <= 24MHz SDM=1 SDC=0 + * - delay half-cycle sample mode : CLK <= 40MHz SDM=0 SDC=0 + * - delay one-cycle sample mode : CLK >= 80MHz SDM=0 SDC=1 + */ + reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); + reg &= ~(SUN6I_TFR_CTL_SDM | SUN6I_TFR_CTL_SDC); + + if (tfr->effective_speed_hz <= 24000000) + reg |= SUN6I_TFR_CTL_SDM; + else if (tfr->effective_speed_hz >= 80000000) + reg |= SUN6I_TFR_CTL_SDC; + + sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); } - sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); /* Finally enable the bus - doing so before might raise SCK to HIGH */ reg = sun6i_spi_read(sspi, SUN6I_GBL_CTL_REG); reg |= SUN6I_GBL_CTL_BUS_ENABLE; @@ -701,10 +730,12 @@ static void sun6i_spi_remove(struct platform_device *pdev) static const struct sun6i_spi_cfg sun6i_a31_spi_cfg = { .fifo_depth = SUN6I_FIFO_DEPTH, + .has_clk_ctl = true, }; static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = { .fifo_depth = SUN8I_FIFO_DEPTH, + .has_clk_ctl = true, }; static const struct of_device_id sun6i_spi_match[] = { From patchwork Wed May 10 08:11:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13236605 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C489C77B7D for ; Wed, 10 May 2023 08:12:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236546AbjEJIMh (ORCPT ); Wed, 10 May 2023 04:12:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236599AbjEJIMZ (ORCPT ); Wed, 10 May 2023 04:12:25 -0400 Received: from mail-wr1-x42c.google.com (mail-wr1-x42c.google.com [IPv6:2a00:1450:4864:20::42c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CD6472B9; Wed, 10 May 2023 01:12:13 -0700 (PDT) Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-30786c6082dso2958545f8f.2; Wed, 10 May 2023 01:12:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683706331; x=1686298331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J7busPrq4Ix2D0XVL7/yDg+1KY42O5SIQ2uX5rrJTys=; b=cwfH/+hXjPVqsFqPAIMVFAMy/0AZnkWQv5AVzAZ4kFPGmzVfJfihnaFyDcE+SELLRt NOopU7B/B1n31QF6G211fNpBJQqAoY5hWVtj/0ecksqZLNLoo5SL55M1qGVXmbeW8VsN hdjpovHFnThVqzLFoeJi1QMDuIbJyKzt2y7ElcQnJgfUg8BRGDS1cxZY6c9WddnZrsyF hum5LUNIP6ExTkPdbNmdAP7TwUclhdPKtIdTBx5Sg+M2FKi/ypgCWDqrZsDaXwM5DmMt +U1pLrLSyv5+xgD0ftvRhqro6o9fehPhh9SAnZJH8PJfPoaytTlB1baXd7y+uEUIbcc0 c8Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683706331; x=1686298331; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J7busPrq4Ix2D0XVL7/yDg+1KY42O5SIQ2uX5rrJTys=; b=PF92t4vPycdw5FzNJsb8yCVXxUWFbJq4iyewUaw0IhCXIY2g/lz2qAEoKQGGlEy1L8 JDScRFHOfTB8gXeJMcC7U0Jm0LSlls8W/rwok0fJN4f23iH4PlK7ClSQhoyajm7zGJUK w5sAZSJIrtKbcmsOpNK9eHfWfBe8z3dh4FiGXI9qdy5DtJaLgSHm5QQqxJSMNLNR+dAw ly5vLTPNrRTAmqC9Jz5IVV/2qINJb82gtd4WsAbwlmR6Ge7MbQjQrX/lFE1LgsZ6z7bN rVHjRihwjtZ9piXgFmPk64+EiB2Etd3KjqZ3njCeyzTxh9N6NgMW0ZIJOojCQwtzhhsQ Taug== X-Gm-Message-State: AC+VfDxq7fdxUE4zQy39wOGRAs8qXklqFTI1mO3oJ8IMWofaE1oO9xcw kYhKuNRUQR0tzjfa2kqdgQU= X-Google-Smtp-Source: ACHHUZ4/QkzVl0TJSqhBhDoUCH2XfVGSUjiyUzXaRk2eB1bjvRBst+fKX1rWZ4a5w4/LIhNzGfSHSg== X-Received: by 2002:adf:f2c3:0:b0:306:2b81:88e1 with SMTP id d3-20020adff2c3000000b003062b8188e1mr12417493wrp.0.1683706331190; Wed, 10 May 2023 01:12:11 -0700 (PDT) Received: from localhost.localdomain ([176.221.215.212]) by smtp.gmail.com with ESMTPSA id f16-20020a5d4dd0000000b003062ad45243sm16496375wru.14.2023.05.10.01.12.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 01:12:10 -0700 (PDT) From: Maksim Kiselev To: Andre Przywara Cc: Icenowy Zheng , Maksim Kiselev , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Cristian Ciocaltea , Maxime Ripard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 4/5] spi: sun6i: add support for R329/D1/R528/T113s SPI controllers Date: Wed, 10 May 2023 11:11:11 +0300 Message-Id: <20230510081121.3463710-5-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230510081121.3463710-1-bigunclemax@gmail.com> References: <20230510081121.3463710-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org These SoCs has two SPI controllers. One of it is quite similar to previous ones, but with internal clock divider removed; the other added MIPI DBI Type-C offload based on the first one. Add basical support for these controllers. As we're not going to support the DBI functionality now, just implement the two kinds of controllers as the same. Co-developed-by: Icenowy Zheng Signed-off-by: Maksim Kiselev Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/spi/spi-sun6i.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/spi/spi-sun6i.c b/drivers/spi/spi-sun6i.c index e4efab310469..02a3a4f2b3a0 100644 --- a/drivers/spi/spi-sun6i.c +++ b/drivers/spi/spi-sun6i.c @@ -738,9 +738,17 @@ static const struct sun6i_spi_cfg sun8i_h3_spi_cfg = { .has_clk_ctl = true, }; +static const struct sun6i_spi_cfg sun50i_r329_spi_cfg = { + .fifo_depth = SUN8I_FIFO_DEPTH, +}; + static const struct of_device_id sun6i_spi_match[] = { { .compatible = "allwinner,sun6i-a31-spi", .data = &sun6i_a31_spi_cfg }, { .compatible = "allwinner,sun8i-h3-spi", .data = &sun8i_h3_spi_cfg }, + { + .compatible = "allwinner,sun50i-r329-spi", + .data = &sun50i_r329_spi_cfg + }, {} }; MODULE_DEVICE_TABLE(of, sun6i_spi_match); From patchwork Wed May 10 08:11:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maksim Kiselev X-Patchwork-Id: 13236606 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 31B37C7EE24 for ; Wed, 10 May 2023 08:12:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236472AbjEJIMx (ORCPT ); Wed, 10 May 2023 04:12:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231124AbjEJIMo (ORCPT ); Wed, 10 May 2023 04:12:44 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C1A217695; Wed, 10 May 2023 01:12:20 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id ffacd0b85a97d-30644c18072so4519551f8f.2; Wed, 10 May 2023 01:12:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683706339; x=1686298339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ziv+62Y+GAylpM/ibpSxQKGKhNzMiq6MRDwumNWDsYk=; b=VT0u/vcYhd5TFnEjTToBKJ/wdwffJ2L0okYTTCOhTHsgU8erF1p5oh+r9iXPW4wbu/ JnTop+tXh8VrgSxnao1lkFM/+EBiicRqWgtiLTRyblzOZnarhN2C1fvW4sK5B3VxXHpF 8FCZFeOgbkMduNe6GUL8qaFECRy9lAdSf8+8D4Y6X08m1sNwovljZAD5RT+YxswVePUH VOR8QElPUjAYXoUHoO+8GoCjVE1jPjgoHFcw46x7PiFzo7xQS6zIZTxOQHV68TNo4ouP L6luZ0nnd42ACFwel/2uGTpmtIKFHO65j7ENNms8hLs9EdPypPORR8im6mEBhNXO61Ov F6Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683706339; x=1686298339; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ziv+62Y+GAylpM/ibpSxQKGKhNzMiq6MRDwumNWDsYk=; b=HRy5O4VvKpsPOxDhjNvQKfWSWOwRxIgs8nfJlwv8DU6A+Quygp0TmNpCUE0yN4omRc HP1lGP1yjwZX4y8ZUOx1Hm66hWfqsR5v87zouaZJ00y0PRvhFY564u8u55qdZ/Ao+CsQ W47ieAhtEM3mn987D4l3FBn2pGHfJi3uomYQXg/b9vR3Vb+lZjqB+7RZsV7U873flDeG /rzsCcf1109I42nyTP6XVDLZ6MKyw7OMFHisEiqDMSfj3fKHo4T3hiT3+qC4gM4IrQP6 X1yoGv5vWLwL4X0fjLjGb55NEfObC8xmhKX7ggnaAv9JThA0+IrgxOTcDnCUQomR1WqO +b4A== X-Gm-Message-State: AC+VfDxVAkuC+y2RIH6sI9gG7YtdqYaICIEAgj1mSjcYCh4PuxtS/E6h 8q0Qet1f4JxN7xnwU6sy7ic= X-Google-Smtp-Source: ACHHUZ5sd70u2BkeoYnaZa5+eyQCVzqpqKrugxquzDd2XRbo7GFO2hlIBYRs0XLRBwAUP6Sj3isaqQ== X-Received: by 2002:adf:ecc4:0:b0:2f9:ee8c:a2fa with SMTP id s4-20020adfecc4000000b002f9ee8ca2famr12260618wro.64.1683706339136; Wed, 10 May 2023 01:12:19 -0700 (PDT) Received: from localhost.localdomain ([176.221.215.212]) by smtp.gmail.com with ESMTPSA id f16-20020a5d4dd0000000b003062ad45243sm16496375wru.14.2023.05.10.01.12.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 01:12:18 -0700 (PDT) From: Maksim Kiselev To: Andre Przywara Cc: Icenowy Zheng , Maksim Kiselev , Conor Dooley , Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Paul Walmsley , Palmer Dabbelt , Albert Ou , Cristian Ciocaltea , Maxime Ripard , linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: [PATCH v5 5/5] riscv: dts: allwinner: d1: Add SPI controllers node Date: Wed, 10 May 2023 11:11:12 +0300 Message-Id: <20230510081121.3463710-6-bigunclemax@gmail.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230510081121.3463710-1-bigunclemax@gmail.com> References: <20230510081121.3463710-1-bigunclemax@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Some boards form the MangoPi family (MQ\MQ-Dual\MQ-R) may have an optional SPI flash that connects to the SPI0 controller. This controller is the same for R329/D1/R528/T113s SoCs and should be supported by the sun50i-r329-spi driver. So let's add its DT nodes. Signed-off-by: Maksim Kiselev Acked-by: Conor Dooley Reviewed-by: Andre Przywara Reviewed-by: Jernej Skrabec --- .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 922e8e0e2c09..1bb1e5cae602 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -108,6 +108,12 @@ rmii_pe_pins: rmii-pe-pins { function = "emac"; }; + /omit-if-no-ref/ + spi0_pins: spi0-pins { + pins = "PC2", "PC3", "PC4", "PC5"; + function = "spi0"; + }; + /omit-if-no-ref/ uart1_pg6_pins: uart1-pg6-pins { pins = "PG6", "PG7"; @@ -447,6 +453,37 @@ mmc2: mmc@4022000 { #size-cells = <0>; }; + spi0: spi@4025000 { + compatible = "allwinner,sun20i-d1-spi", + "allwinner,sun50i-r329-spi"; + reg = <0x04025000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>; + clock-names = "ahb", "mod"; + dmas = <&dma 22>, <&dma 22>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI0>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + + spi1: spi@4026000 { + compatible = "allwinner,sun20i-d1-spi-dbi", + "allwinner,sun50i-r329-spi-dbi", + "allwinner,sun50i-r329-spi"; + reg = <0x04026000 0x1000>; + interrupts = ; + clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>; + clock-names = "ahb", "mod"; + dmas = <&dma 23>, <&dma 23>; + dma-names = "rx", "tx"; + resets = <&ccu RST_BUS_SPI1>; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + usb_otg: usb@4100000 { compatible = "allwinner,sun20i-d1-musb", "allwinner,sun8i-a33-musb";