From patchwork Wed May 10 15:32:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13237018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D23BEC7EE22 for ; Wed, 10 May 2023 15:33:26 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pwlo9-0007Be-LJ; Wed, 10 May 2023 11:32:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pwlo6-0007AW-UG for qemu-devel@nongnu.org; Wed, 10 May 2023 11:32:46 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pwlnv-0000Tr-Hx for qemu-devel@nongnu.org; Wed, 10 May 2023 11:32:46 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3f42bcf5df1so21165295e9.3 for ; Wed, 10 May 2023 08:32:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683732753; x=1686324753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qDPTs09PsI8EmAO4/Xss2kSkklk22rd5jb1ypAYGrnQ=; b=epEmcP0cKwkup7fXmkXlQGfN8nuYXmsLefruZRj/qA31GHjhg6koFg8oyPqenYf/3X Y4mTQO7hN0yWvtI/BAqo9vYStkQoY3K+ZB8CctsUEhCIvxk5NESfFftUEtix5OjGVLs0 D185PCFgk1ldlAHXvLRj22R6cwssUMhKVmoIhXeQcVW4r0ONOqSyLWWANw8tj2sfmAve NynxWONKABBTR5vS3owwivmeWkyLZzNVE8/sAiwPwU97c+Kf/brrza/4HBIfto1l/S2C q2z1sAAC0c3SAHTWIyfTDsSMSTwGylW06tDL5UYraQV1LKGVBPzrd7Kc3yG1amVQSU+M v9wQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683732753; x=1686324753; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qDPTs09PsI8EmAO4/Xss2kSkklk22rd5jb1ypAYGrnQ=; b=Y++O/4zfuR51gw8dR+4ttcgtkojtoDn+zsLHdnSnREXSzmOdXAcmVxzyXSalNcTLRN 4JtMULfhjQworCNecJ3tQjfjk4Pq6rV//Z2rptpF4Aglk3VdeSsi4l1cDWRCBrPOt9F+ p9rOBCr+rgGiPxx0FGFNdpgAUwxOppzFBAtRKWduZW5Zr2NtOCDEAmamhT8ocGAK7IRH Ym0EEu6k8Y3As9xJMjpCVTGgAI+l45vgyZWLQJ28CBmjVmn9UA/lmvJ/AxGGyp2aljNw eXkDb1rRanhLOHhRFBCUdRDmUJCBNVdJCT0uCjXVn+coU46YTopUBJ+go5rUXsl/BEou HcOg== X-Gm-Message-State: AC+VfDzzYtZ5fBgWVnf5jN3GV2t2S2axEu/hKLqBPbUbRSwml0aOsCoI puzAPvpexJcLRW1KlPergI65xdUndbo= X-Google-Smtp-Source: ACHHUZ4Xam3SROJR5VZbQtn2jANf9Bj4Px+G++RnPNS1xE4CRvH+0C4d12wTrmCd53ZDrQ8k5WTUuQ== X-Received: by 2002:adf:f790:0:b0:2f2:7a0e:5cc9 with SMTP id q16-20020adff790000000b002f27a0e5cc9mr11228526wrp.19.1683732753620; Wed, 10 May 2023 08:32:33 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id b15-20020a5d4b8f000000b003064600cff9sm17660531wrt.38.2023.05.10.08.32.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 08:32:33 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne Subject: [PATCH v2 1/3] target/openrisc: Allow fpcsr access in user mode Date: Wed, 10 May 2023 16:32:26 +0100 Message-Id: <20230510153228.264954-2-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230510153228.264954-1-shorne@gmail.com> References: <20230510153228.264954-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=shorne@gmail.com; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As per OpenRISC spec 1.4 FPCSR can be read and written in user mode. Update mtspr and mfspr helpers to support this by moving the is_user check into the helper. Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- Since v1: - Update commit message to remove text about no-existant logic change. target/openrisc/sys_helper.c | 45 +++++++++++++++++----- target/openrisc/translate.c | 72 ++++++++++++++++-------------------- 2 files changed, 67 insertions(+), 50 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ec145960e3..8a0259c710 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -29,17 +29,37 @@ #define TO_SPR(group, number) (((group) << 11) + (number)) +static inline bool is_user(CPUOpenRISCState *env) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return (env->sr & SR_SM) == 0; +#endif +} + void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) { -#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = env_archcpu(env); +#ifndef CONFIG_USER_ONLY CPUState *cs = env_cpu(env); target_ulong mr; int idx; #endif + /* Handle user accessible SPRs first. */ switch (spr) { + case TO_SPR(0, 20): /* FPCSR */ + cpu_set_fpcsr(env, rb); + return; + } + + if (is_user(env)) { + raise_exception(cpu, EXCP_ILLEGAL); + } + #ifndef CONFIG_USER_ONLY + switch (spr) { case TO_SPR(0, 11): /* EVBAR */ env->evbar = rb; break; @@ -187,12 +207,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) cpu_openrisc_timer_update(cpu); qemu_mutex_unlock_iothread(); break; -#endif - - case TO_SPR(0, 20): /* FPCSR */ - cpu_set_fpcsr(env, rb); - break; } +#endif } target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, @@ -204,10 +220,22 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, OpenRISCCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); int idx; +#else + OpenRISCCPU *cpu = env_archcpu(env); #endif + /* Handle user accessible SPRs first. */ switch (spr) { + case TO_SPR(0, 20): /* FPCSR */ + return env->fpcsr; + } + + if (is_user(env)) { + raise_exception(cpu, EXCP_ILLEGAL); + } + #ifndef CONFIG_USER_ONLY + switch (spr) { case TO_SPR(0, 0): /* VR */ return env->vr; @@ -324,11 +352,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, cpu_openrisc_count_update(cpu); qemu_mutex_unlock_iothread(); return cpu_openrisc_count_get(cpu); -#endif - - case TO_SPR(0, 20): /* FPCSR */ - return env->fpcsr; } +#endif /* for rd is passed in, if rd unchanged, just keep it back. */ return rd; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 76e53c78d4..43ba0cc1ad 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -819,45 +819,12 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a) static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) { - check_r0_write(dc, a->d); - - if (is_user(dc)) { - gen_illegal_exception(dc); - } else { - TCGv spr = tcg_temp_new(); - - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - if (dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - } else { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); - } - dc->base.is_jmp = DISAS_EXIT; - } + TCGv spr = tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); - } - return true; -} - -static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) -{ - if (is_user(dc)) { - gen_illegal_exception(dc); - } else { - TCGv spr; + check_r0_write(dc, a->d); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - /* For SR, we will need to exit the TB to recognize the new - * exception state. For NPC, in theory this counts as a branch - * (although the SPR only exists for use by an ICE). Save all - * of the cpu state first, allowing it to be overwritten. - */ + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); if (dc->delayed_branch) { tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_discard_tl(jmp_pc); @@ -865,11 +832,36 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); } dc->base.is_jmp = DISAS_EXIT; + } + + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); + return true; +} + +static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) +{ + TCGv spr = tcg_temp_new(); - spr = tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); } + /* + * For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp = DISAS_EXIT; + + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); return true; } From patchwork Wed May 10 15:32:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13237019 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 09AD7C77B7C for ; Wed, 10 May 2023 15:33:42 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pwloD-0007DL-Hx; Wed, 10 May 2023 11:32:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pwlo7-0007Ap-8a for qemu-devel@nongnu.org; Wed, 10 May 2023 11:32:47 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pwlnw-0000Tz-Tl for qemu-devel@nongnu.org; Wed, 10 May 2023 11:32:46 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f4249b7badso38276535e9.3 for ; Wed, 10 May 2023 08:32:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683732755; x=1686324755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=csrTYP46uv8wz6vyHOZQLXOhfuaiNnRYRLiW7uRVmzE=; b=azReCyQo9AgaGA3ibfYJryDdwquXFqJwPZwK0X3Dm7urN26R+XZbpLATyGxBarPO+i k7ftL5jcOPnE7EKvuFlaLv2TD9/5/IvTkpkhFHkWLAB+8ukQkPkuaPRVC9rXpC3f6KrO Fs1NSosBcw3/1CEtTRe1+NDu2yBY4Q07/EDs7VQTvFGBCsnFmZWenqSSfIVxmgnlvpe8 ihlMC3tonynFOnUaDURRitZcA5QkJlhKX5jRlFaj5bPqXiPU1t06cTBaAP/HHlSvmKMa ybA1xkRQPPjGPmS8KoOAvx96aiiEL33i+KsqOGr3BN3PUckYiorJFkOPs48TVNeVDmV8 xMNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683732755; x=1686324755; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=csrTYP46uv8wz6vyHOZQLXOhfuaiNnRYRLiW7uRVmzE=; b=MWItqutlRoKSFZIqce0B5FwTGRxMXfAZYZxeZvIvkpiiK184qGM+31HIpo78G1ec4J qRH+sysajrJEIWi4yK/viEGIaFJ5OCgSlDeHfkeYyTTX7QERZvwzu5RFWZjrOa1y5iZN m1v4Q4RPAVEM4OGMA8ZYXn8EbfT8dfYwa0D4u4QN3bztJwXNmhSO+p/Z6pKyNkRrjswN idQI+YF4Lgwf110tKUyyYQzHSFhgptAhuUbi12ZfPLu0P2AothxiApNjcFMW97COm6m3 h8kLoJdxuKWdtO7FZ5Zsh6N8rUpPxw/x6NIiVLxqOHlezMxutAKz2jDc3aAGAtyZrmep 7ESA== X-Gm-Message-State: AC+VfDzphamUUhyKlTgqU2AejQiq4WD5ld/4JLqUFKKAnGa1wDdsgcQs ZzcxHcSfDNZgtx2PuMK7T+o0yMzBg7s= X-Google-Smtp-Source: ACHHUZ4d8w3jwX0NwLaCbLZ+ubxAXF2N260dZROoXaUG1NICx/cqcEC0cnoWdEno8KdyavlNhKXpzQ== X-Received: by 2002:a7b:c5d2:0:b0:3f3:2b37:dd34 with SMTP id n18-20020a7bc5d2000000b003f32b37dd34mr11817929wmk.9.1683732754947; Wed, 10 May 2023 08:32:34 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id z17-20020a1c4c11000000b003ee20b4b2dasm22951062wmf.46.2023.05.10.08.32.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 08:32:34 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne Subject: [PATCH v2 2/3] target/openrisc: Set PC to cpu state on FPU exception Date: Wed, 10 May 2023 16:32:27 +0100 Message-Id: <20230510153228.264954-3-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230510153228.264954-1-shorne@gmail.com> References: <20230510153228.264954-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=shorne@gmail.com; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Store the PC to ensure the correct value can be read in the exception handler. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- Since v1: - Use function do_fpe (similar to do_range) to raise exception. target/openrisc/fpu_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index f9e34fa2cc..8b81d2f62f 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -20,8 +20,8 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exception.h" #include "fpu/softfloat.h" static int ieee_ex_to_openrisc(int fexcp) @@ -45,6 +45,15 @@ static int ieee_ex_to_openrisc(int fexcp) return ret; } +static G_NORETURN +void do_fpe(CPUOpenRISCState *env, uintptr_t pc) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = EXCP_FPE; + cpu_loop_exit_restore(cs, pc); +} + void HELPER(update_fpcsr)(CPUOpenRISCState *env) { int tmp = get_float_exception_flags(&env->fp_status); @@ -55,7 +64,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env) if (tmp) { env->fpcsr |= tmp; if (env->fpcsr & FPCSR_FPEE) { - helper_exception(env, EXCP_FPE); + do_fpe(env, GETPC()); } } } From patchwork Wed May 10 15:32:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13237020 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2A983C7EE22 for ; Wed, 10 May 2023 15:33:57 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pwlo9-0007Bp-SH; Wed, 10 May 2023 11:32:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pwlo8-0007BG-0C for qemu-devel@nongnu.org; Wed, 10 May 2023 11:32:48 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pwlny-0000U8-CP for qemu-devel@nongnu.org; Wed, 10 May 2023 11:32:47 -0400 Received: by mail-wr1-x434.google.com with SMTP id ffacd0b85a97d-2fe3fb8e25fso4948096f8f.0 for ; Wed, 10 May 2023 08:32:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683732756; x=1686324756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QuCoDiAObR/Z2Z2rP0Xwqovsoce8UpTQfGK7ANVfuJg=; b=KIsq5p2U2yMptwyjPYSaCRAThtTaWZ7xLaVsAKqsv53q6EYaNAbeyZGRkhGOBSiGpV /FtDPMApZ6haqXtdRbhT2zHiiedDuDqOALgALSaxZSPUb5e9mNhff1ZqkydMMiKKCwdg ktmlaBEb3jeacH+9jMCubIOiFjUW7aqgeTf0rxKmScofNOnsl5cBRYmFLD2jVwbIH02p BGSZqLXJiiRW8zPQ776azOljZnWCXq5VjcnTEMoGCsKmPZPVkpDE/jCb0RMDXwsolvMz 2UQurxQ+k66wlwfx/W+AlfV9i+9L+hRHdFaVkvclfegtlBbPCBsCXyKupZ5aDLBIt48o e3uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683732756; x=1686324756; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QuCoDiAObR/Z2Z2rP0Xwqovsoce8UpTQfGK7ANVfuJg=; b=dKLkByk8AxGHgzVk24PItYSpYmUgYWYZswYH244vYUh82BZwMWdYxtvPHMYvPLsw1i bIZP9JsLu9Ywns9F1oUiOPfy8ntM7rRvKWJjogYHgIu9KN0MjEHh2TbugfVxDBPP1yjk 6m4dT1y+fma3UOnhkYtsf865lIXFxlzWQLpqPKBl/LtwNxGuGsCsXPVvxtbmPzO6PLYt 8K57BcukYZd421VusBAXdIKgjHm5RBEZuQq2CEXK5AW7JnjjhdkPYmCb6MMm6RpKKcIz oMZoLcSBE3XoxaQ6y/KmIfAziXrVxlADjt50hHjeDjVr35HwfR08Yq4qFhTTESdgL3Lt ZJqw== X-Gm-Message-State: AC+VfDzS3sII+ohi8Q79O6Wl+OsiMWjaJtfgpSOKl/VP5zmqzSDzifmo nH4lAYtDS85gQ1XOuiO0Mfrb5JSoorQ= X-Google-Smtp-Source: ACHHUZ6vtCmnt4hzcunQjfDLkcgztJ61GW3/hX6XhjJkp2R2GdOU49jEXRlVGXgXiaDAqsXiqhB+9w== X-Received: by 2002:a5d:510a:0:b0:304:8149:239b with SMTP id s10-20020a5d510a000000b003048149239bmr11917447wrt.50.1683732756332; Wed, 10 May 2023 08:32:36 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id r10-20020a056000014a00b00307972e46fasm9394157wrx.107.2023.05.10.08.32.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 May 2023 08:32:35 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne Subject: [PATCH v2 3/3] target/openrisc: Setup FPU for detecting tininess before rounding Date: Wed, 10 May 2023 16:32:28 +0100 Message-Id: <20230510153228.264954-4-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230510153228.264954-1-shorne@gmail.com> References: <20230510153228.264954-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=shorne@gmail.com; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org OpenRISC defines tininess to be detected before rounding. Setup qemu to obey this. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- Since v1: - Remove setting default NaN behavior. I discussed with the FPU developers and they mentioned the OpenRISC hardware should be IEEE compliant when handling and forwarding NaN payloads, and they don't want try change this. target/openrisc/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 0ce4f796fa..61d748cfdc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -90,6 +91,9 @@ static void openrisc_cpu_reset_hold(Object *obj) s->exception_index = -1; cpu_set_fpcsr(&cpu->env, 0); + set_float_detect_tininess(float_tininess_before_rounding, + &cpu->env.fp_status); + #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; cpu->env.picsr = 0x00000000;