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Miller" , Jakub Kicinski , Richard Cochran , Jacob Keller Subject: [PATCH net-next 1/9] ptp: Clarify ptp_clock_info .adjphase expects an internal servo to be used Date: Wed, 10 May 2023 13:52:58 -0700 Message-Id: <20230510205306.136766-2-rrameshbabu@nvidia.com> X-Mailer: git-send-email 2.38.4 In-Reply-To: <20230510205306.136766-1-rrameshbabu@nvidia.com> References: <20230510205306.136766-1-rrameshbabu@nvidia.com> X-ClientProxiedBy: SJ0PR05CA0105.namprd05.prod.outlook.com (2603:10b6:a03:334::20) To BYAPR12MB2743.namprd12.prod.outlook.com (2603:10b6:a03:61::28) Precedence: bulk X-Mailing-List: netdev@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BYAPR12MB2743:EE_|MW5PR12MB5624:EE_ X-MS-Office365-Filtering-Correlation-Id: 171fec36-805b-403d-fe6a-08db5198a717 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k+ez4ewNZRrv2TLUFgvNeVxSlPZ8V/p9/2iYnV/VeIgnfjFbQa+wjSFflvUrS+Mbxpq215CDDcDh/eICoFzFOx50SOrX75oW8kkBs1B0ZIJ7hgJ728bNTfajqV+BLBrs8ddt28x6AwQgqUviqHaeFzPhTwzCslOzyRi/KXtYv0y7iJqZgr79UAghkRRxWUP1cwXcdov7qsTTqXqDaPEQnp+2vwzTL67fEyKbXR2+Y0mF5QvifXuRROAIx6kVVf21tkkSVl2QVdVOMFDcIQCvQgPkMJDxjVZPyGcIio9uJDPrTSb/vgNCSe+c3E2fShdkW8JSidF+06c9pzdXXOvw7tZFWQ6s+SQRYB7VdvI+PZez15y3RzVhNH40d2wogD8Dne3/h0nftLVf5NWUEhgLkyat7EffXnFv5E5Ik1pJJ52lqCiQETjpmle9ii/gDVuQMKq2V5IDNuy0vE//C9Cp73cJVu0Q3cdONqQ5Cq/Pr2uPolp2xmMVzy2SRIMQ2DbamA6X9lDeKkP6C4l/JqtCt257s5Tak/Rb0iS8YLRsQGKqUOPHIHZ4LxIm7MFyGwBJH98XgiDTlXyWnb/H9oqHDM6X4EsLotA5+IV5XT0TX6qVCYQamaO4BadRLbBLUOg8 X-Forefront-Antispam-Report: CIP:255.255.255.255;CTRY:;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:BYAPR12MB2743.namprd12.prod.outlook.com;PTR:;CAT:NONE;SFS:(13230028)(4636009)(346002)(136003)(39860400002)(366004)(396003)(376002)(451199021)(86362001)(5660300002)(41300700001)(4326008)(6666004)(38100700002)(316002)(6486002)(6506007)(6512007)(26005)(1076003)(478600001)(54906003)(36756003)(2906002)(8936002)(8676002)(186003)(83380400001)(66946007)(6916009)(66476007)(66556008)(2616005)(142923001);DIR:OUT;SFP:1101; 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Implementation of the internal servo algorithm are defined by the individual devices. Cc: Jakub Kicinski Cc: Richard Cochran Signed-off-by: Rahul Rameshbabu --- Documentation/driver-api/ptp.rst | 17 +++++++++++++++++ include/linux/ptp_clock_kernel.h | 6 ++++-- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/Documentation/driver-api/ptp.rst b/Documentation/driver-api/ptp.rst index 664838ae7776..c6ef41cf6130 100644 --- a/Documentation/driver-api/ptp.rst +++ b/Documentation/driver-api/ptp.rst @@ -73,6 +73,23 @@ Writing clock drivers class driver, since the lock may also be needed by the clock driver's interrupt service routine. +PTP hardware clock requirements for '.adjphase' +----------------------------------------------- + + The 'struct ptp_clock_info' interface has a '.adjphase' function. + This function has a set of requirements from the PHC in order to be + implemented. + + * The PHC implements a servo algorithm internally that is used to + correct the offset passed in the '.adjphase' call. + * When other PTP adjustment functions are called, the PHC servo + algorithm is disabled, and the frequency prior to the '.adjphase' + call is restored internally in the PHC. + + **NOTE:** '.adjphase' is not a simple time adjustment functionality + that 'jumps' the PHC clock time based on the provided offset. It + should correct the offset provided using an internal algorithm. + Supported hardware ================== diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h index fdffa6a98d79..f8e8443a8b35 100644 --- a/include/linux/ptp_clock_kernel.h +++ b/include/linux/ptp_clock_kernel.h @@ -77,8 +77,10 @@ struct ptp_system_timestamp { * nominal frequency in parts per million, but with a * 16 bit binary fractional field. * - * @adjphase: Adjusts the phase offset of the hardware clock. - * parameter delta: Desired change in nanoseconds. + * @adjphase: Indicates that the PHC should use an internal servo + * algorithm to correct the provided phase offset. + * parameter delta: PHC servo phase adjustment target + * in nanoseconds. * * @adjtime: Shifts the time of the hardware clock. * parameter delta: Desired change in nanoseconds. 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This patch adds information about the Mellanox device family. Signed-off-by: Rahul Rameshbabu Acked-by: Richard Cochran --- Documentation/driver-api/ptp.rst | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/driver-api/ptp.rst b/Documentation/driver-api/ptp.rst index c6ef41cf6130..6eab5253b800 100644 --- a/Documentation/driver-api/ptp.rst +++ b/Documentation/driver-api/ptp.rst @@ -123,3 +123,16 @@ Supported hardware - LPF settings (bandwidth, phase limiting, automatic holdover, physical layer assist (per ITU-T G.8273.2)) - Programmable output PTP clocks, any frequency up to 1GHz (to other PHY/MAC time stampers, refclk to ASSPs/SoCs/FPGAs) - Lock to GNSS input, automatic switching between GNSS and user-space PHC control (optional) + + * NVIDIA Mellanox + + - GPIO + - Certain variants of ConnectX-6 Dx and later products support one + GPIO which can time stamp external triggers and one GPIO to produce + periodic signals. + - Certain variants of ConnectX-5 and older products support one GPIO, + configured to either time stamp external triggers or produce + periodic signals. + - PHC instances + - All ConnectX devices have a free-running counter + - ConnectX-6 Dx and later devices have a UTC format counter From patchwork Wed May 10 20:53:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Rameshbabu X-Patchwork-Id: 13237261 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CC7F21CDD for ; Wed, 10 May 2023 20:59:14 +0000 (UTC) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2074.outbound.protection.outlook.com [40.107.244.74]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5A15729D for ; Wed, 10 May 2023 13:58:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=CTWicWeyFSgtfmRmnRxHvOj1L3ypDkVg8I/TqQ8hp45KPm7oYJA18+s7ivK0zarqCbXY3/FSK31Ga7cgd6t5pnd9ab3gEFZRGvCk774qVIznp97qtam6FX07oy9am7qHqzEYSSUmf9srKcBA1quYyyLnHZzuTvOuw/jMO6RZf9OgRT2iK7PDOvYSFCwAfhbcojL+4rTVr0DhwSHzkdBrHDGTK24xkFavonW9y/VqR95AOjWtbkbK9n1wzV9XfmINH8LCTL0Dh0/Gn2hgZGZKeTMU4ZtEmEmGBURcZxsVXyr0cNYkz9SvIMonuqtV+JFNvOyctkDSHuZdifLs0B5SCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=c1KmTdOfEKSuPeNZeRYC4urBdlOKgDxcAA+qdlwQfr8=; b=HRxIEZGvtIIFRyIYTU6U5eaWsvvByHxPV4NKKPBjmgfQWiuymhGJ/+8WgXAL0+7NiozuUbNyGSyek+/CNxIJMDk4El7A4GKWwA0nhobr3ragboyZu4QqTWAJD0v2lNueh642/obEwdUbF1IdtquTCP1P7Ys1h/8F6n5k2XVmyp0Qh5axlo4PY7athnsSOzv9RAhwYz+h+buW7/Sdgdw6ut7VjG0nalaS8bztQ5dCRy4pX8UWGcFjaRGmqbA7jE++C2aQQwBmTbp25ucVZ7t5wxeMz0hAR7SjTSrc+vJpbMDRGEl7yYQdpXlJi5kfPbySm9Xg0kV6q69iKSa8uHvVQA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=c1KmTdOfEKSuPeNZeRYC4urBdlOKgDxcAA+qdlwQfr8=; b=YLeA9Yf1SGPutlcOM0gDcAtqQ0MHnOCjWkiludg/4GlPzWw8BdZUtXVzfgzzLxb2yaHpvaxtAnzB7hhOihMvQmqz7RQsAosec9ZRv7JifetSEUO8iENqwJEq3iI6k29+exAuoVUg1rAPDCLiPguZGHUR3Tb0oVqvZ7AZojFzSqXtw6kWA7zwOqPN8f+EsBg/FkyoZvTidjRJmgDHww9FX4NrF8y+xHGTxTmVv6pMgRqP7iYsI5U2USMlmZKDXxT6sn81K97h7Oq6d1uCaU0i3bb2xNHozZIES7aucRJJUmBDEEi48WpcFO6NmblJsZuDi/FS4iz77PNrH7OMgaDHYQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from BYAPR12MB2743.namprd12.prod.outlook.com (2603:10b6:a03:61::28) by MW5PR12MB5624.namprd12.prod.outlook.com (2603:10b6:303:19d::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.18; Wed, 10 May 2023 20:53:52 +0000 Received: from BYAPR12MB2743.namprd12.prod.outlook.com ([fe80::de5a:9000:2d2f:a861]) by BYAPR12MB2743.namprd12.prod.outlook.com ([fe80::de5a:9000:2d2f:a861%7]) with mapi id 15.20.6363.033; Wed, 10 May 2023 20:53:52 +0000 From: Rahul Rameshbabu To: netdev@vger.kernel.org Cc: Saeed Mahameed , Gal Pressman , Tariq Toukan , "David S. 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Cc: Jakub Kicinski Cc: Shuah Khan Cc: Richard Cochran Cc: Maciek Machnikowski Signed-off-by: Rahul Rameshbabu Acked-by: Richard Cochran --- tools/testing/selftests/ptp/testptp.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c index 198ad5f32187..ca2b03d57aef 100644 --- a/tools/testing/selftests/ptp/testptp.c +++ b/tools/testing/selftests/ptp/testptp.c @@ -110,7 +110,7 @@ static long ppb_to_scaled_ppm(int ppb) static int64_t pctns(struct ptp_clock_time *t) { - return t->sec * 1000000000LL + t->nsec; + return t->sec * NSEC_PER_SEC + t->nsec; } static void usage(char *progname) @@ -317,7 +317,7 @@ int main(int argc, char *argv[]) tx.time.tv_usec = adjns; while (tx.time.tv_usec < 0) { tx.time.tv_sec -= 1; - tx.time.tv_usec += 1000000000; + tx.time.tv_usec += NSEC_PER_SEC; } if (clock_adjtime(clkid, &tx) < 0) { From patchwork Wed May 10 20:53:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Rameshbabu X-Patchwork-Id: 13237255 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 647F821CC4 for ; Wed, 10 May 2023 20:57:55 +0000 (UTC) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2060e.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe5a::60e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C4E98A60 for ; Wed, 10 May 2023 13:57:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TBEnMKHRHO5a0OP0Bb+sDYwjbITqgmUth5YgXYCSTm2mGBf1/U87Bh940hz3jnN3YPA/Hs5QoEGPZ+yysANs8H/wlgB2ivNR6YuHAyNmfM1e/sMwUA9DPMTo6x2R/DZJ1+R+vTDslXN3MARYyOY8k/Qj3FvCpuslmiS2ZmbarfXLgusF/reFoygoHKK5gSWHgSlYqiGRn+1e4cpFhtHvelHGI4isOMaVCpuaxnKhdeOCufk8gs2wPJCS1exOLOBQMkQqVtnDbcXQ7buw+es1A3IqpDLB8UxSNNv/O8OsY0cAACJdzR3szV8ArE4iYABioY+78Yp/AFVX0YxQr9CwpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=3l58gfbJDCz4OLrUG6plTxaF1O4DIYrW7WT6qLyxPpY=; b=BLeqGN8H8H+m10IXk265Qo9zRX+xLx7TjFla/xsDZlpyXq4dbKBaq6PcKFdOSyhnduQYQ6C386RExLASZnXGDDWaSZ2ki4Q+5BUVCIf/X/ufWe7IhTnD6lfoxdwsQxMittAxd0qW89HyA8kDbWzo6sEqI3VZ62K5Bao7gnYMJckbYtBlkVzgPTTQrRCgwgPSndsmfi9Ytf8ar+JKc4+ACsh4x0XznmZTi5OnJokOLvC+cowFLrNfv6/O2qbLBjXfD7u+ubHosyaF6HdjJu24DvGyzPYb44yMGj44kuCT6jYOi/GfmMr8l7xcaegvaIO+YazztfYE2yRXnW9Ah5/+3g== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=3l58gfbJDCz4OLrUG6plTxaF1O4DIYrW7WT6qLyxPpY=; b=TaKaVicGszPmtkwRRn3cbZx34YoqoK3rqWzHj+H+N65mfOmK3UgPBdoPS58J/tZLW7fGJPjXPQpztYpE88viprPXX4My1qERwvYXIi5U6g08FOyvIFo8TmP+ASEYHwuzTuRdCYvH4BSGT7Zyu+4R4HVGdOna2B0Tj/V4fWTa8XaBcYwALMuRYpxnHRCtww9EhY3ldJQ7/Xniw1KQrlxaPWWs7ugmJ3lt6UtdmNQbIPpTzIGjN9oSekUExfLL2ugFp4hFik4Rsurs7pDjDf/QQr5tyh4CAHqvv7CZ734f8mMIvPcoveQaXRex2dNOWGY9XojTOq9DQflAIJWstS6PZg== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from BYAPR12MB2743.namprd12.prod.outlook.com (2603:10b6:a03:61::28) by MW5PR12MB5624.namprd12.prod.outlook.com (2603:10b6:303:19d::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.18; Wed, 10 May 2023 20:53:54 +0000 Received: from BYAPR12MB2743.namprd12.prod.outlook.com ([fe80::de5a:9000:2d2f:a861]) by BYAPR12MB2743.namprd12.prod.outlook.com ([fe80::de5a:9000:2d2f:a861%7]) with mapi id 15.20.6363.033; Wed, 10 May 2023 20:53:54 +0000 From: Rahul Rameshbabu To: netdev@vger.kernel.org Cc: Saeed Mahameed , Gal Pressman , Tariq Toukan , "David S. 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Support seconds and nanoseconds for the offset value. Cc: Jakub Kicinski Cc: Shuah Khan Cc: Richard Cochran Cc: Maciek Machnikowski Signed-off-by: Rahul Rameshbabu Acked-by: Richard Cochran --- tools/testing/selftests/ptp/testptp.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c index ca2b03d57aef..ae23ef51f198 100644 --- a/tools/testing/selftests/ptp/testptp.c +++ b/tools/testing/selftests/ptp/testptp.c @@ -134,6 +134,7 @@ static void usage(char *progname) " 1 - external time stamp\n" " 2 - periodic output\n" " -n val shift the ptp clock time by 'val' nanoseconds\n" + " -o val phase offset (in nanoseconds) to be provided to the PHC servo\n" " -p val enable output with a period of 'val' nanoseconds\n" " -H val set output phase to 'val' nanoseconds (requires -p)\n" " -w val set output pulse width to 'val' nanoseconds (requires -p)\n" @@ -167,6 +168,7 @@ int main(int argc, char *argv[]) int adjfreq = 0x7fffffff; int adjtime = 0; int adjns = 0; + int adjphase = 0; int capabilities = 0; int extts = 0; int flagtest = 0; @@ -188,7 +190,7 @@ int main(int argc, char *argv[]) progname = strrchr(argv[0], '/'); progname = progname ? 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The callback is used to return an error if an offset not supported by the PHC is used in ADJ_OFFSET. The ioctls PTP_CLOCK_GETCAPS and PTP_CLOCK_GETCAPS2 now advertise the maximum offset a PHC's phase control functionality is capable of supporting. Introduce new sysfs node, max_phase_adjustment. Cc: Jakub Kicinski Cc: Shuah Khan Cc: Richard Cochran Cc: Maciek Machnikowski Signed-off-by: Rahul Rameshbabu --- drivers/ptp/ptp_chardev.c | 5 ++++- drivers/ptp/ptp_clock.c | 4 ++++ drivers/ptp/ptp_sysfs.c | 12 ++++++++++++ include/linux/ptp_clock_kernel.h | 5 +++++ include/uapi/linux/ptp_clock.h | 3 ++- tools/testing/selftests/ptp/testptp.c | 6 ++++-- 6 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c index af3bc65c4595..362bf756e6b7 100644 --- a/drivers/ptp/ptp_chardev.c +++ b/drivers/ptp/ptp_chardev.c @@ -136,7 +136,10 @@ long ptp_ioctl(struct posix_clock *pc, unsigned int cmd, unsigned long arg) caps.pps = ptp->info->pps; caps.n_pins = ptp->info->n_pins; caps.cross_timestamping = ptp->info->getcrosststamp != NULL; - caps.adjust_phase = ptp->info->adjphase != NULL; + caps.adjust_phase = ptp->info->adjphase != NULL && + ptp->info->getmaxphase != NULL; + if (caps.adjust_phase) + caps.max_phase_adj = ptp->info->getmaxphase(ptp->info); if (copy_to_user((void __user *)arg, &caps, sizeof(caps))) err = -EFAULT; break; diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c index 790f9250b381..80f74e38c2da 100644 --- a/drivers/ptp/ptp_clock.c +++ b/drivers/ptp/ptp_clock.c @@ -135,11 +135,15 @@ static int ptp_clock_adjtime(struct posix_clock *pc, struct __kernel_timex *tx) ptp->dialed_frequency = tx->freq; } else if (tx->modes & ADJ_OFFSET) { if (ops->adjphase) { + s32 max_phase_adj = ops->getmaxphase(ops); s32 offset = tx->offset; if (!(tx->modes & ADJ_NANO)) offset *= NSEC_PER_USEC; + if (offset > max_phase_adj || offset < -max_phase_adj) + return -ERANGE; + err = ops->adjphase(ops, offset); } } else if (tx->modes == 0) { diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c index f30b0a439470..62a5fafcd407 100644 --- a/drivers/ptp/ptp_sysfs.c +++ b/drivers/ptp/ptp_sysfs.c @@ -27,7 +27,18 @@ static ssize_t var##_show(struct device *dev, \ } \ static DEVICE_ATTR(name, 0444, var##_show, NULL); +#define PTP_SHOW_CB_INT(name, cb) \ +static ssize_t cb##_show(struct device *dev, \ + struct device_attribute *attr, char *page) \ +{ \ + struct ptp_clock *ptp = dev_get_drvdata(dev); \ + return snprintf(page, PAGE_SIZE-1, "%d\n", \ + ptp->info->cb(ptp->info)); \ +} \ +static DEVICE_ATTR(name, 0444, cb##_show, NULL); + PTP_SHOW_INT(max_adjustment, max_adj); +PTP_SHOW_CB_INT(max_phase_adjustment, getmaxphase); PTP_SHOW_INT(n_alarms, n_alarm); PTP_SHOW_INT(n_external_timestamps, n_ext_ts); PTP_SHOW_INT(n_periodic_outputs, n_per_out); @@ -309,6 +320,7 @@ static struct attribute *ptp_attrs[] = { &dev_attr_clock_name.attr, &dev_attr_max_adjustment.attr, + &dev_attr_max_phase_adjustment.attr, &dev_attr_n_alarms.attr, &dev_attr_n_external_timestamps.attr, &dev_attr_n_periodic_outputs.attr, diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h index f8e8443a8b35..1ef4e0f9bd2a 100644 --- a/include/linux/ptp_clock_kernel.h +++ b/include/linux/ptp_clock_kernel.h @@ -82,6 +82,10 @@ struct ptp_system_timestamp { * parameter delta: PHC servo phase adjustment target * in nanoseconds. * + * @getmaxphase: Advertises maximum offset that can be provided + * to the hardware clock's phase control functionality + * through adjphase. + * * @adjtime: Shifts the time of the hardware clock. * parameter delta: Desired change in nanoseconds. * @@ -171,6 +175,7 @@ struct ptp_clock_info { struct ptp_pin_desc *pin_config; int (*adjfine)(struct ptp_clock_info *ptp, long scaled_ppm); int (*adjphase)(struct ptp_clock_info *ptp, s32 phase); + s32 (*getmaxphase)(struct ptp_clock_info *ptp); int (*adjtime)(struct ptp_clock_info *ptp, s64 delta); int (*gettime64)(struct ptp_clock_info *ptp, struct timespec64 *ts); int (*gettimex64)(struct ptp_clock_info *ptp, struct timespec64 *ts, diff --git a/include/uapi/linux/ptp_clock.h b/include/uapi/linux/ptp_clock.h index 1d108d597f66..05cc35fc94ac 100644 --- a/include/uapi/linux/ptp_clock.h +++ b/include/uapi/linux/ptp_clock.h @@ -95,7 +95,8 @@ struct ptp_clock_caps { int cross_timestamping; /* Whether the clock supports adjust phase */ int adjust_phase; - int rsv[12]; /* Reserved for future use. */ + int max_phase_adj; /* Maximum phase adjustment in nanoseconds. */ + int rsv[11]; /* Reserved for future use. */ }; struct ptp_extts_request { diff --git a/tools/testing/selftests/ptp/testptp.c b/tools/testing/selftests/ptp/testptp.c index ae23ef51f198..a162a3e15c29 100644 --- a/tools/testing/selftests/ptp/testptp.c +++ b/tools/testing/selftests/ptp/testptp.c @@ -292,7 +292,8 @@ int main(int argc, char *argv[]) " %d pulse per second\n" " %d programmable pins\n" " %d cross timestamping\n" - " %d adjust_phase\n", + " %d adjust_phase\n" + " %d maximum phase adjustment (ns)\n", caps.max_adj, caps.n_alarm, caps.n_ext_ts, @@ -300,7 +301,8 @@ int main(int argc, char *argv[]) caps.pps, caps.n_pins, caps.cross_timestamping, - caps.adjust_phase); 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No longer do a range check in .adjphase callback implementation. Handled by the ptp stack. Cc: Saeed Mahameed Signed-off-by: Rahul Rameshbabu Acked-by: Richard Cochran --- .../ethernet/mellanox/mlx5/core/lib/clock.c | 31 +++++++++---------- 1 file changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c index 932fbc843c69..973babfaff25 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c @@ -93,17 +93,23 @@ static bool mlx5_modify_mtutc_allowed(struct mlx5_core_dev *mdev) return MLX5_CAP_MCAM_FEATURE(mdev, ptpcyc2realtime_modify); } -static bool mlx5_is_mtutc_time_adj_cap(struct mlx5_core_dev *mdev, s64 delta) +static s32 mlx5_ptp_getmaxphase(struct ptp_clock_info *ptp) { - s64 min = MLX5_MTUTC_OPERATION_ADJUST_TIME_MIN; - s64 max = MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX; + struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); + struct mlx5_core_dev *mdev; - if (MLX5_CAP_MCAM_FEATURE(mdev, mtutc_time_adjustment_extended_range)) { - min = MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MIN; - max = MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX; - } + mdev = container_of(clock, struct mlx5_core_dev, clock); + + return MLX5_CAP_MCAM_FEATURE(mdev, mtutc_time_adjustment_extended_range) ? + MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MAX : + MLX5_MTUTC_OPERATION_ADJUST_TIME_MAX; +} + +static bool mlx5_is_mtutc_time_adj_cap(struct mlx5_core_dev *mdev, s64 delta) +{ + s64 max = mlx5_ptp_getmaxphase(&mdev->clock.ptp_info); - if (delta < min || delta > max) + if (delta < -max || delta > max) return false; return true; @@ -351,14 +357,6 @@ static int mlx5_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta) static int mlx5_ptp_adjphase(struct ptp_clock_info *ptp, s32 delta) { - struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); - struct mlx5_core_dev *mdev; - - mdev = container_of(clock, struct mlx5_core_dev, clock); - - if (!mlx5_is_mtutc_time_adj_cap(mdev, delta)) - return -ERANGE; - return mlx5_ptp_adjtime(ptp, delta); } @@ -734,6 +732,7 @@ static const struct ptp_clock_info mlx5_ptp_clock_info = { .pps = 0, .adjfine = mlx5_ptp_adjfine, .adjphase = mlx5_ptp_adjphase, + .getmaxphase = mlx5_ptp_getmaxphase, .adjtime = mlx5_ptp_adjtime, .gettimex64 = mlx5_ptp_gettimex, .settime64 = mlx5_ptp_settime, From patchwork Wed May 10 20:53:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rahul Rameshbabu X-Patchwork-Id: 13237257 X-Patchwork-Delegate: kuba@kernel.org Received: from lindbergh.monkeyblade.net (lindbergh.monkeyblade.net [23.128.96.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFDC1168D6 for ; Wed, 10 May 2023 20:58:22 +0000 (UTC) Received: from NAM12-MW2-obe.outbound.protection.outlook.com (mail-mw2nam12on2060e.outbound.protection.outlook.com [IPv6:2a01:111:f400:fe5a::60e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C0EA1998 for ; Wed, 10 May 2023 13:57:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kJy32RGFt7UPmQtNCkYqz4Q10C48dlytaXcjDMdHsB3boCYHMNFo7mYaMLIcA+OgKuOCRt+nBpxJKcIQOZ4u18tLvYBopKn68mIGSGq3fdTdJJKsK7AK2B/dGMQu1qpozAO+AO+506ip0zbu+irFaZPUGaUi0g0MJ72VrTziaPnHtHqZvByre2EjCWymYYzCQQWMCnrCUpmwXme1TiJaNGBpG1nUzVwEwTqcJvRyVzj8Cp+BUjHCD2lIUZuBXaXu7FcC7mru+hxh0XQvfAbWj/qa7fcMpEcsulQFLCCi0bUVgXec32Kq2TZ/uRE3i4p1KPWcj3fUsVl0P7tF9KuU5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=CIz6FjYJvU9aKk1zEaIYCJqwEg84tC/Okf7qwQ8z/oI=; b=b5TzZY/FbLx1Ku8+n74a8FC09NNPSA/Jhou/jrUNezDYs9g4OAawwzoaiaXRwbufdmc1r86BNbTJbmmBXFGSyastBrFPifV73kIvuUHsZlLAHHdDj273LJMbIzoUoIy48vO55PMoDd5t4n9FZrfDpneMfRAj+ZTG5EHv5P+obCktNiltMW3E6I1qZDpXQfvnaQ+prkvvJFjPjZcpyO9SE7uw4MsrQKhusxRZKGmef6fJD/n2v2bLnVnzHmW5YCOpJsyU6HHjiCIDpWEfhcWVsYQGKDqPNVEJb8GLRWFmjKN2KPgYBJvqXjwS9OqeZBdQAO0dZiOG1Zq5gpQrKPbfXQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nvidia.com; dmarc=pass action=none header.from=nvidia.com; dkim=pass header.d=nvidia.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CIz6FjYJvU9aKk1zEaIYCJqwEg84tC/Okf7qwQ8z/oI=; b=QTBIIkwTtlALQRDrs7VKfTgA8xiiu62YTEnFvcBeE2b45nc82Uw3tq7ts+x4iWBnbwBS7+hmL07iv0CQE5yrLxzRjQY47NE8i2NsTxXPZU4OWVkxUOtIi+qX7lGMjKGSa7mUpSvPH9CP9i0jreA1DRTHVqDm5zeKLoswmbgZMjZB6mNB+3QUl2czfDJrmkRdlJ4uaB2POaK5XkaM3ULTEyqaJc9R5wzPycudOA4gbMmi/Bo7ze+hk+gpOEInUoACOGVNq789jyowzYG8ULKZKxkguofNXTs/C9R1L+ZmyAvUncGpcEGCsLvLo7fWrIwLQj5VS5pG2+Foh4X5NE70hQ== Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from BYAPR12MB2743.namprd12.prod.outlook.com (2603:10b6:a03:61::28) by MW5PR12MB5624.namprd12.prod.outlook.com (2603:10b6:303:19d::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6387.18; Wed, 10 May 2023 20:54:00 +0000 Received: from BYAPR12MB2743.namprd12.prod.outlook.com ([fe80::de5a:9000:2d2f:a861]) by BYAPR12MB2743.namprd12.prod.outlook.com ([fe80::de5a:9000:2d2f:a861%7]) with mapi id 15.20.6363.033; Wed, 10 May 2023 20:53:59 +0000 From: Rahul Rameshbabu To: netdev@vger.kernel.org Cc: Saeed Mahameed , Gal Pressman , Tariq Toukan , "David S. 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Cc: Richard Cochran Cc: Vincent Cheng Signed-off-by: Rahul Rameshbabu --- drivers/ptp/ptp_clockmatrix.c | 36 +++++++++++++++++------------------ drivers/ptp/ptp_clockmatrix.h | 2 +- 2 files changed, 18 insertions(+), 20 deletions(-) diff --git a/drivers/ptp/ptp_clockmatrix.c b/drivers/ptp/ptp_clockmatrix.c index c9d451bf89e2..f6f9d4adce04 100644 --- a/drivers/ptp/ptp_clockmatrix.c +++ b/drivers/ptp/ptp_clockmatrix.c @@ -1692,14 +1692,23 @@ static int initialize_dco_operating_mode(struct idtcm_channel *channel) /* PTP Hardware Clock interface */ /* - * Maximum absolute value for write phase offset in picoseconds - * - * @channel: channel - * @delta_ns: delta in nanoseconds + * Maximum absolute value for write phase offset in nanoseconds * * Destination signed register is 32-bit register in resolution of 50ps * - * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 + * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 ps + * Represent 107374182350 ps as 107374182 ns + */ +static s32 idtcm_getmaxphase(struct ptp_clock_info *ptp __always_unused) +{ + return MAX_ABS_WRITE_PHASE_NANOSECONDS; +} + +/* + * Internal function for implementing support for write phase offset + * + * @channel: channel + * @delta_ns: delta in nanoseconds */ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) { @@ -1708,7 +1717,6 @@ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) u8 i; u8 buf[4] = {0}; s32 phase_50ps; - s64 offset_ps; if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) { err = channel->configure_write_phase(channel); @@ -1716,19 +1724,7 @@ static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns) return err; } - offset_ps = (s64)delta_ns * 1000; - - /* - * Check for 32-bit signed max * 50: - * - * 0x7fffffff * 50 = 2147483647 * 50 = 107374182350 - */ - if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS) - offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS; - else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS) - offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS; - - phase_50ps = div_s64(offset_ps, 50); + phase_50ps = div_s64((s64)delta_ns * 1000, 50); for (i = 0; i < 4; i++) { buf[i] = phase_50ps & 0xff; @@ -2048,6 +2044,7 @@ static const struct ptp_clock_info idtcm_caps = { .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, .adjphase = &idtcm_adjphase, + .getmaxphase = &idtcm_getmaxphase, .adjfine = &idtcm_adjfine, .adjtime = &idtcm_adjtime, .gettime64 = &idtcm_gettime, @@ -2064,6 +2061,7 @@ static const struct ptp_clock_info idtcm_caps_deprecated = { .n_ext_ts = MAX_TOD, .n_pins = MAX_REF_CLK, .adjphase = &idtcm_adjphase, + .getmaxphase = &idtcm_getmaxphase, .adjfine = &idtcm_adjfine, .adjtime = &idtcm_adjtime_deprecated, .gettime64 = &idtcm_gettime, diff --git a/drivers/ptp/ptp_clockmatrix.h b/drivers/ptp/ptp_clockmatrix.h index bf1e49409844..7c17c4f7f573 100644 --- a/drivers/ptp/ptp_clockmatrix.h +++ b/drivers/ptp/ptp_clockmatrix.h @@ -18,7 +18,7 @@ #define MAX_PLL (8) #define MAX_REF_CLK (16) -#define MAX_ABS_WRITE_PHASE_PICOSECONDS (107374182350LL) +#define MAX_ABS_WRITE_PHASE_NANOSECONDS (107374182L) #define TOD_MASK_ADDR (0xFFA5) #define DEFAULT_TOD_MASK (0x04) From patchwork Wed May 10 20:53:05 2023 Content-Type: text/plain; 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This change refactors the negation of the offset stored in the register to be after the boundary check of the offset value rather than before. Boundary checking is done based on the intended value rather than its device-specific representation. Cc: Richard Cochran Cc: Min Li Signed-off-by: Rahul Rameshbabu --- drivers/ptp/ptp_idt82p33.c | 18 +++++++++--------- drivers/ptp/ptp_idt82p33.h | 4 ++-- 2 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/ptp/ptp_idt82p33.c b/drivers/ptp/ptp_idt82p33.c index afc76c22271a..057190b9cd3d 100644 --- a/drivers/ptp/ptp_idt82p33.c +++ b/drivers/ptp/ptp_idt82p33.c @@ -978,24 +978,23 @@ static int idt82p33_enable(struct ptp_clock_info *ptp, return err; } +static s32 idt82p33_getmaxphase(__always_unused struct ptp_clock_info *ptp) +{ + return WRITE_PHASE_OFFSET_LIMIT; +} + static int idt82p33_adjwritephase(struct ptp_clock_info *ptp, s32 offset_ns) { struct idt82p33_channel *channel = container_of(ptp, struct idt82p33_channel, caps); struct idt82p33 *idt82p33 = channel->idt82p33; - s64 offset_regval, offset_fs; + s64 offset_regval; u8 val[4] = {0}; int err; - offset_fs = (s64)(-offset_ns) * 1000000; - - if (offset_fs > WRITE_PHASE_OFFSET_LIMIT) - offset_fs = WRITE_PHASE_OFFSET_LIMIT; - else if (offset_fs < -WRITE_PHASE_OFFSET_LIMIT) - offset_fs = -WRITE_PHASE_OFFSET_LIMIT; - /* Convert from phaseoffset_fs to register value */ - offset_regval = div_s64(offset_fs * 1000, IDT_T0DPLL_PHASE_RESOL); + offset_regval = div_s64((s64)(-offset_ns) * 1000000000ll, + IDT_T0DPLL_PHASE_RESOL); val[0] = offset_regval & 0xFF; val[1] = (offset_regval >> 8) & 0xFF; @@ -1175,6 +1174,7 @@ static void idt82p33_caps_init(u32 index, struct ptp_clock_info *caps, caps->n_ext_ts = MAX_PHC_PLL, caps->n_pins = max_pins, caps->adjphase = idt82p33_adjwritephase, + caps->getmaxphase = idt82p33_getmaxphase, caps->adjfine = idt82p33_adjfine; caps->adjtime = idt82p33_adjtime; caps->gettime64 = idt82p33_gettime; diff --git a/drivers/ptp/ptp_idt82p33.h b/drivers/ptp/ptp_idt82p33.h index 8fcb0b17d207..6a63c14b6966 100644 --- a/drivers/ptp/ptp_idt82p33.h +++ b/drivers/ptp/ptp_idt82p33.h @@ -43,9 +43,9 @@ #define DEFAULT_OUTPUT_MASK_PLL1 DEFAULT_OUTPUT_MASK_PLL0 /** - * @brief Maximum absolute value for write phase offset in femtoseconds + * @brief Maximum absolute value for write phase offset in nanoseconds */ -#define WRITE_PHASE_OFFSET_LIMIT (20000052084ll) +#define WRITE_PHASE_OFFSET_LIMIT (20000l) /** @brief Phase offset resolution * From patchwork Wed May 10 20:53:06 2023 Content-Type: text/plain; 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Cc: Richard Cochran Cc: Jonathan Lemon Signed-off-by: Rahul Rameshbabu Acked-by: Vadim Fedorenko --- drivers/ptp/ptp_ocp.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/ptp/ptp_ocp.c b/drivers/ptp/ptp_ocp.c index ab8cab4d1560..20a974ced8d6 100644 --- a/drivers/ptp/ptp_ocp.c +++ b/drivers/ptp/ptp_ocp.c @@ -1124,6 +1124,12 @@ ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm) return -EOPNOTSUPP; } +static s32 +ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info) +{ + return 0; +} + static int ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns) { @@ -1239,6 +1245,7 @@ static const struct ptp_clock_info ptp_ocp_clock_info = { .adjtime = ptp_ocp_adjtime, .adjfine = ptp_ocp_null_adjfine, .adjphase = ptp_ocp_null_adjphase, + .getmaxphase = ptp_ocp_null_getmaxphase, .enable = ptp_ocp_enable, .verify = ptp_ocp_verify, .pps = true,