From patchwork Thu May 11 15:09:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13238131 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 30A9DC77B7F for ; Thu, 11 May 2023 15:10:47 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px7w0-0005Xj-3y; Thu, 11 May 2023 11:10:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px7vt-000555-Mv for qemu-devel@nongnu.org; Thu, 11 May 2023 11:10:17 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px7vm-00027T-4D for qemu-devel@nongnu.org; Thu, 11 May 2023 11:10:17 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3f42bcf5df1so33644825e9.3 for ; Thu, 11 May 2023 08:10:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683817805; x=1686409805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+OT6i+7tCi6iezpIwGJmcpXv13tSv9fa3ejqVOJNCoI=; b=HzWSmtiB32/w4dfIwsO/+Bx3f6HnM40kTgM8WWVueVgTMq36OncOrlQUJoE4eCLXOi 0M8rM8eMNvflDT8Qcyr/1TXWsgSMZfCmHguXckv3f6lhSXOzKgBDszEAIzQv6d701kiE lvy13N77pGY1sPlqn1p8wxK+OXTciGVfylj+9W0YS1p801feVTRG3QFhmmkd2o07hT/q dEgAz/dBdcohMIjivypIEGtd5rtHO/fLag2wOnGmMclHUnMES+3Xj8b/TNjtksdK21fd pkoiuhyZrjTQ25nYC9WW3KACCeI7o+Zk2e5PnJ8VIQvKJScEvCg+t3dQH0g1ZnzA6diC GGmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683817805; x=1686409805; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+OT6i+7tCi6iezpIwGJmcpXv13tSv9fa3ejqVOJNCoI=; b=bVmdPqdz+vBbLzVUeTZhpUt1JeRjG0XnwPsqN2S3gAWwmqg4PWoNvL2Dqyx4/F3COb shgJY94GKqMqO1jc7uBbethvRAIB52aJpUHFC4URcl9pqsTiBR1L/21iqw9rZhRCIxBt gZTI3luzaCXsykxW6IRcfiWwdAWLqIgcpMGcVfaGNuZEZThQk0rJA6k4HKp2Nb92R6OG Nd8AXfuazFFcVgrbLnNptmUFMM1B8sw37VuozwS4IIPRcTzdRiUTkjWCkRd42Ry33mf1 WrD2m10nJeP6+FgKWnBhbk7pDjiZ1/EH1sl3MEfuS8y8qbnlE3SCI+TuMkmpIDET7Q5t ui6w== X-Gm-Message-State: AC+VfDzbhQDRPqsDapvI7/CbCfRJ/erfM5vbP23l8x+0ubFlXZuoXrGJ qEV2piDagVqqZYvLXdnGjbzg6JyQWQA= X-Google-Smtp-Source: ACHHUZ4FHHmEhjQbG9pnuHKknc55z27ILls1GCUv0rX/obemng0C1c4+KLXvaGAHHKzJU8xud2NQoA== X-Received: by 2002:adf:fd83:0:b0:305:f2d5:2a12 with SMTP id d3-20020adffd83000000b00305f2d52a12mr15175071wrr.21.1683817805023; Thu, 11 May 2023 08:10:05 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id e13-20020a5d65cd000000b0030789698eebsm17088387wrw.89.2023.05.11.08.10.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 08:10:04 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne , Richard Henderson Subject: [PATCH v3 1/3] target/openrisc: Allow fpcsr access in user mode Date: Thu, 11 May 2023 16:09:57 +0100 Message-Id: <20230511151000.381911-2-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230511151000.381911-1-shorne@gmail.com> References: <20230511151000.381911-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=shorne@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org As per OpenRISC spec 1.4 FPCSR can be read and written in user mode. Update mtspr and mfspr helpers to support this by moving the is_user check into the helper. Link: https://raw.githubusercontent.com/openrisc/doc/master/openrisc-arch-1.4-rev0.pdf Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- Since v2: - Add reviewed-by - In helper_mfspr bring cpu out of ifdef to avoid replicatig the definition. Originally I left it in the ifdef to avoid having to mix having pointers and the data array defined on the stack. But that's overthinking. Since v1: - Update commit message to remove text about no-existant logic change. target/openrisc/sys_helper.c | 45 ++++++++++++++++------ target/openrisc/translate.c | 72 ++++++++++++++++-------------------- 2 files changed, 66 insertions(+), 51 deletions(-) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ec145960e3..ccdee3b8be 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -29,17 +29,37 @@ #define TO_SPR(group, number) (((group) << 11) + (number)) +static inline bool is_user(CPUOpenRISCState *env) +{ +#ifdef CONFIG_USER_ONLY + return true; +#else + return (env->sr & SR_SM) == 0; +#endif +} + void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) { -#ifndef CONFIG_USER_ONLY OpenRISCCPU *cpu = env_archcpu(env); +#ifndef CONFIG_USER_ONLY CPUState *cs = env_cpu(env); target_ulong mr; int idx; #endif + /* Handle user accessible SPRs first. */ switch (spr) { + case TO_SPR(0, 20): /* FPCSR */ + cpu_set_fpcsr(env, rb); + return; + } + + if (is_user(env)) { + raise_exception(cpu, EXCP_ILLEGAL); + } + #ifndef CONFIG_USER_ONLY + switch (spr) { case TO_SPR(0, 11): /* EVBAR */ env->evbar = rb; break; @@ -187,27 +207,33 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb) cpu_openrisc_timer_update(cpu); qemu_mutex_unlock_iothread(); break; -#endif - - case TO_SPR(0, 20): /* FPCSR */ - cpu_set_fpcsr(env, rb); - break; } +#endif } target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, target_ulong spr) { + OpenRISCCPU *cpu = env_archcpu(env); #ifndef CONFIG_USER_ONLY uint64_t data[TARGET_INSN_START_WORDS]; MachineState *ms = MACHINE(qdev_get_machine()); - OpenRISCCPU *cpu = env_archcpu(env); CPUState *cs = env_cpu(env); int idx; #endif + /* Handle user accessible SPRs first. */ switch (spr) { + case TO_SPR(0, 20): /* FPCSR */ + return env->fpcsr; + } + + if (is_user(env)) { + raise_exception(cpu, EXCP_ILLEGAL); + } + #ifndef CONFIG_USER_ONLY + switch (spr) { case TO_SPR(0, 0): /* VR */ return env->vr; @@ -324,11 +350,8 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd, cpu_openrisc_count_update(cpu); qemu_mutex_unlock_iothread(); return cpu_openrisc_count_get(cpu); -#endif - - case TO_SPR(0, 20): /* FPCSR */ - return env->fpcsr; } +#endif /* for rd is passed in, if rd unchanged, just keep it back. */ return rd; diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 76e53c78d4..43ba0cc1ad 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -819,45 +819,12 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a) static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) { - check_r0_write(dc, a->d); - - if (is_user(dc)) { - gen_illegal_exception(dc); - } else { - TCGv spr = tcg_temp_new(); - - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - if (dc->delayed_branch) { - tcg_gen_mov_tl(cpu_pc, jmp_pc); - tcg_gen_discard_tl(jmp_pc); - } else { - tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); - } - dc->base.is_jmp = DISAS_EXIT; - } + TCGv spr = tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); - } - return true; -} - -static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) -{ - if (is_user(dc)) { - gen_illegal_exception(dc); - } else { - TCGv spr; + check_r0_write(dc, a->d); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - /* For SR, we will need to exit the TB to recognize the new - * exception state. For NPC, in theory this counts as a branch - * (although the SPR only exists for use by an ICE). Save all - * of the cpu state first, allowing it to be overwritten. - */ + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); if (dc->delayed_branch) { tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_discard_tl(jmp_pc); @@ -865,11 +832,36 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); } dc->base.is_jmp = DISAS_EXIT; + } + + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mfspr(cpu_R(dc, a->d), cpu_env, cpu_R(dc, a->d), spr); + return true; +} + +static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) +{ + TCGv spr = tcg_temp_new(); - spr = tcg_temp_new(); - tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); - gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); + if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { + gen_io_start(); } + /* + * For SR, we will need to exit the TB to recognize the new + * exception state. For NPC, in theory this counts as a branch + * (although the SPR only exists for use by an ICE). Save all + * of the cpu state first, allowing it to be overwritten. + */ + if (dc->delayed_branch) { + tcg_gen_mov_tl(cpu_pc, jmp_pc); + tcg_gen_discard_tl(jmp_pc); + } else { + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4); + } + dc->base.is_jmp = DISAS_EXIT; + + tcg_gen_ori_tl(spr, cpu_R(dc, a->a), a->k); + gen_helper_mtspr(cpu_env, spr, cpu_R(dc, a->b)); return true; } From patchwork Thu May 11 15:09:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13238132 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CD5FFC77B7C for ; Thu, 11 May 2023 15:10:48 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px7vw-0005Af-JA; Thu, 11 May 2023 11:10:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px7vt-00054B-Dn for qemu-devel@nongnu.org; Thu, 11 May 2023 11:10:17 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px7vm-00027u-61 for qemu-devel@nongnu.org; Thu, 11 May 2023 11:10:17 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-307c040797bso1269329f8f.3 for ; Thu, 11 May 2023 08:10:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683817806; x=1686409806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=woscPhkVSzEl8I9GHPQdrPr9fWimU19q3FnzxdVnQus=; b=GVco0JmF6YjIS44Dc1aXt1G422QkEYcS3DNxNfooT40ONaa7ntaAdAT59UCcKVYWuD DRls+kLQAPbsS/vhjlkFEtp8Bj2yY2ySt3EPjxdb582+kVYEEJDpBpC9/PN0ClbXNC9a lIXQtOYJYYPewVtUUW/rwWn47w3IQ9BCR1YG6I78tLwwV8isVJOoUGWFfjr1Wmd7UzTf Jgq/YT/Jncj9uOWP3AqkehjLKzcOIcgS372Sp9zS8QHJP5lCMgBNh7nTbcwTp3f0XqIW xKwKPXbUiu+lHyf+0+Ia8OcshyxGZjBsGYOX9EvdxIyfVsNEWWewocy+BO2TsgObR+gu sj5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683817806; x=1686409806; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=woscPhkVSzEl8I9GHPQdrPr9fWimU19q3FnzxdVnQus=; b=ixG5/syH5nwt7Yf++inoqipV4WP0fvhDWENjW0SeFN2md4cYMlwDYOY1cvoPRrliP1 BnEqgAhES5ouUM41qbB78yZDzZSCkwBrFsnaJJz4j8IxahtjNwPL5bSJSeGlBkXLVcRo an9nwLUY8+pGu0Onh0J/otaPcvwIC5xxDmz4kV80CkWiPeLLjPhzGubCnIb2FJVueFSv O747Qs6h8udfkcS5X3uRLwDOkL8Ra2qLDxtCkDwSttkCOm95JXyxChxCighaXQsCB+tl C/d2oK38XG+9PKuhd7Qglf6SgTMUxVN8Q+0bwAifq+qxYfxdjSnx3sH+Zfy6wMh4qDI/ YS/g== X-Gm-Message-State: AC+VfDwmkNWQeyySxD+49LoXmjZ24yYpfU84vrWFsUiOxRDyDtNk2ISF UkBHhpFCxt/JxdWUicg6lgfpYBkftUY= X-Google-Smtp-Source: ACHHUZ6pZxkH20q8pvuG9JNq8nxaz7BTjcYoa/jpxSw7s4UDtpgaFxEor38jIkCDVTvyDWpe7nYCeA== X-Received: by 2002:a5d:6285:0:b0:307:b9da:1547 with SMTP id k5-20020a5d6285000000b00307b9da1547mr5069301wru.12.1683817806426; Thu, 11 May 2023 08:10:06 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id z13-20020adfd0cd000000b0030631a599a0sm20603811wrh.24.2023.05.11.08.10.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 08:10:05 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne , Richard Henderson Subject: [PATCH v3 2/3] target/openrisc: Set PC to cpu state on FPU exception Date: Thu, 11 May 2023 16:09:58 +0100 Message-Id: <20230511151000.381911-3-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230511151000.381911-1-shorne@gmail.com> References: <20230511151000.381911-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=shorne@gmail.com; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Store the PC to ensure the correct value can be read in the exception handler. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- Since v2: - Add reviewed-by Since v1: - Use function do_fpe (similar to do_range) to raise exception. target/openrisc/fpu_helper.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/target/openrisc/fpu_helper.c b/target/openrisc/fpu_helper.c index f9e34fa2cc..8b81d2f62f 100644 --- a/target/openrisc/fpu_helper.c +++ b/target/openrisc/fpu_helper.c @@ -20,8 +20,8 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "exception.h" #include "fpu/softfloat.h" static int ieee_ex_to_openrisc(int fexcp) @@ -45,6 +45,15 @@ static int ieee_ex_to_openrisc(int fexcp) return ret; } +static G_NORETURN +void do_fpe(CPUOpenRISCState *env, uintptr_t pc) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = EXCP_FPE; + cpu_loop_exit_restore(cs, pc); +} + void HELPER(update_fpcsr)(CPUOpenRISCState *env) { int tmp = get_float_exception_flags(&env->fp_status); @@ -55,7 +64,7 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env) if (tmp) { env->fpcsr |= tmp; if (env->fpcsr & FPCSR_FPEE) { - helper_exception(env, EXCP_FPE); + do_fpe(env, GETPC()); } } } From patchwork Thu May 11 15:09:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stafford Horne X-Patchwork-Id: 13238133 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8E008C77B7F for ; Thu, 11 May 2023 15:11:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1px7vy-0005Lh-0C; Thu, 11 May 2023 11:10:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1px7vu-00058f-MU for qemu-devel@nongnu.org; Thu, 11 May 2023 11:10:18 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1px7vn-00029g-6s for qemu-devel@nongnu.org; Thu, 11 May 2023 11:10:18 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f41dceb9d1so60658325e9.1 for ; Thu, 11 May 2023 08:10:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1683817808; x=1686409808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H53SzrgO3ToHMUxDNY/DRv16525yykIj2GicLYBw9HE=; b=hhbOXIpv8hae4f1/pgUX5pZtIlTUIB7ChkXXaTzwl1HzlWbRmgQ4RNs/FY1X7ExvMg K4HKVAmaaM6pwgOqih5Zc57OvS/6ynVkPEszdYTgtkWLCddYDabnAy3ZqVQV+SN6NUTN lMW9qi42i3q0jtgLMMjIFEoIkdZ6To0GWQeHiLMVN2PmnOcnw21LCa903L2f2PAl+oL6 im+5OAQbDLAFGdGuCEQ1zwuu1JmKhwTvOFQwgYYQfnr0yZlAFKckAQg39wi6ZotjVPKe MlwQzwVSL9QEasJ4+6WCjTElD0fhfRv6cTYzy37jMzd0CGOSE6mG7XkSJeCgzN0icozE 83Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683817808; x=1686409808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H53SzrgO3ToHMUxDNY/DRv16525yykIj2GicLYBw9HE=; b=DdNEV26vER9nQ3XzmBR5Duv7VcvcIZshP5Ssywl6J1JYBA0iZeGlWJ+HHYHh3//tPr c329xLANTLbz/zZcyq6LdnxZyDtUiSX3FYDhnHN2Yz9l0GjGseR/yJYtpKVgVIlQCey5 8gqKSEDjlyVhlSyR2prz+5Tpla3A7q8lj4hSY6R8OVlPrSsoioESVoFd6sgfhdaioFbO l5wr/QGpM3SzGXko2xH2SRV/AJur5fPMf25J9cxDPLU4uAY2/MKo84u6ei/24GD8yJzW X4/e9i9EXPikZ26VRiWPlpv+ZYgjsoN01g7vT72Zu2b1APUZVUhVENbauuCJgGM0M/9+ 2UGA== X-Gm-Message-State: AC+VfDwP7Roz7kGbpvRiMEKv9wjFTDJshs5dAIkq+NnpIVWw2juooi5+ aZXPp4mpjo51oeZsgk7idEEw8egn83E= X-Google-Smtp-Source: ACHHUZ4DHwv/BLI291DFdbNZ5tWNK0c7ay1bRzeYlHINJGOP8kdOrTCbBv7xRNet7znJrRPZqIvNDA== X-Received: by 2002:a05:600c:2047:b0:3f4:2452:9675 with SMTP id p7-20020a05600c204700b003f424529675mr10279607wmg.0.1683817807960; Thu, 11 May 2023 08:10:07 -0700 (PDT) Received: from localhost (cpc1-brnt4-2-0-cust862.4-2.cable.virginm.net. [86.9.131.95]) by smtp.gmail.com with ESMTPSA id d10-20020a1c730a000000b003f325f0e020sm25834044wmb.47.2023.05.11.08.10.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 08:10:07 -0700 (PDT) From: Stafford Horne To: QEMU Development Cc: Linux OpenRISC , Stafford Horne , Richard Henderson Subject: [PATCH v3 3/3] target/openrisc: Setup FPU for detecting tininess before rounding Date: Thu, 11 May 2023 16:09:59 +0100 Message-Id: <20230511151000.381911-4-shorne@gmail.com> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230511151000.381911-1-shorne@gmail.com> References: <20230511151000.381911-1-shorne@gmail.com> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=shorne@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org OpenRISC defines tininess to be detected before rounding. Setup qemu to obey this. Signed-off-by: Stafford Horne Reviewed-by: Richard Henderson --- Since v2: - Add reviewed-by Since v1: - Remove setting default NaN behavior. target/openrisc/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 0ce4f796fa..61d748cfdc 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -22,6 +22,7 @@ #include "qemu/qemu-print.h" #include "cpu.h" #include "exec/exec-all.h" +#include "fpu/softfloat-helpers.h" #include "tcg/tcg.h" static void openrisc_cpu_set_pc(CPUState *cs, vaddr value) @@ -90,6 +91,9 @@ static void openrisc_cpu_reset_hold(Object *obj) s->exception_index = -1; cpu_set_fpcsr(&cpu->env, 0); + set_float_detect_tininess(float_tininess_before_rounding, + &cpu->env.fp_status); + #ifndef CONFIG_USER_ONLY cpu->env.picmr = 0x00000000; cpu->env.picsr = 0x00000000;